Patent Application
20090073758
1. Field of the Invention
The embodiments of the invention provide static random access memory (SRAM) cells with asymmetric floating-body pass-gate transistors.
2. Description of the Related Art
A typical static random access memory (SRAM) cell ideally includes a balanced pair of cross-coupled inverters storing a single data bit with a high at the output of one inverter and a low at the output of the other. A pair of pass-gates (also ideally, a balanced pair of FETs) selectively connect the complementary outputs of the cross-coupled inverters to a corresponding complementary pair of bit lines. A word line connected to the gates of the pass-gate FETs selects connecting the cell to the corresponding complementary pair of bit lines. During a write, the pass-gates are turned on and the bit line contents are coupled to the cross-coupled inverters, which fight the switch until the cell voltages cross and the cross-coupled inverters take over. Typically, most of the switching is done by cell NFETs, because the off-PFET does not turn on until the high-side (at the on-PFET) is pulled at least to the PFET threshold below the supply voltage, perhaps as much as ⅓ or ½ or more of the supply voltage. Similarly, during a read, each cell on the selected word line couples its contents to its corresponding bit line pair through NFET pass-gates. Since the bit line pair is typically pre-charged to some common voltage, initially, the internal (to the cell) low voltage rises until one of the bit line pairs drops sufficiently to develop a small difference signal (e.g., 50 mV). Thus, in these conventional cells, the NFETs did most, if not all of the switching and so, considerable design effort is expended tweaking cell NFET sizes to improve read and write performance.
There are three factors that limit SRAM cells soft yields. These factors include writability, readability, and stability. However, there is a trade-off among the three constraints. The prior art fails to provide a method and structure to improve these three factors simultaneously.
The embodiments of the invention provide SRAM cells with asymmetric floating-body pass-gate transistors. More specifically, a semiconductor device includes an SRAM cell, a first pass-gate transistor, and a second pass-gate transistor. The first pass-gate transistor is connected to a first side of the SRAM cell, wherein the first pass-gate transistor comprises a first drain region and a first source region. The second pass-gate transistor is connected to a second side of the SRAM cell, wherein the second side is opposite the first side. The second pass-gate transistor comprises a second source region and a second drain region.
Furthermore, the first pass-gate transistor comprises a first channel region; and, the second pass-gate transistor comprises a second channel region. The first channel region and the second channel region each comprise a xenon implant. Moreover, the first source region and/or the second source region comprise a xenon implant. The first drain region and the second drain region each lack a xenon implant. The xenon implant in the first source region and/or the second source region and the lack of the xenon implant in the first and second drain regions cause an asymmetric floating body effect in the first pass-gate transistor and/or the second pass-gate transistor.
The first pass-gate transistor is positioned between a first bit line and a first internal node of the SRAM cell, wherein the first drain region of the first pass-gate transistor is tied with the first bit line. Moreover, the first source region of the first pass-gate transistor is tied with the first internal node of the SRAM cell. The second pass-gate transistor is positioned between a second bit line and a second internal node of the SRAM cell, wherein the second drain region of the second pass-gate transistor is tied with the second bit line. Further, the second source region of the second pass-gate transistor is tied with the second internal node of the SRAM cell. Additionally, the first pass-gate transistor comprises a higher threshold-voltage and a lower drive current relative to the second pass-gate transistor.
The embodiments of the invention also provide a method of forming the semiconductor device. The method begins by simultaneously forming a first pass-gate transistor and a second pass-gate transistor adjacent an SRAM cell. This includes protecting drain regions of the first pass-gate transistor and the second pass-gate transistor with masks to avoid implantation of xenon within the drain regions.
After protecting the drain regions with the masks, the method implants xenon implants into source regions of the first pass-gate transistor and the second pass-gate transistor. If the drain regions comprise a higher voltage potential than the source regions, the xenon implants increase the threshold voltage of the first pass-gate transistor and the second pass-gate transistor. If the source regions comprise a higher voltage potential than the drain regions, the xenon implants decrease the threshold voltage of the first pass-gate transistor and the second pass-gate transistor.
After protecting the drain regions with the masks and before removing the masks, the method also implants xenon implants into channel regions of the first pass-gate transistor and the second pass-gate transistor. Subsequently, the masks are removed.
Accordingly, the embodiments of the invention improve SRAM yields via asymmetric floating-body pass-gate transistors. This provides benefits in SOI technologies with no trade-off on power and performance. Methods for forming the asymmetric pass-gate transistors are also provided with more advantage on higher voltage and higher frequency. There is no area penalty and no process adjusting penalty due to straight-forward implementation.
More specifically, an asymmetric floating-body effect is accomplished via an asymmetric xenon implant (i.e., on the source side only). This effect dynamically strengthens or weakens the pass-gates in favor of the stability and writability without degradation on readability. As more fully described below, in the read mode, the left pass-gate is weakened, which helps the stability; while in the write mode, the right pass-gate is strengthened, which helps the writability.
These and other aspects of the embodiments of the invention will be better appreciated and understood when considered in conjunction with the following description and the accompanying drawings. It should be understood, however, that the following descriptions, while indicating preferred embodiments of the invention and numerous specific details thereof, are given by way of illustration and not of limitation. Many changes and modifications may be made within the scope of the embodiments of the invention without departing from the spirit thereof, and the embodiments of the invention include all such modifications.
The embodiments of the invention will be better understood from the following detailed description with reference to the drawings, in which:
The embodiments of the invention and the various features and advantageous details thereof are explained more fully with reference to the non-limiting embodiments that are illustrated in the accompanying drawings and detailed in the following description. It should be noted that the features illustrated in the drawings are not necessarily drawn to scale. Descriptions of well-known components and processing techniques are omitted so as to not unnecessarily obscure the embodiments of the invention. The examples used herein are intended merely to facilitate an understanding of ways in which the embodiments of the invention may be practiced and to further enable those of skill in the art to practice the embodiments of the invention. Accordingly, the examples should not be construed as limiting the scope of the embodiments of the invention.
Due to the nature of planar process of CMOS device technology, transistors are typically designed with symmetrical source and drain. To achieve higher performance in a limited biasing range (e.g., the source voltage always biased lower than the drain voltage on NFETs), some transistors implement asymmetric doping profile at source and drain sides. However, these designs sacrifice the device performance (e.g., drain-induced-barrier-lowering and short channel effect) if the biased voltages of source and drain are swapped, and are not suitable for pass-gate logic applications. The embodiments of the invention provide a NFET with the asymmetric source and drain diode leakages that induce asymmetric floating-body effect. This design exhibits asymmetric behavior (e.g., higher drive current when drain voltage is higher than source voltage, lower drive current vice versa) in pass-gate application without degrading device performance.
Accordingly, the embodiments of the invention improve SRAM yields via asymmetric floating-body pass-gate transistors. This provides benefits in SOI technologies with no trade-off on power and performance. Methods for forming the asymmetric pass-gate transistors also provide advantages for higher voltage and higher frequency devices. There is no area penalty and no process adjusting penalty due to the straight-forward implementation disclosed herein.
Referring to
If diode leakage at the source region 130 (ISB) is stronger than diode leakage at the drain region 140 (IDB), then due to body potential difference caused by asymmetrical floating body effect, the asymmetrical pass-gate transistor 100 (e.g., n-type field effect transistor) exhibits lower threshold voltage as biasing Vsd=Vdd than as biasing Vds=Vdd. Vdd represents a positive applied voltage, and is also referred as the applied voltage on the bit line (BL) and word line (WL) of an SRAM. Moreover, Vsd is the voltage between the source region 130 to the drain region 140. If the voltage potential at the source region 130 is higher than the voltage potential at the drain region 140, then the Vsd is positive. Otherwise, the Vsd is negative. Vds represents the voltage between the drain region 140 to the source region 130. If the voltage potential at the drain region 140 is higher than the voltage potential at source region 130, then the Vds is positive. Otherwise, the Vds is negative.
Referring now to
Node 206 of the SRAM cell 200 is applied at a positive voltage (Vcs); and, node 208 of the SRAM cell 200 is connected to the GND. The SRAM cell 200 includes a first inverter 212, having a first transistor 214 and a second transistor 216. Additionally, the SRAM cell 200 includes a second inverter 222, having a third transistor 224 and a fourth transistor 226.
The bit line BL (node 237) is connected to the drain side 236 of pass-gate transistor 210 (also referred to herein as the “first pass-gate transistor”), and the complementary bit line BL (node 247) is connected to the drain side 246 of pass-gate transistor 220 (also referred to herein as the “second pass-gate transistor”). Further, the word line WL (node 242) is connected to the gates of both pass-gates 210 and 220.
The voltages applied to the drains (node 236 and 246) of pass-gates transistors 210 and 220, respectively, can be greater to or less than the voltage applied to the sources (node 238 and 248) of pass-gates transistors 210 and 220, respectively.
Referring now to
The SOI region 520 includes a source region 540 adjacent to the STI region 530 and a drain region 550 adjacent to the STI region 532. The SOI region also includes a channel region 560 between the source region 540 and the drain region 550. Further, a gate 570 is above the channel region, wherein the gate 570 can be formed from polysilicon.
A mask 580 is positioned on the drain region 550 and the STI region 532. As such, a xenon implantation process is blocked from implanting within the drain region 550; whereas the xenon implantation process is capable of implanting xenon 590 within the source region 540 and the channel region 560.
Accordingly, the embodiments of the invention provide SRAM cells with asymmetric floating-body pass-gate transistors. More specifically, a semiconductor device includes an SRAM cell, a first pass-gate transistor, and a second pass-gate transistor. The first pass-gate transistor is connected to a first side of the SRAM cell, wherein the first pass-gate transistor comprises a first drain region and a first source region. The second pass-gate transistor is connected to a second side of the SRAM cell, wherein the second side is opposite the first side. The second pass-gate transistor comprises a second source region and a second drain region.
Furthermore, the first pass-gate transistor comprises a first channel region; and, the second pass-gate transistor comprises a second channel region. The first channel region and the second channel region each comprise a xenon implant. Moreover, the first source region and/or the second source region comprise a xenon implant. The first drain region and the second drain region each lack a xenon implant. The xenon implant in the first source region and/or the second source region and the lack of the xenon implant in the first and second drain regions cause an asymmetric floating body effect in the first pass-gate transistor and/or the second pass-gate transistor.
The first pass-gate transistor is positioned between a first bit line and a first internal node of the SRAM cell, wherein the first drain region of the first pass-gate transistor is tied with the first bit line. Moreover, the first source region of the first pass-gate transistor is tied with the first internal node of the SRAM cell. The second pass-gate transistor is positioned between a second bit line and a second internal node of the SRAM cell, wherein the second drain region of the second pass-gate transistor is tied with the second bit line. Further, the second source region of the second pass-gate transistor is tied with the second internal node of the SRAM cell. Additionally, the first pass-gate transistor comprises a higher threshold-voltage and a lower drive current with respect to the second pass-gate transistor.
After protecting the drain regions with the masks, in item 720, the method implants xenon implants into source regions of the first pass-gate transistor and the second pass-gate transistor. If the drain regions comprise a higher voltage potential than the source regions, the xenon implants increase a threshold voltage of the first pass-gate transistor and the second pass-gate transistor (item 730). If the source regions comprise a higher voltage potential than the drain regions, the xenon implants decrease the threshold voltage of the first pass-gate transistor and the second pass-gate transistor (item 740).
After protecting the drain regions with the masks and before removing the masks, in item 750, the method also implants xenon implants into channel regions of the first pass-gate transistor and the second pass-gate transistor. Subsequently, in item 760, the masks are removed.
Accordingly, the embodiments of the invention improve SRAM yields via asymmetric floating-body pass-gate transistors. This provides benefits in SOI technologies with no trade-off on power and performance. Methods for forming the asymmetric pass-gate transistors also provide advantages for higher voltage and higher frequency devices. There is no area penalty and no process adjusting penalty due to the straight-forward implementation disclosed herein.
The foregoing description of the specific embodiments will so fully reveal the general nature of the invention that others can, by applying current knowledge, readily modify and/or adapt for various applications such specific embodiments without departing from the generic concept, and, therefore, such adaptations and modifications should and are intended to be comprehended within the meaning and range of equivalents of the disclosed embodiments. It is to be understood that the phraseology or terminology employed herein is for the purpose of description and not of limitation. Therefore, while the embodiments of the invention have been described in terms of preferred embodiments, those skilled in the art will recognize that the embodiments of the invention can be practiced with modification within the spirit and scope of the appended claims.
