This invention relates to metal oxide semiconductor material for use in channel layers of semiconductor devices, especially in the back channel etch (BCE) type of thin film transistor (TFT) devices.
In thin film semiconductor devices such as thin film transistors (TFTs), the devices include spaced apart source and drain areas that conduct through a channel layer positioned therebetween. At least one gate insulator and gate electrode are positioned above and/or below the channel layer, to control the conduction. In many applications TFTs are used where high heat cannot be tolerated during fabrication and, thus, a semiconductor must be used that can be deposited at relatively low temperatures (e.g. room temperature) but which still has relatively high mobility and with sufficient operation stability.
There is a strong interest in metal oxide semiconductor because of its high carrier mobility, light transparency and low deposition temperature. The high carrier mobility expands applications to higher performance domains that require higher frequency or higher current. The light transparency eliminates the need for a light shield in display and sensor active matrices. The low deposition temperature enables application to flexible electronics on plastic substrates.
The unique features of metal oxide semiconductors are: (1) carrier mobility is less dependent on grain size of films, that is, high mobility amorphous or nanocrystalline metal oxide is possible; (2) density of surface states is low and enables easy field effect for TFTs, this is contrary to covalent semiconductors (such as Si or a-Si) where surface states have to be passivated by hydrogen; and (3) mobility strongly depends on the volume carrier density. In order to achieve high mobility for high performance applications, the volume carrier density of the metal oxide channel should be high and thickness of the metal oxide film should be small (e.g. <100 nm and preferably <50 nm).
However, a major deficiency of metal oxide semiconductors is stability and the tendency to become polycrystalline at higher temperatures. Popular metal oxides, such as zinc oxide, indium oxide, tin-oxide, gallium oxide and composite/blend made of their combinations such as indium tin oxide, indium zinc oxide, indium gallium zinc oxide, are not very stable and become polycrystalline at moderate temperatures (i.e. greater than approximately 400° C.). Polycrystalline semiconductor metal oxides with large crystalline grains (e.g., approaching micron grain size) are not desirable in semiconductor devices for several reasons. For example, the characteristics of transistors formed in polycrystalline semiconductor metal oxides can vary, even between adjacent devices in an array, because of the variation in crystal size and position. To better understand this problem, in a conduction area under a sub-micron gate each different transistor can include from one or two poly-silicon crystalline grains to several crystalline grains and the different number of crystals in the conduction area will produce different characteristics. The dimensions and their physical characteristics among different grains are also different. Another reason for favoring thin amorphous/nanocrystalline semiconductor layer is its robustness to mechanical bending. Such amorphous/nanocrystalline film is ideal semiconductor material for flexible electronic devices.
The stability of metal oxide thin film transistors (TFTs) depends strongly on processing temperatures. For TFT processed at high temperatures, the traps in the bulk semiconductor layer and at the interface or interfaces between the gate insulator and the semiconductor layer and/or between the passivation layer and the semiconductor layer can be reduced. For applications such as active matrix organic light emitting devices (AMOLED) extreme stability is required. It is advantageous to take the metal oxide TFTs to high temperatures, generally between 250° C. and 700° C., during processing. Meanwhile it is desirable to maintain the amorphous/nanocrystalline nature of the metal oxide at these processing temperatures.
The performance and stability of metal oxide TFTs also strongly depends on their structures and processing conditions. Generally, etch-stop type of TFTs have better stability than the BCE type of TFTs due to the fact that the former structure offers protection of the metal oxide channel during etching of source/drain metal, resulting in less damage to the top surface of the channel layer. However, the BCE type of TFTs are favored from the point of view of manufacturing efficiency and cost, due to one less deposition/patterning cycle. Therefore, there is currently a dilemma or trade-off between the selection of etch-stop type or BCE type of metal-oxide TFTs for manufacturing.
Further, the stability of metal oxide TFTs also strongly depends on the material and processing condition used for depositing gate insulator and source/drain metal. From the point of view of manufacturing efficiency and throughput, silicon nitride (SiNx) processed by PECVD is preferred as the gate insulator. However hydrogen content is usually very high when SiNx is deposited with the existing PECVD tools at the display manufacturing lines (for such SiNx, it is sometimes denoted as SiNx:H). The diffusion of hydrogen from the gate insulator into the metal oxide channel usually causes serious deterioration of the TFT stability. By choosing silicon oxide (SiOx), or SiONx as gate insulator material, the TFT stability can usually be improved, but the production efficiency is significantly decreased due to much longer time required for SiOx or SiONx deposition. Additionally, since the gate insulator layer made by PECVD SiOx or SiONx is more porous than SiNx, additional problems arise when copper is used as gate metal in applications requiring large-size and high resolution displays. Basically, copper will more easily diffuse through the SiOx or SiONx gate insulator into the metal oxide channel, deteriorating TFT stability. Similar deterioration of TFT stability due to copper diffusion into the metal oxide channel also occurs when copper is used in the source/drain metal (or stack of metals).
It would be highly advantageous, therefore, to remedy the foregoing and other deficiencies inherent in the prior art.
Accordingly, it is an object of the present invention to provide a new and improved metal oxide semiconductor material for a TFT channel layer.
Another object of the invention is to provide a new and improved metal oxide semiconductor material with improved stability and has less tendency to become polycrystalline at process temperatures required for high stability.
Another object of the invention is to provide a new and improved metal oxide semiconductor material with improved stability, high carrier mobility, and good control of oxygen vacancies.
Another object of the invention is to provide a new and more robust metal oxide semiconductor such that it can withstand the process damage associated with the back channel etch (BCE) process (either dry etch or wet etch of source/drain).
Another objective of the invention is to provide a new and improved metal-oxide TFT with less process steps, which are compatible with process tools well-established in a-Si TFT manufacture line.
Another object of the invention is to provide a new and more robust metal oxide semiconductor such that it is less susceptible to the deleterious effects of hydrogen diffusion from the gate insulator (GI) or copper diffusion from the gate metal or source/drain metal, into the channel region, thereby greatly improving the stability of the TFT.
Another object of the invention is to provide a stable thin film transistor and thin film circuit comprising such with the channel layer made of such stable metal oxide semiconductor channel.
Briefly, to achieve the desired objects of the instant invention in accordance with a preferred embodiment thereof, a stable amorphous/nanocrystalline metal oxide material is provided for use as a semiconductor in semiconductor devices, the material includes a composite/mixture of an amorphous/nanocrystalline semiconductor ionic metal oxide and an amorphous/nanocrystalline non-semiconducting covalent metal/non-metal oxide. The stable amorphous/nanocrystalline metal oxide material is represented by one of the formula XOaYOb, and X—O—Y, where YO is an amorphous/nanocrystalline insulating covalent metal/non-metal oxide and XO is an amorphous/nanocrystalline semiconductor ionic metal oxide. The covalent metal/non-metal oxide, YO, tends to be amorphous/nanocrystalline and insulating when formed in its single phase. The ionic metal oxide, XO, tends to be polycrystallized with grain size of micron scale at process temperature and behaves as a semiconductor with energy gap larger than 2 eV when formed in its single phase. Adding YO into the composite/blend of XOaYOb prevents XO from polycrystallizing into micron size grains and results in amorphous/nanocrystalline semiconductor composite/blend film during film forming and following process steps, and thus results in a stable electronic device during storage and operation.
The desired objects of the instant invention are further achieved in a thin film semiconductor device having a semiconductor layer including a composite/mixture of an amorphous/nanocrystalline semiconductor ionic metal oxide and an amorphous/nanocrystalline non-semiconducting covalent metal/non-metal oxide. A pair of terminals is positioned in communication with the semiconductor layer and defines a conductive channel, and a gate terminal is positioned in communication with the conductive channel and further positioned to control conduction of the channel.
The invention further includes a method of fabricating metal oxide thin film transistors with a back channel etch (BCE) process by exploiting the chemically-robust (S/D etch-resistant) nature of the metal oxide channel made by blending/mixing a semiconductor ionic metal oxide with an amorphous/nanocrystalline non-semiconducting covalent metal/non-metal oxide. Also included in the method is a post-BCE passivation process and structure which enables effective protection of the channel from ambient moisture and light through use of multi-layers (including inorganic/inorganic, organic/organic or organic/inorganic combinations) which inhibit moisture accumulation and shield light.
The invention further includes a method of fabricating metal oxide thin film transistors with high process-throughput SiNx gate insulator, by exploiting the chemically-robust (hydrogen resistant) nature of the metal oxide channel made by blending/mixing a semiconductor ionic metal oxide with an amorphous/nanocrystalline non-semiconducting covalent metal/non-metal oxide.
The invention further includes a method of fabricating metal oxide thin film transistors compatible with copper-containing electrodes either as a gate terminal or as source/drain terminals, by exploiting the chemically-robust (copper resistant) nature of the metal oxide channel made by mixing a semiconductor ionic metal oxide with an amorphous/nanocrystalline non-semiconducting covalent metal/non-metal oxide.
The foregoing and further and more specific objects and advantages of the instant invention Will become readily apparent to those skilled in the art from the following detailed description of a preferred embodiment thereof taken in conjunction with the drawings, in Which:
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It will be understood that the above four examples of thin film transistors illustrate only some of the possible embodiments. For example, each of the above examples is a single gate transistor. Double gate transistors, i.e. a gate above and below the channel, are known in conjunction with virtually all of the examples. It is intended that the present invention applies to all possible or potential thin film transistors and other thin film devices, e. g. diodes, etc. Further, for purposes of this disclosure it will be understood that in all of the TFT examples the metal oxide film is designed as being “deposited on the substrate”, even if a film is interposed therebetween.
An alternative name for the TFT structure shown in
When passivation layer 64 is made of inorganic dielectric material, an optional second passivation layer 66 can be added thereover. A dense and/or hydrophobic layer 66 can inhibit moisture in the ambient from penetrating through the passivation layers 66 and 64 to reach the channel 58. Layer 66 can be either an inorganic material such as silicon oxide, silicon nitride or an organic material such as PMMA based polymer, PMGI, polyimide, polysiloxane, or other commercially available insulator polymers, insulting organometallic molecules (such as organo-alumina, organo-tantania, organo-titania, organo-hafnia, organo-zerconia), photoresists, liquid glasses and so on used as planarization layer or bank layer. Photopatternable organic materials and photoresists are preferred when via-holes or other patterns are need for layers 64 and 66.
Layer 66 can also be a class of material categorized as surface-assembled-monolayer (SAM) of organic molecules. One-side of SAM molecules has strong affinity to the passivation layer 64 underneath, the other side of SAM molecules has high hydrophobicity and repulsing to water molecules from the ambient. A multiple layer passivation layer can be achieved with multiple coatings, a process similar to that for a Langmuir-Blodgett film known to experts in the field.
Another class of organic materials called surface promoters (or adhesion promoters) or surface modifiers can also be used in layer 66 and layer 64. Such organic or organometallic molecules are characterized with a saturated carbon chain with one end-group with hydrophobic property and the other side with hydrophilic property. When coating over a metal-oxide channel, the surface promoters passivate the metal-oxide channel with a dense, thin layer with the top surface repulsing moisture in the ambient. Examples of silane-based surface promotors include hexamethyldisilazane (HMDS), and diphenylsilanediol-derivatives (AR 300-80). The former is often processed with a spray coater, or vapor-primer and the later is often processed with a spin-coater, slit coater or slot coater. Examples of organometallic molecule based surface promotors/modifiers include organo-titanium molecules. Such thin films can be formed by a sol-gel or a solution processed by casting, spin-coating, slot-coating, or one of printing methods known to the experts in the arts. Hydrogen and Carbon groups in such organo-metallic molecules can be removed partially or completely with a post-casting annealing process. In the case of hydrogen/carbon full removal, a thin, dense metal-oxide passivation film is formed without damage to the channel layer underneath. An example of forming such a surface modifier layer between photosensing layer and cathode in a photovoltaic cell has been described in Advanced Material, Vol 18, pp 572-576 (2006).
When an organic layer is used for passivation layer 64, an inorganic passivation material (for example, as described for passivation layer 64 above) can be used for optional passivation layer 66.
Combinations of the organic materials described above can also be used for passivation layers 64 and 66 in either stack or blend forms. The thickness of each passivation layer(s) in 64 and 66 can range from a few molecular layer (˜nm) to a few microns. The total thickness of passivation layers 64 and 66 is typically no more than 5 microns.
No matter which passivation material and process is selected, it is preferred to keep the top free-surface of the passivation layer 64 (or 66 when a bi-layer passivation structure is used) hydrophobic. This can be done with a coating process with SAM or surface promotor material, or with a plasma surface treatment with a fluorine based gas (such as CF4 or SF6).
The difference between TFT 50A and TFT 50B is the relative dimensions between the channel layer 58 and the source/drain layer 60/62. In TFT 50A, the channel layer and the outer dimensions of the source/drain layer are different, which are typically made from two mask steps. While in 50B, the outer dimensions of the channel and the source/drain layer are kept the same. Such structure can be achieved with a single photomask step with a half-tone photo-exposure process known to experts in the field. Processes of active matrix liquid crystal display backpanels based on TFT 50A typically involve five mask steps. In contrast, processes of active matrix liquid crystal display backpanels based on TFT 50B typically involve four mask steps. In applications sensitive to process cost, processes related to TFT 50B are preferred. Also in general, less mask process steps also results in better process yield. In addition, when sputter is used for both channel layer (58) and source/drain layer (60, 62), the process for fabricating TFT 50B enables continuous deposition of the metal layer of source 60 and drain 62 over metal oxide semiconductor channel layer 58 without a vacuum break, ensuring a clean interface and superb contact quality between metal oxide semiconductor layer 58 and source 60 and drain 62.
Amorphous/nanocrystalline metal oxide semiconductor materials are desirable for use in the channel layer of semiconductor devices because of their high carrier mobility and device uniformity. They also enable large size, foldable electronic devices due to its superb sustainability under bending. However, metal oxide semiconductors, such as zinc oxide, indium oxide, tin oxide, gallium oxide and combinations thereof, are relatively unstable and have a tendency to become polycrystalline at higher process temperatures. Polycrystalline semiconductor metal oxides are not desirable in semiconductor devices because of the many drawbacks in their structure.
It is known in the art that the channel length of presently standard thin film transistors is less than approximately 5 microns. For purposes of this disclosure the term “amorphous, nanocrystalline, or amorphous/nanocrystalline” is defined as a material with grain size, along the channel length, much less than the channel length of presently standard thin film transistors, e.g. approximately 100 nanometers or less.
Some amorphous/nanocrystalline metal or non-metal oxides, such as aluminum oxide, boron oxide, silicon oxide, magnesium oxide, beryllium oxide, and composites comprising combinations thereof, are very stable and do not become polycrystalline easily at the process temperatures. However, these metal/non-metal oxides are not good semiconductors and cannot be used as the channel layer in semiconductor devices in their normal state.
It has been found that the stability of amorphous/nanocrystalline metal oxide semiconductor materials can be greatly improved by blending/mixing some non-semiconducting amorphous or nanocrystalline metal/non-metal oxides with the ionic metal oxide semiconductor materials. The component of non-semiconducting amorphous/nanocrystalline metal/non-metal oxide prevents the component of ionic metal oxide semiconductor from becoming polycrystalline with large grain sizes, resulting in amorphous/nanocrystalline semiconductor composites/blends/mixtures with all phases and components in amorphous/nanocrystalline structure. In the case of mixtures with multiple phases, because the non-semiconducting amorphous or nanocrystalline metal oxides are virtually non-conducting, it is necessary to provide a continuous network of the amorphous or nanocrystalline metal oxide semiconductor materials through the resulting mixture. Thus, carrier flow is not interrupted by the non-semiconducting amorphous/nanocrystalline metal oxide material mixed with the ionic amorphous/nanocrystalline metal oxide semiconductor materials and mobility of the composite oxide can be high. Thus, the stability of the composite oxides is enhanced by the stable oxide component but the mobility remains high. Further, it will be understood that several different types of non-semiconducting amorphous/nanocrystalline metal oxides with different valences or other characteristics may be included in a composite mixture to achieve different results, at least one result being enhanced stability.
Some typical non-semiconducting amorphous/nanocrystalline metal oxides that can be used in a composite mixture include AlO, SiO, MgO, BeO, BO, and the like, and combinations thereof. In the technical literature, SiO and BO are sometimes called non-metal oxides. Generally, the non-semiconducting amorphous/nanocrystalline metal/non-metal oxides are more covalent in nature with a relatively high energy gap, that is Eg greater than approximately 6 eV. For ease of understanding, the non-semiconducting amorphous/nanocrystalline metal/non-metal oxides may be referred to generically as ‘covalent metal/non-metal oxides’.
Some typical metal oxide semiconductor materials include zinc oxide, indium oxide, tin oxide, gallium oxide, cadmium oxide, tantalum oxide, titanium oxide, tungsten oxide, molybdenum oxide, vanadium oxide, niobium oxide, and the like, and composite/blend/mixture comprising their combinations. Generally, the metal oxide semiconductor materials are more, or practically, ionic in nature with a relatively low energy gap, that is Eg less than approximately 4 eV. For ease of understanding, the semiconducting metal oxides may be referred to generically as ‘ionic metal oxides’. Many amorphous ionic metal oxide films formed at low temperature processes tend to become crystallized under a post annealing at high temperature or under storage at ambient conditions.
Different valence metals, i.e. metals from different groups in the periodic table, and mixtures thereof can be used to enhance stability or desirable semiconductor characteristics in a composite mixture. It will be understood that some covalent metal/non-metal oxides will add more stability because they have a greater tendency not to crystallize (e.g. a higher energy gap). Also, the amount of stable or covalent metal/non-metal oxide added to the composite mixture is determined by the necessity to maintain a continuous network of the amorphous or nanocrystalline metal oxide semiconductor materials.
In the present composite/blend/mixture, the amorphous/nanocrystalline metal oxide semiconductor components are represented by XO and the non-semiconducting amorphous/nanocrystalline metal oxide components are represented by YO. Thus, a formula for the composite/blend/mixture can be described as XOaYOb, where ‘a’ is the amount of amorphous/nanocrystalline metal oxide semiconductor material (ionic metal oxide) in the composite mixture and ‘b’ is the amount of non-semiconducting amorphous/nanocrystalline metal/non-metal oxide material (covalent metal/non-metal oxide) in the composite mixture. In this equation ‘a’ and ‘b’ can be used to describe molecular amount, weight amount, or number of metal-oxide bonds. It should be understood that ‘a’ and ‘b’ are non-zero (greater than zero) and to comply with the requirement that the composite mixture include a continuous network of the amorphous/nanocrystalline metal oxide semiconductor materials, ‘a’ will generally be larger than ‘b’. In certain circumstance, b is larger than a few %, e.g., larger than approximately 3% of the total material (a+b). Also, the amount of amorphous/nanocrystalline semiconductor ionic metal oxide is preferably greater than approximately 17% of the total mixture.
High temperature annealing of such mixture oxide (for example, in process of forming sputter target) often transfer the oxide mixture from multiple phases into a single phase alloy oxide composite/blend (sometimes also called a solid solution). Thin films formed from sputter deposition processes with such target retains such uniform, single phase morphology. One characteristic of such amorphous/nanocrystalline semiconductor oxide is a single oxygen atom bonded to both the metal corresponding to ionic semiconductor oxide X—O (XO) and the metal/non-metal oxide corresponding to covalent insulator oxide, Y—O (YO): i.e., forming X—O—Y bond structure at atomic (sub-nanometer) scale. The chemically stable O—Y bond helps stabilizing the ionic X—O bond and thus, improves the stability of the metal-oxide TFT under storage and during operation under biasing field.
The bonding dissociating energy of such covalent metal-oxide bond, O—Y (YO), is often larger than the ionic metal-oxide bond, X—O (XO), in the mixture/composite. The amorphous/nanocrystalline semiconductor metal oxide composites/blends/mixtures disclosed in this invention provide a new class of stable semiconductor metal-oxide which is of particular importance for electronic device and circuit applications.
One property change that arises from mixing a stable covalent metal oxide with an amorphous or nanocrystalline metal oxide semiconductor material is that the stable covalent metal oxide tends to reduce the number of oxygen vacancies. If oxygen is used during deposition in the normal procedure (i.e. less than 5%), the oxygen vacancies can be substantially reduced and the conduction (mobility) of the composite material can become too low. For example, it has been found that by using oxygen during the deposition, carriers are decreased to less than 1018 carriers per cm3. Thus, the use of oxygen to control the carrier concentration in the composite mixture, while it is possible, is a relatively sensitive process.
Instead of using oxygen to control the carrier concentration during deposition, it has been found that nitrogen (N2) can be used to reduce the carrier concentration. The presence of N2 during deposition can reduce the carrier concentration, but not as strongly as oxygen because nitrogen is less reactive compared to oxygen. Thus, the use of nitrogen is less sensitive and it is easier to achieve the desired carrier concentration.
In addition to using N2 gas during deposition, it has also found that a post annealing under N2, O2 or mixture of both after TFT process steps (see
Thus, a new and improved metal oxide semiconductor material has been disclosed that has improved stability and has less tendency to become polycrystalline at higher temperatures. Also, the new and improved metal oxide semiconductor material has high carrier mobility and good control of oxygen vacancies.
The stable metal-oxide disclosed in this invention is ideal for use as the channel layer in a TFT. In one special case, it enables the production of a TFT with BCE structures shown in
The stable metal-oxide/metal oxide semiconductor channel is non-reactive to chemical exposures during source/drain metal layer deposition and patterning, non-reactive to the chemical exposures during passivation layer and other following layers, depositions and patterning. The stable metal oxide/metal oxide semiconductor channel layer is also resistant to hydrogen, Cu diffusion from abutting layers above and below during TFT storage and operation.
The stable metal-oxide/metal oxide TFT disclosed in this invention with structures shown in
With a third electrode layer, a TFT with double-gate (both top and bottom gates) can be constructed by combing
In certain applications including AMLCD, it is preferable to optimize the metal-oxide TFT with both high carrier mobility under forward bias and stable performance under reverse gate-to-source/drain bias, both in dark and under light illumination. This could be achieved by tuning the channel composition in a vertical direction. For example, oxygen concentration can be varied vertically by properly annealing the channel in an oxygen rich or oxygen deficient environment.
A bilayer or multiple-layer stack can also be used for the channel with the layer in contact with source and drain with more YO than the layer contacting the gate insulator layer: i.e., ‘b’ is higher in the vicinity of channel-to-passivation interface than that in vicinity of channel-to-GI interface.
As an example,
In another application one could minimize charge trapping and TFT sensitivity to light exposure by adopting a XOaYOb channel layer with high YO concentrations near both GI and Passivation interface. In one special case, ‘b’ near channel-to-GI interface can be in range of 0<b<3%, and ‘b’ near channel-to-passivation interface can be substantially larger than 5% (in this description, percentage is defined by b/(a+b)). Such composite change along vertical direction can be achieved by several methods. For example, in the case of forming the channel layer with sputter deposition, the gradient composition change can be achieved by co-deposition with two sputter targets with a proper rate change. In the case of inline or cluster sputter tools in the manufacturing line, the ‘b’ composition change can be achieved by moving the substrate between different deposition zones with a corresponding ‘b’ composition change.
Another approach for arranging a stable XOaYOb channel layer is to take ionic semiconductor XO with two sub components X1-O and X2-O with the following formula: [(X1-O)a1(X2-O)a2]aYOb (a=a1+a2, a+b=1) in which the chemical dissociation energy of X2-O bond is substantially higher than X1-O bond. In the channel layer with [ (X1-O)a1(X2-O)a2]aYOb composite/mixture, one could vary the composition along the vertical direction in the channel layer. For example, the X2-O in the vicinity of channel-GI and channel-passivation interfaces is higher than in the center along the vertical direction. Stack layers can be produced without vac break so that improves channel layer quality is achieved.
Metal-oxide TFTs were also made with the structure and a process flow corresponding to
Various changes and modifications to the embodiment herein chosen for purposes of illustration will readily occur to those skilled in the art. To the extent that such modifications and variations do not depart from the spirit of the invention, they are intended to be included within the scope thereof which is assessed only by a fair interpretation of the following claims.
Having fully described the invention in such clear and concise terms as to enable those skilled in the art to understand and practice the same, the invention claimed is:
This application is a continuation-in-part application of currently pending U.S. application Ser. No. 12/206,615, filed Sep. 8, 2008.
Number | Date | Country | |
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Parent | 12206615 | Sep 2008 | US |
Child | 14829812 | US |