Stack element circuit

Abstract

A circuit including a reference element adapted to provide a reference current and having a control terminal and a first terminal, there being a voltage (Vct) between the control terminal and the first terminal of the reference element, and a plurality of series-connected stack elements, each the stack element including a first terminal connected to a first voltage, and a control tern connected to a second terminal, the stack elements being adapted to receive at least one of the reference current and a multiple of the reference current, the stack elements and the reference element being matched such that a voltage between the control terminal and the first terminal of at least one of the stack elements is generally the same as Vct.

Description

FIELD OF THE INVENTION

The present invention relates generally to circuitry for memory cell arrays, such as circuitry that may be used for voltage regulators for erasable, programmable read only memories (EPROMs), electrically erasable, programmable read only memories (EEPROMs), and flash EEPROM memories, for example.

BACKGROUND OF THE INVENTION

Voltage regulators are circuits useful for providing accurate analog voltages for erasable, programmable read only memories (EPROMs) and other integrated circuits. A voltage regulator may typically comprise a reference voltage, a comparator, a driver and a resistor divider. An example of a prior art voltage regulator is shown in FIG. 1 , and uses a so-called Miller architecture, well known in the art. A comparator GM 1 is connected to the gate of a PMOS (p-channel metal oxide semiconductor) driver GM 2 . The comparator GM 1 is supplied a supply voltage V PP , and compares voltages IP and FB. The comparator GMI adjusts the gate voltage of the PMOS driver GM 2 to equalize voltages IP and FB. The output voltage, OP, is thus a multiple of the input voltage, IP. The multiplication factor is determined by the resistor divider (RD) ratio between OP and FB.

A problem with this type of regulator is that a large current (typically >100 μA) is required across the resistor divider RD in order to establish the multiplication factor. It is possible to make this current arbitrarily small by increasing the resistance of the divider. However, this may have several undesirable effects. First, the drive capability of the regulator may be lowered. Second, increasing the resistance may require significant silicon area. Third, the speed of the feedback is a function of the current, and as such, lowering the current may substantially degrade the regulator's stability.

In EPROM applications, the V PP supply ( FIG. 1 ) is usually a pumped voltage. Pumping from the chip supply (V DD ) to a higher voltage (V PP ) is a process that has a low efficiency. Any current consumption from V PP requires a significantly larger current consumption from V DD , usually by a factor of 5-10. As such, it is critical to conserve current in regulators operating from a boosted source, such as those providing the wordline voltage in EPROMs. In the regulator of FIG. 1 , the resistor divider drains current from the V PP supply, such that a current of 100 μA required across the resistor divider may mean a V DD current of 1 mA.

Accordingly, there is a need for a regulator that has a low current consumption from V PP or another supply, while providing a high drive capability.

SUMMARY OF THE INVENTION

The present invention seeks to provide a stack element circuit that may be used to provide an improved voltage regulator. The present invention may comprise stacked diode-connected transistors that receive a reference current or a multiple thereof from a reference element, which may be a reference transistor. Diode-connected transistors are transistors whose gate is connected to the drain. The diode-connected transistors and the reference element are preferably matched such that a gate-source voltage of the diode-connected transistors is generally the same as the gate-source voltage of the reference element.

There is thus provided in accordance with a preferred embodiment of the present invention a circuit including a reference element adapted to provide a reference current and having a control terminal and a first terminal, there being a voltage (V ct ) between the control terminal and the first terminal of the reference element, and a plurality of series-connected stack elements, each the stack element including a first terminal connected to a first voltage, and a control terminal connected to a second terminal, the stack elements being adapted to receive at least one of the reference current and a multiple of the reference current, the stack elements and the reference element being matched such that a voltage between the control terminal and the first terminal of at least one of the stack elements is generally the same as V ct .

In accordance with a preferred embodiment of the present invention a voltage between the control terminal and the first terminal of each the stack element is generally the same as V ct .

Further in accordance with a preferred embodiment of the present invention one of the first and second terminals comprises an input and the other of the first and second terminals comprises an output, and the output of a first stack element is connected to the input of a subsequent stack element.

Still further in accordance with a preferred embodiment of the present invention the reference element is at a voltage V DD and the stack elements are at voltage V PP wherein V PP ≧V DD .

In accordance with a preferred embodiment of the present invention the stack elements include diode-connected transistors and the reference element includes a transistor, the diode-connected transistors and the reference element being matched such that a gate-source voltage of the diode-connected transistors is generally the same as V ct .

Further in accordance with a preferred embodiment of the present invention the reference element is adapted to have a fixed V ct voltage.

Still further in accordance with a preferred embodiment of the present invention the circuit includes a voltage regulator having an input and an output, wherein the input is a control terminal of the reference element, and the output is an output of a top transistor of the stack, the top transistor being the first of the diode-connected transistors that receives the reference current.

In accordance with a preferred embodiment of the present invention the first terminal includes an input and the second terminal includes an output.

In accordance with a preferred embodiment of the present invention the stack elements and the reference element include NMOS (n-channel metal oxide semiconductor) transistors, and the first terminal includes an input including at least one of a source and bulk, the control terminal includes a gate, and the second terminal includes an output including a drain.

Further in accordance with a preferred embodiment of the present invention the reference element receives a reference voltage at the control terminal and the output generates the reference current.

Still further in accordance with a preferred embodiment of the present invention the stack elements and the reference element include NMOS transistors, wherein for each NMOS transistor, a resistor is connected between a source of the transistor and the first terminal, a bulk of the transistor is connected to at least one of the source and the first terminal, the control terminal includes a gate, the first terminal comprises an input of the stack element and the second terminal includes an output including a drain.

Additionally in accordance with a preferred embodiment of the present invention an input of the reference element is at ground (GND).

In accordance with a preferred embodiment of the present invention an output of the circuit is the output of the top stack element, the top stack element being the first of the stack elements that receives the reference current.

Further in accordance with a preferred embodiment of the present invention a bottom stack element, the bottom stack element being the last of the stack elements that receives the reference current, receives a second reference voltage at its input.

Still further in accordance with a preferred embodiment of the present invention the stack elements and the reference element include NMOS transistors, and the first terminal includes an input including at least one of a source and bulk, the control terminal includes a gate, and the second terminal includes an output including a drain, wherein the reference element receives a reference voltage at the control terminal and the output generates the reference current, wherein an input of the reference element is at ground (GND), wherein an output of the circuit is the output of the top stack element, the top stack element being the first of the stack elements that receives the reference current, and wherein a bottom stack element, the bottom stack element being the last of the stack elements that receives the reference current, receives a second reference voltage at its input.

In accordance with another preferred embodiment of the present invention the first terminal includes an output and the second terminal includes an inputs Further in accordance with a preferred embodiment of the present invention the stack elements and the reference element include PMOS (p-channel metal oxide semiconductor) transistors, and the first terminal includes an output including at least one of a source and bulk, the control terminal includes a gate, and the second terminal includes an input including a drain.

Still further in accordance with a preferred embodiment of the present invention the stack elements and the reference element include PMOS transistors, wherein for each PMOS transistor, a resistor is connected between a source of the transistor and the first terminal, a bulk of the transistor is connected to at least one of the source and the first terminal, the control terminal includes a gate, the first terminal comprises an input of the stack element and the second terminal includes an input including a drain.

Additionally in accordance with a preferred embodiment of the present invention the control terminal and the input of the reference element are at GND.

In accordance with a preferred embodiment of the present invention a reference voltage is placed at the output of the reference element.

Further in accordance with a preferred embodiment of the present invention the control terminal of a bottom stack element the bottom stack element being the last of the stack elements that receives the reference current, receives a second reference voltage and the input of the bottom stack element is at GND.

Still further in accordance with a preferred embodiment of the present invention the stack elements and the reference element include PMOS transistors, and the first terminal includes an output including at least one of a source and bulk, the control terminal includes a gate, and the second terminal includes an input including a drain, wherein the control terminal and the input of the reference element are at GND, wherein a reference voltage is placed at the output of the reference element, wherein an output of the circuit is the output of the top stack element, the top stack element being the first of the stack elements that receives the reference current, and wherein the control terminal of a bottom stack element, the bottom stack element being the last of the stack elements that receives the reference current, receives a second reference voltage and the input of the bottom stack element is at GND.

In accordance with a preferred embodiment of the present invention the reference element is connected to the stack elements via a current mirror.

Further in accordance with a preferred embodiment of the present invention the current mirror includes at least two matched transistors.

Still further in accordance with a preferred embodiment of the present invention a voltage across the stack elements includes the V ct multiplied by a number of the stack elements.

In accordance with a preferred embodiment of the present invention a first reference voltage (V REF ) is input to the reference element.

Further in accordance with a preferred embodiment of the present invention a second reference voltage is input to the stack elements.

Still further in accordance with a preferred embodiment of the present invention the second reference voltage includes the first reference voltage divided by a voltage divider.

Additionally in accordance with a preferred embodiment of the present invention the second reference voltage is equal to the first reference voltage divided by a predetermined factor Y, and wherein an output OP of the circuit is given by OP=(S×V REF )+(V REF /Y) wherein S=the number of stack elements.

In accordance with a preferred embodiment of the present invention the voltage divider includes a resistor divider. The resistor divider may be buffered by a buffer. The output of the buffer may be input to the stack elements. The resistor divider may include a variable resistor divider or a digitally controlled resistor divider, for example.

Further in accordance with a preferred embodiment of the present invention there is a shunting path to at least one of the stack elements.

There is also provided in accordance with a preferred embodiment of the present invention a driver including fist and second PMOS transistors, first and second NMOS transistors, and first and second current sources, wherein a gate and a drain of the first PMOS transistor are connected to the first current source, and the first current source is grounded, and wherein a source of the first PMOS transistor is connected to a source of the first NMOS transistor, the first NMOS transistor having its gate and its drain connected to the second current source, the second current source being connected to a supply voltage, and wherein gates of the NMOS transistors are connected to each other, and gates of the FMOS transistors are connected to each other, and wherein a drain of the second NMOS transistor is connected to the supply voltage and a source of the second NMOS transistor is connected to an output of the driver, and wherein a drain of the second PMOS transistor is connected to GND, and a source of the second PMOS transistor is connected to the output of the driver.

In accordance with a preferred embodiment of the present invention the first and second current sources are derivable from a reference current.

Further in accordance with a preferred embodiment of the present invention the first and second current sources are generally equal.

Still further in accordance with a preferred embodiment of the present invention an input to the driver is connected to an output of a circuit including a reference element adapted to provide a reference current and having a control terminal and a first terminal, there being a voltage (V ct ) between the control terminal and the first terminal of the reference element, and a plurality of series-connected stack elements, each the stack element including a fist terminal connected to a first voltage, and a control terminal connected to a second terminal, the stack elements being adapted to receive at least one of the reference current and a multiple of the reference current, the stack elements and the reference element being matched such that a voltage between the control terminal and the first terminal of at least one of the stack elements is generally the same as V ct , wherein a first reference voltage (V REF ) is input to the reference element, and wherein a second reference voltage is input to the stack elements.

There is also provided in accordance with a preferred embodiment of the present invention a circuit including a reference element adapted to receive a first reference voltage and provide a reference current, and a plurality of series-connected stack elements adapted to receive the reference current and provide a multiple of the fist reference voltage, wherein the multiple is a function of the number of the stack elements.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will be understood and appreciated more fully from the following detailed description taken in conjunction with the appended draw in which:

FIG. 1 is a schematic illustration of a prior art voltage regulator;

FIG. 2 is a schematic illustration of a general circuit comprising stack elements, which may be used as a voltage regulator circuit, constructed and operative in accordance with a preferred embodiment of the present invention;

FIG. 3 is a schematic illustration of a voltage regulator constructed and operative in accordance with a preferred embodiment of the present invention, and using NMOS transistors;

FIG. 4 is a schematic illustration of the voltage regulator of FIG. 3 , illustrating diode-connected transistor circuitry, circuitry of a driver, and a circuit to generate a V OFFSET input used in the regulator of FIG. 3 ;

FIG. 5 is a schematic illustration of another version of the voltage regulator of FIG. 3 , constructed and operative in accordance with another preferred embodiment of the present invention, and including digital control of the V OFFSET input and the number of stack elements in the circuit;

FIG. 6 is a graphical illustration of a rise and fall of an output voltage of the voltage regulator of FIG. 5 , in accordance with a preferred embodiment of the present invention;

FIG. 7 is a schematic illustration of yet another version of the voltage regulator of FIG. 3 , constructed and operative in accordance with yet another preferred embodiment of the present invention, and including PMOS transistors;

FIGS. 8 and 9 are schematic illustrations of stack elements of the general circuit of FIG. 2 , which comprises NMOS transistors, in accordance with a preferred embodiment of the present invention, respectively without and with a resistor, and

FIGS. 10 and 11 are schematic illustrations of stack elements of the general circuit of FIG. 2 , which comprises PMOS transistors, in accordance with a preferred embodiment of the present invention, respectively without and with a resistor.

DETAILED DESCRIPTION OF THE PRESENT INVENTION

Reference is now made to FIG. 2 , which illustrates a circuit 100 comprising stack elements 102 , which may be used as a voltage regulator circuit, con d and operative in accordance with a preferred embodiment of the present invention.

The circuit 100 may include a reference element 104 adapted to provide a reference current (I ref ) and having a control terminal 97 , a first terminal 99 and a second terminal 98 , there being a voltage (V ct ) between the control terminal 97 and the first terminal 99 of reference element 104 . Reference element 104 may comprise an NMOS transistor, in which case control terminal 97 comprises a gate of the transistor, second terminal 98 comprises a drain of the transistor, first terminal 99 comprises a source of the transistor and V ct is the gate-source voltage (V gs ).

A plurality of series-connected stack elements 102 is preferably provided, wherein each stack element 102 comprises a first terminal 106 , and a control terminal 108 connected to a second terminal 110 . The stack elements 102 may receive the reference current I ref or a multiple thereof. The stack elements 102 and the reference element 104 are preferably matched. Two elements are considered “tcatched” if their lengths are substantially equal, and if their widths and current are either substantially equal or are the same multiple hereof The stack elements 102 and the reference element 104 are preferably matched such that the voltage between the control terminal 108 and the first terminal 106 of one or all of the stack elements 102 is generally the same as the V ct of the reference element 104 . (It is noted again that if reference element 104 is a transistor, then V ct =V gs ) The output of a first stack element 102 is connected to the input of a subsequent stack element 102 . The reference element 104 may be at a voltage V dd and the stack elements may be at voltage V pp wherein V pp ≧V dd .

The circuit 100 may be implemented in several ways in accordance with the present invention. More detailed examples of a circuit wherein the stack elements 102 and the reference element 104 comprise NMOS transistors are described hereinbelow with reference to FIGS. 3-6 . A more detailed example of a circuit wherein the stack elements 102 and the reference element 104 comprise PMOS transistors is described hereinbelow with reference to FIG. 7 . Two simplified and general examples of Circuits comprising NMOS transistors without and with a resistor are described hereinbelow with reference to FIGS. 8 and 9 . Two simplified and general examples of circuits comprising PMOS transistors without and with a resistor are described hereinbelow with reference to FIGS. 10 and 11 .

Reference is now made to FIG. 3 , which illustrates an implementation of the circuit 100 of FIG. 2 in a voltage regulator 10 constructed and operative in accordance with a preferred embodiment of the present invention.

A reference voltage V REF may be input via a circuit node n 1 into a gate g 1 of an NMOS reference element M 1 . A source S 1 and bulk of M 1 are connected to GND. A drain d 1 of M 1 is connected at a circuit node n 5 to a drain d 5 and a gate g 5 of a PMOS transistor M 5 , whose source S 5 and bulk are at V PP . The gate g 5 of M 5 is connected to a gate g 6 of a PMOS transistor M 6 , whose source S 6 and bulk are at V PP . A drain d 6 of M 6 is connected at a circuit node 114 to a gate g 2 and a drain d 2 of an NMOS transistor M 2 . A source S 2 and bulk of M 2 are connected through a circuit node n 3 to a gate g 3 and a drain d 3 of an NMOS transistor M 3 . A source S 3 and bulk of M 3 are connected at a circuit node n 2 to a gate g 4 and a drain d 4 of an NMOS transistor M 4 . A source S 4 and bulk of M 4 may be connected at a circuit node n 6 to a second input (a second reference voltage) V OFFSET . Circuit node n 4 is also connected to an input of a driver B 1 , whose output is an output of a regulator OP. Transistors M 5 and M 6 form a current mirror 12 . A current mirror is defined as a circuit element or portion of a circuit that receives an input current and outputs the same input current or a multiple thereof.

In accordance wit a preferred embodiment of the present invention, the circuit of FIG. 3 is manufactured in a process that allows independent control of the NMOS bulk voltages. Examples of such processes are triple well processes, and silicon-on-insulator.

One operation of the circuit in accordance with an embodiment of the invention is as follows. The input reference voltage V REF , which may typically be at a value of 1.3V, several 100 mV above the NMOS threshold voltage, is input to the gate g 1 of M 1 . M 1 then acts as a current source at its drain d 1 providing a reference current I ref , which may typically be 5-10 kA. This current may be subject to process variations, but these generally do not affect the output voltage.

The current I ref is fed into the current mirror 12 formed by transistors M 5 and M 6 . If transistors M 5 and M 6 are matched, the current at the drain d 6 of M 6 is I ref , or in general, at least a multiple thereof. The NMOS transistors M 1 , M 2 , M 3 and M 4 are all preferably matched. Since transistors M 2 , M 3 and M 4 are all diode connected (i.e., gate connected to drain) and have generally the same current as M 1 , their gate-source voltage (V gs ) is generally the same as the gate-source voltage of M 1 .

The transistors M 2 , M 3 and M 4 form a “stack” 14 , that is, a plurality of series-connected stack elements, wherein each of transistors M 2 , M 3 and M 4 is a stack element. The voltage across stack 14 is the gate-source voltage V gs multiplied by the number of transistors in the stack 14 . In the illustrated embodiment, for example, since there are three transistors in the stack 14 , the voltage between nodes n 4 and n 6 is three times V REF . If a second reference voltage source, also referred to as an offset voltage V OFFSET , is added at node n 6 , the voltage at n 4 and OP is 3×V REF +V OFFSET . V OFFSET may be equal to V REF divided by a predetermined factor Y, as described hereinbelow. The value of OP may be increased/decreased by increasing/decreasing the number of transistors in the stack 14 . In more general terms:

OP =( S×V REF )+( V REF /Y )  (1)

where S=the number of transistors in the stack 14 and Y is the divider ratio between V REF and V OFFSET .

In principle, any output voltage may be achieved by varying the number of transistors in the stack 14 and the divider ratio between V REF and V OFFSET . The driver B 1 may be a class AB driver, which can drive the output strongly while using minimal quiescent current.

In accordance with embodiments described herein, transistor M 2 is the “top” stack element, i.e., the first stack element to receive the reference current, and transistor M 4 is the “bottom” stack element, i.e., the last stack element to receive the reference current.

A more detailed version of the first embodiment is shown in FIG. 4 . This schematic includes the circuit of FIG. 3 , detailed circuitry of driver B 1 , as well as a circuit to generate the V OFFSET input.

In the embodiment of FIG. 4 , the driver B 1 is formed by PMOS transistors M 7 and M 8 , NMOS transistors M 9 and M 10 , and current sources C 1 and C 2 . A gate g 7 and a drain d 7 of M 7 are connected via a circuit node n 7 to current source C 1 . Current source C 1 is grounded to GND. A source S 7 of M 7 is connected at a circuit node n j to a source S 9 of transistor M 9 . The gate g 9 of M 9 and its drain d 9 are connected to current source C 2 via a circuit node no. The current source C 2 is connected to V PP . The gate g 9 of M 9 is connected to a gate g 10 of transistor M 10 , whose drain d 10 is connected to V PP and whose source S 10 is connected to OP via a circuit node n k . A gate g 8 of M 8 is connected to the gate g 7 of transistor M 7 . A source s 8 of M 8 is connected to node n k , and a drain d 8 of M 8 is connected to GND.

The circuit to generate the V OFFSET input preferably comprises a resistor divider 16 . Resistor divider 16 may comprise, without limitation, a resistor R 1 connected to V REF via circuit node n 1 , and to a resistor B 2 at circuit node 19 , Resistor R 2 is grounded to GND. A buffer B 2 bas a positive input connected to node n 9 , and a negative input connected to node n 6 , which, as described hereinabove, is connected to source S 4 (not shown) and bulk of M 4 .

In the driver B 1 of FIG. 4 , transistors M 7 , M 8 , M 9 and M 10 and current sources C 1 and C 2 preferably have equal current and are matched. C 1 and C 2 may be derived from I ref , or from another current reference. The current flowing in the stack 14 formed by transistors M 2 , M 3 , and M 4 is generally unaffected by the presence of the current in current sources C 1 and C 2 , because the two current sources compensate for each other. Thus, the voltage at n 4 is still defined by equation 1.

Transistor M 9 is diode connected, such that:

V ( n 8 )= V ( n 4 )+ V t +V dsat   (2)

where V t is the threshold voltage of transistor M 9 and V dsat is the degree to which the transistor M 9 is turned on beyond the threshold, According to basic MOSFET physics, the drain current I d is described by;

I d =k′W/L ( V dsat ) 2   (3)

where k′ is a process parameter, W and L are the width and length of the MOSFET and

V dsat =V gs −V t   (4)

with V gs being the gate-source voltage.

Similarly, transistor M 7 is diode connected and

V ( n 7 )= V ( n 4 )− V t −V dsat   (5)

Transistors M 8 and M 10 are preferably back-to-back source followers and are matched with M 7 and M 9 , respectively. The symmetry between the four transistors M 7 , Mg, M 9 and M 10 causes:

a) OP to be generally at the same voltage as n 4 in steady state,

b) the current flowing in the M 7 , M 9 branch to be generally equal to that in the M 8 , M 10 branch in steady state, and

c) V dsat (M 8 ) to be generally equal to V dsat (M 7 ), and V dsat (M 9 ) to be generally equal to V dsat (M 10 ) in steady state.

If the voltage at OP differs from n 4 , then the V dsat of one of transistors M 9 and M 10 increases, whereas the V dsat of the other transistor (M 8 or M 10 ) decreases, in accordance with equation 4. This results in a large current (in accordance with equation 3), which restores the equality between n 4 and OP. Thus the drive capability at OP may be very high. However, the quiescent currents of the circuit of FIG. 4 may be very low (˜20-30 μA).

The V offset input supplied at the source of M 4 may be generated by resistor divider 16 from V ref , which may be buffered by B 2 . It is noted that B 2 may have V DD as the supply such that the current drains caused by the buffer and the resistor divider 16 are less costly than those in the prior art.

A further enhancement of the voltage regulator of FIG. 3 or FIG. 4 is now described with reference to FIG. 5 , which includes digital control circuitry 18 .

Digital control circuitry 18 to generate the V OFFSET input preferably comprises a resistor divider 20 that may comprise, without limitation, a resistor R 1 connected to V REF via circuit node n 1 , and to a resistor R 2 at a circuit node n 12 . Resistor R 2 is connected to a resistor R 3 at a circuit node n 11 , and resistor R 3 is connected to a resistor R 4 via a circuit node n 10 . Resistor R 4 is grounded to GND. An NMOS transistor M 14 has its source S 14 connected to node n 12 , its gate g 14 connected to a digital input D 1 , and its drain d 14 connected to node n 9 via a circuit node n m . An NMOS transistor M 13 has its source S 13 connected to node n 11 , its gate g 13 connected to a digital input D 2 , and its drain d 13 connected to node n 9 via node n m . An NMOS transistor M 12 has its source S 12 connected to node n 10 , its gate g 12 connected to a digital input D 3 , and its drain d 12 connected to node n 9 . As described hereinabove with reference to FIG. 4 , buffer B 2 has a positive input connected to node n 9 , and a negative input connected to node n 6 , which is connected to source S 4 and bulk of M 4 . An NMOS transistor M 11 has its source S 11 connected to the gate g 4 of transistor M 4 , its gate g 11 connected to a digital input D 4 , and its drain d 11 connected to node n 6 via a circuit node n i .

In the embodiment of FIG. 5 , digital inputs D 1 , D 2 , and D 3 turn on/off transistors M 12 , M 13 , and M 14 , thus determining which voltage along the resistor divider 20 is input to buffer B 2 . Id this manner, the V OFFSET may be digitally controlled to be an arbitrary value between VRBF and GND, determined by the amount of digital inputs and transistors used. When the digital input D 4 is enabled, transistor M 11 shunts the V gs of transistor M 4 . Thus, the number of transistors in the diode stack 14 may also be determined digitally, The embodiment of FIG. 5 allows digital control of the S and Y values in equation 1 for a given regulator. In an EPROM device, this may be a very useful feature to allow different trim levels for the wordline voltage.

Reference is now made to FIG. 6 , which illustrates a SPICE simulation of the rise and fall of OP for the circuit in FIG. 5 . In the example of FIG. 6 , OP is driven from V DD (2.6V) to 4.9V and back to V DD . The values of V REF and V OFFSET are 1.3V and 1V respectively. The output capacitance is 50 pF. The regulator raises V(OP) to its final value in <1 μs. This requires currents in the mA range. The quiescent current is 30 μA, typical of class AB operation. It is emphasized-that these are only exemplary values, and the present invention is not limited to these values.

The circuits shown in FIGS. 3-5 all use NMOS transistors in the V gs stack and to generate I ref . However, in order to have good V gs matching between these transistors, it may be preferable to have independent control of the bulk voltage. In most CMOS process, all of the NMOS bulks may be permanently grounded, such that the V gs voltages in the stack may differ as a result of the bulk effect. For these processes, it is possible to implement the regulator with another embodiment of the present invention, which uses PMOS transistors for the reference current and the V gs stack, as is now described with reference to FIG. 7 .

A gate g 1 , and a drain d 1 of a PMOS reference element M 1 ′ are connected to GND. A source S 1′ of M 1 ′ is connected at a circuit node n 13 to the positive input of a comparator B 1 ′ and to its bulk. A drain d 15 of a PMOS transistor M 15 is connected to node n 13 . A gate g 15 of M 15 is connected to output of comparator B 1 ′ at a node n 14 , and to a gate g 16 of a PMOS transistor M 16 . A source S 15 of M 15 is connected to V DD . A source S 16 of M 16 is connected to V DD . A gate g 17 and a drain d 17 of an NMOS transistor M 17 are connected to a drain d 16 of Resistor M 16 at a node n 15 . A source S 17 of M 17 is grounded to GND. The gate g 17 of M 17 is connected to a gate g 18 of an NMOS transistor M 18 , whose source S 18 is grounded to GND. A drain d 18 of M 18 is connected at node n 5 to the drain d 5 of PMOS transistor M 5 . Some of the transistors form current mirrors. For example, transistors M 5 and M 6 form a current mirror, transistors M 15 and M 6 form a current mirror, wherein transistor M 15 is also used to generate the voltage at node n 13 ; transistors M 17 and M 18 form a current mirror; and the combination of transistors M 5 , M 6 , M 15 , M 16 , M 17 and M 18 forms a current mirror that receives an input current from the reference element and outputs the same input current or a multiple thereof to the stack elements.

The drain d 6 of M 6 is connected at node n 4 to a source and bulk S 2′ of a PMOS transistor M 2 ′. A gate g 2′ and a drain d 2′ of transistor M 2 ′ are connected through node n 3 to a source and bulk S 3 , of a PMOS transistor M 3 ′. A gate g 3′ and a drain d 3′ of transistor M 3 ′ are connected through node n 2 to a source and bulk S 4′ of a PMOS transistor M 4 ′. A gate g 4′ of transistor M 4 ′ is connected through node n 6 to node n 9 , to which are connected resistors R 1 and R 2 of resistor divider 16 . As described hereinabove with reference to FIG. 4 , resistor divider 16 may comprise without limitation resistor R 1 connected to V REF via node n 1 , and to resistor R 2 at node n 9 . Resistor R 2 is grounded to GND. Comparator B 1 ′ has a positive input connected to node n 13 , and a negative input connected to node n 1 . Comparator B 1 ′ receives V DD . Driver B 1 is connected to node n 4 as described hereinabove with reference to FIG. 4 .

The reference current, I ref is generated across PMOS transistor M 1 ′ in the embodiment of FIG. 7 . Transistor M 1 ′ is connected as a diode (gate to drain), and its source is driven by M 15 at node n 13 . The source voltage of M 1 ′ is fed back to the positive input of comparator B 1 ′, which has its negative input at V REF . The operational amplifier formed by B 1 ′ and M 15 equalizes the positive and negative inputs, such that V(n 13 )=V REF . The current in M 1 ′ (I ref ) is mirrored through transistors M 16 , M 17 , MI 8 , M 5 and M 6 to the V gs diode stack 14 ′ formed by M 2 ′, M 3 ′ and M 4 ′. The voltage between the gate of M 4 ′ and the source of M 2 ′ is 3×V REF , since M 1 ′, M 2 ′, M 3 ′ and M 4 ′ are matched in current and dimension. In addition, the offset voltage may be driven to the gate of M 4 by the resistor divider 16 from V REF , such that the voltage at n 4 is defined by equation 1. The output buffer (i.e., driver) that is formed by current sources C 1 and C 2 and by transistors M 7 -M 10 is generally identical to that shown in FIGS. 4 and 5 . In principle, any output buffer (driver) may be used in the embodiment of FIG. 7 , if and when necessary. The digital enhancements shown in FIG. 5 may also be implemented in the embodiment of FIG. 7 . The circuit of FIG. 7 obeys equation (1).

As mentioned hereinabove, the circuit 100 may be implemented without and with a resistor in accordance with the present invention. For example, as shown in FIG. 8 , the stack elements 102 and the reference element 104 of circuit 100 may comprise NMOS transistors. In such an embodiment, the control terminal 108 comprises the gate of the NMOS transistor, the first terminal 106 comprises the input which is the source and bulk of the NMOS transistor, and the second terminal 110 comprises the output which is the drain of the NMOS transistor, as described hereinabove with reference to the embodiment shown in FIG. 3 .

Referring to FIG. 9 , a resistor 107 may be connected between the source of the NMOS transistor and the first terminal 106 . The bulk may be connected either to the source or the first terminal 106 . Resistor 107 is preferably connected this way in the stack elements 102 and the reference element 104 .

Reference is now made to FIG. 10 , which illustrates another embodiment of the circuit 100 , wherein the stack elements 102 and the reference element 104 comprise PNOS transistors. In such an embodiment, the fast terminal 106 comprises an output comprising at least one of the source and bulk of the PMOS transistor, the control terminal 108 comprises the gate of the PMOS transistor, and the second terminal 110 comprises the input comprising the drain of the PMOS transistor, as described hereinabove with reference to the embodiment of FIG. 7 .

Referring to FIG. 11 , a resistor 107 may be connected between the source of the PMOS transistor and the first terminal 106 . The bulk may be connected either to the source or the first terminal 106 . Resistor 107 is preferably connected this way in the stack elements 102 and the reference element 104 .

Connecting resistor 107 between the source of the transistor and the first terminal 106 , as in FIGS. 9 and 11 , may achieve a more uniform temperature coefficient of current for the reference and stack elements. In other words, the reference and stack currents may be more uniform over a wide range of temperature.

It will be appreciated by persons skilled in the art that the present invention is not limited by what has been particularly shown and described herein above. Rather the scope of the invention is defined by the claims that follow:

Claims

1. A circuit comprising:a reference element adapted to provide either a reference current or a multiple of said reference current and having a control terminal and a first terminal, there being a voltage (Vct) between said control terminal and said first terminal of said reference element; and a plurality of series-connected stack elements, each said stack element comprising a first terminal and a control terminal connected to a second terminal, wherein one of said first and second terminals comprises an input and the other of said first and second terminals comprises an output, and the output of a first stack element is connected to the input of a subsequent stack element, said stack elements being adapted to receive from said reference element either said reference current or a multiple of said reference current, said stack elements and said reference element being matched such that a voltage between said control terminal and said first terminal of at least one of said stack elements is generally the same as Vct, wherein a voltage across one or more of said stack elements being a function of a parameter independent of any parameters associated with said reference element, and wherein said stack elements and said reference element comprise NMOS transistors, wherein for each NMOS transistor, a resistor is connected between a source of said transistor and said first terminal, a bulk of said transistor is connected to at least one of the source and said first terminal, said control terminal comprises a gate, said first terminal comprises an input of said stack element and said second terminal comprises an output comprising a drain.

2. A circuit comprising:a reference element adapted to provide either a reference current or a multiple of said reference current and having a control terminal and a first terminal, there being a voltage (Vct) between said control terminal and said first terminal of said reference element; and a plurality of series-connected stack elements, each said stack element comprising a first terminal and a control terminal connected to a second terminal, wherein one of said first and second terminals comprises an input and the other of said first and second terminals comprises an output, and the output of a first stack element is connected to the input of a subsequent stack element, said stack elements being adapted to receive from said reference element either said reference current or a multiple of said reference current, said stack elements and said reference element being matched such that a voltage between said control terminal and said first terminal of at least one of said stack elements is generally the same as Vct, wherein a voltage across one or more of said stack elements being a function of a parameter independent of any parameters associated with said reference element, and wherein said stack elements and said reference element comprise NMOS (p-channel metal oxide semiconductor) transistors, and said first terminal comprises an output comprising at least one of a source and bulk, said control terminal comprises a gate, and said second terminal comprises an input comprising a drain.

3. A circuit comprising:a reference element adapted to provide either a reference current or a multiple of said reference current and having a control terminal and a first terminal, there being a voltage (Vct) between said control terminal and said first terminal of said reference element; and a plurality of series-connected stack elements, each said stack element comprising a first terminal and a control terminal connected to a second terminal, wherein one of said first and second terminals comprises an input and the other of said first and second terminals comprises an output, and the output of a first stack element is connected to the input of a subsequent stack element, said stack elements being adapted to receive from said reference element either said reference current or a multiple of said reference current, said stack elements and said reference element being matched such that a voltage between said control terminal and said first terminal of at least one of said stack elements is generally the same as Vct, wherein a voltage across one or more of said stack elements being a function of a parameter independent of any parameters associated with said reference element, and wherein said stack elements and said reference element comprise PMOS transistors, wherein for each PMOS transistor, a resistor is connected between a source of said transistor and said first terminal, a bulk of said transistor is connected to at least one of the source and said first terminal, said control terminal comprises a gate, said first terminal comprises an output of said stack element and said second terminal comprises an input comprising a drain.

4. The circuit according to claim 2 wherein said control terminal and the input of said reference element are at GND.

5. The circuit according to claim 4 wherein a reference voltage is placed at the output of said reference element.

6. The circuit according to claim 2 wherein the control terminal of a bottom stack element, said bottom stack element being the last of said stack elements that receives said reference current, receives a second reference voltage and the input of said bottom stack element is at GND.

7. A circuit comprising:a reference element adapted to provide either a reference current or a multiple of said reference current and having a control terminal and a first terminal, there being a voltage (Vct) between said control terminal and said first terminal of said reference element; and a plurality of series-connected stack elements, each said stack element comprising a first terminal and a control terminal connected to a second terminal, wherein one of said first and second terminals comprises an input and the other of said first and second terminals comprises an output, and the output of a first stack element is connected to the input of a subsequent stack element, said stack elements being adapted to receive from said reference element either said reference current or a multiple of said reference current, said stack elements and said reference element being matched such that a voltage between said control terminal and said first terminal of at least one of said stack elements is generally the same as Vct, wherein a voltage across one or more of said stack elements being a function of a parameter independent of any parameters associated with said reference element; wherein said stack elements and said reference element comprise PMOS transistors, and said first terminal comprises an output comprising at least one of a source and bulk, said control terminal comprises a gate, and said second terminal comprises an input comprising a drain; wherein said control terminal and the input of said reference element are at GND; wherein a reference voltage is placed at said output of said reference element; wherein an output of said circuit is the output of the top stack element, said top stack element being the first of said stack elements that receives said reference current; and wherein the control terminal of a bottom stack element, said bottom stack element being the last of said stack elements that receives said reference current, receives a second reference voltage and the input of said bottom stack element is at GNT).

8. The circuit according to claim 1, wherein a first reference voltage (VREF) is input to said reference element, and wherein a second reference voltage is input to said stack elements.

9. The circuit according to claim 8 wherein said second reference voltage comprises said first reference voltage divided by a voltage divider.

10. The circuit according to claim 9 wherein said voltage divider comprises a resistor divider.

11. The circuit according to claim 10 wherein said resistor divider is buffered by a buffer.

12. The circuit according to claim 11 wherein an output of said buffer is input to said stack elements.

13. The circuit according to claim 10 wherein said resistor divider comprises a variable resistor divider.

14. The circuit according to claim 10 wherein said resistor divider comprises a digitally controlled resistor divider.

15. The circuit according to claim 10 wherein said resistor divider is buffered by a buffer, and said resistor divider comprises a digitally controlled resistor divider, wherein an output of said resistor divider is input to said buffer.

16. The circuit according to claim 14 and comprising a shunting path to at least one of said stack elements.

17. A circuit comprising:a reference element adapted to receive a first reference voltage and provide either a reference current or multiple of said reference current; and a plurality of series-connected stack elements adapted to receive said reference current and provide a multiple of said first reference voltage, wherein said multiple is a function of the number of said stack elements, wherein a voltage across one or more of said stack elements being a function of a parameter independent of any parameters associated with said reference element, and wherein a second reference voltage is input to said stack elements, said second reference voltage comprising said first reference voltage divided by a voltage divider.

18. The circuit according to claim 17 wherein said second reference voltage is equal to said first reference voltage divided by a predetermined factor Y, and wherein an output OP of said circuit is given by:OP (S×VREF)+(VREF/Y) wherein S=the number of stack elements.