Patent Application
20050258546
1. Technical Field
The present subject matter relates generally to integrated circuits (“ICs”). More particularly, the present subject matter relates to an IC package comprising at least two stacked dies having shared access to an memory.
2. Background Information
In many electronic systems, it is desirable for multiple devices (e.g., processors) to have access to memory for code and data storage. Determining an optimal configuration and packaging for multiple processor semiconductor dies and memory accessible to the dies is often difficult, costly, and may consume value circuit board space.
In accordance with at least one embodiment of the invention, an integrated circuit (“IC”) package comprises a first semiconductor die and a second semiconductor die. The first and second semiconductor dies are coupled together (e.g., “stacked”) within the same IC package. The first semiconductor die includes an interface to a memory die and the first and second semiconductor dies share said memory formed on said memory die. The memory die can either be located outside or inside the IC package containing the first and second semiconductor dies.
In another embodiment, a system comprises a first IC package containing a memory die and a second IC package coupled to the first IC package. The second IC package contains a die stack comprising first and second dies coupled together. The first semiconductor die includes an interface to the memory die and both of the dies in the die stack share access to the memory die. In some embodiments, the system may comprise a communication system such as a cellular telephone or Personal Digital Assistant (“PDA”).
Certain terms are used throughout the following description and claims to refer to particular system components. As one skilled in the art will appreciate, various companies may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not function. In the following discussion and in the claims, the terms “including” and “comprising” are used in an open-ended fashion, and thus should be interpreted to mean “including, but not limited to.” Also, the term “couple” or “couples” is intended to mean either an indirect or direct connection. Thus, if a first device couples to a second device, that connection may be through a direct connection, or through an indirect connection via other devices and connections.
For a more detailed description of the preferred embodiments of the present invention, reference will now be made to the accompanying drawings, wherein:
The following discussion is directed to various embodiments of the invention. Although one or more of these embodiments may be preferred, the embodiments disclosed should not be interpreted, or otherwise used, as limiting the scope of the disclosure, including the claims, unless otherwise specified. In addition, one skilled in the art will understand that the following description has broad application, and the discussion of any embodiment is meant only to be exemplary, of that embodiment, and not intended to intimate that the scope of the disclosure, including the claims, is limited to that embodiment.
The IC package 20 comprises preferably one semiconductor die 22, although additional dies can be included as well. The die 22 preferably comprises a memory 22 that is accessible via a memory interface 13 on the application engine 12. Both dies 12 and 14 can share access to the memory 22 via the application engine's interface 13. The memory 22 may comprise any suitable type of memory. Examples of memory comprise memory capable of single data rate or double data rate cycles, non-volatile memory (NOR, NAND Flash memory) or volatile memory such as dynamic random access memory (“DRAM”) or static RAM (“SRAM”). The application engine's interface 13 is thus configured to be compatible with the type of memory implemented in IC package 20.
The dies 12 and 14 may be fabricated per the same manufacturing process or different processes. For example, die 12 may be fabricated according to a high performance complementary metal oxide semiconductor (“CMOS”) process such as Texas Instrument's 90 nm CMOS technology, while die 14 may be fabricated according to a lower performance process such as Texas Instrument's 130 nm CMOS technology. The high performance CMOS process permits the application engine 12 to function at relatively high speed, albeit at the potential expense of higher leakage current than would otherwise be the case. The lower performance process used for the modem 14 may achieve lower leakage current than for the application engine 12, but modem 14 may function at a lower performance level. In general, the application engine 12 is designed for higher performance which is desirable for its functionality, whereas the modem 14 need not operate at such high performance and thus can be designed for lower leakage current to save battery (not specifically shown) life.
As noted above, the dies 12 and 14 in the IC package 20 may be coupled together to form a die stack. Any commonly known or later developed manufacturing technique for fabricating the die stack is acceptable. Exemplary die stacking techniques are provided in the following U.S. Pat. Nos. 6,621,155; 6,674,161; and 6,682,955, all of which are incorporated herein by reference.
While the preferred embodiments of the present invention have been shown and described, modifications thereof can be made by one skilled in the art without departing from the spirit and teachings of the invention. For example, although the memory 22 is shown in
| Number | Date | Country | Kind |
|---|---|---|---|
| 04291273.3 | May 2004 | EP | regional |
