Stacked memory cell for use in high-density CMOS SRAM

Abstract

A stacked memory cell for use in a high-density static random access memory is provided that includes first and second pull-down transistors formed in a first layer, a pass transistor connected between a gate of the second pull-down transistor and a bit line and formed in the first layer and a first and second pull-up transistors formed in a second layer located above the first layer and connected with the first and second pull-down transistors respectively to form an inverter latch. With the construction of a stacked memory cell having a lone pass transistor, cell size is reduced compared to a conventional six-transistor cell, and driving performance of the pass transistor can be improved.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other features and advantages of the present invention will become more apparent to those of ordinary skill in the art by describing in detail preferred embodiments thereof with reference to the attached drawings in which:

FIG. 1 is an equivalent circuit diagram of a known six-transistor (6T) CMOS SRAM cell;

FIG. 2 is a layout diagram of a CMOS SRAM cell of FIG. 1;

FIG. 3 is an equivalent circuit diagram of a stacked-type 6T CMOS SRAM cell illustrating the case where a CMOS SRAM cell of FIG. 1 is formed in a stacked-type configuration;

FIG. 4 is schematic cross-sectional view of a stacked-type 6T CMOS SRAM cell of FIG. 3;

FIGS. 5 and 6 are schematic cross-sectional views of a stacked-type 6T CMOS SRAM cell of FIG. 3;

FIG. 7 is an equivalent circuit diagram of a stacked-type 5T CMOS SRAM cell according to an exemplary embodiment of the present invention;

FIG. 8 is schematic cross-sectional view of a stacked-type 5T CMOS SRAM cell of FIG. 7;

FIG. 9 is an equivalent circuit diagram of a stacked-type 5T CMOS SRAM cell according to another exemplary embodiment of the present invention;

FIG. 10 is schematic cross-sectional view of a stacked-type 5T CMOS SRAM cell of FIG. 9;

FIG. 11 is an equivalent circuit diagram of a memory cell array using a stacked-type 5T CMOS SRAM cell of FIG. 7;

FIG. 12 is an equivalent circuit diagram of a memory cell array using a stacked-type 5T CMOS SRAM cell of FIG. 9; and

FIGS. 13 and 14 illustrate arrangements of word lines and bit lines related to a cell array configuration of stacked-type 5T CMOS SRAM cells in accordance with the present invention.

Claims

1. A stacked memory cell for use in a high-density static random access memory, the stacked memory cell comprising: a first pull-down transistor and a second pull-down transistor both formed in a first layer;a first pull-up transistor and a second pull-up transistor both formed in a second layer located over the first layer, wherein the first and second pull-up transistors are respectively connected to the first and second pull-down transistors to form an inverter latch; anda pass transistor connected between a gate of the second pull-down transistor and a bit line, and formed in either a third layer located over the first layer or the second layer.

2. The stacked memory cell according to claim 1, wherein the bit line is a single bit line.

3. The stacked memory cell according to claim 1, wherein the first layer is a semiconductor substrate.

4. The stacked memory cell according to claim 3, wherein any one of the second and third layers is a channel silicon layer formed by selective epitaxial growth (SEG).

5. A stacked memory cell for use in a high-density static random access memory, the stacked memory cell comprising: a first pull-down transistor and a second pull-down transistor both formed in a first layer;a first pull-up transistor and a second pull-up transistor both formed in a second layer located over the first layer, wherein the first and second pull-up transistors are respectively connected to the first and second pull-down transistors to form an inverter latch; anda pass transistor connected between a gate of the first pull-down transistor and a bit line, and formed in the first layer.

6. The stacked memory cell according to claim 5, wherein the bit line is a single bit line.

7. The stacked memory cell according to claim 5, wherein the first layer is a semiconductor substrate.

8. The stacked memory cell according to claim 3, wherein the second layer is a silicon layer formed by selective epitaxial growth (SEG).

9. A stacked memory cell for use in a high-density static random access memory, the stacked memory cell comprising: a first pull-down transistor and a second pull-down transistor both formed in a first layer;a first pull-up transistor and a second pull-up transistor both formed in a second layer located over the first layer, wherein the first and second pull-up transistors are respectively connected to the first and second pull-down transistors to form an inverter latch; anda pass transistor formed in a third layer located over the second layer, and connected between a first data node of the inverter latch and a bit line.

10. The stacked memory cell according to claim 9, wherein the bit line is a single bit line such that there is only bit line one per the memory cell.

11. The stacked memory cell according to claim 8, wherein the first layer is a P-type well formed in a semiconductor substrate.

12. The stacked memory cell according to claim 11, wherein the second and third layers are channel silicon layers formed by selective epitaxial growth (SEG).

13. A five-transistor (5T) complementary metal oxide semiconductor (CMOS) static random access memory (SRAM) cell in which a state of 1 or 0 is written through a single bit line, the 5T CMOS SRAM cell comprising: a first inverter having a first pull-up transistor and a first pull-down transistor connected in series between supply voltage and ground to form a first data node between the first pull-up and pull-down transistors;a second inverter having a second pull-up transistor and a second pull-down transistor connected in series between the supply voltage and ground to form a second data node between the second pull-up and pull-down transistors; anda pass transistor connected between a gate of the first inverter and the single bit line, and receiving a word line signal through a gate,wherein the first pull-down transistor, the second pull-down transistor and the pass transistor are formed in a first conductive layer, and wherein the first pull-up transistor and second pull-up transistor are formed in a second conductive layer located over the first conductive layer.

14. The 5T CMOS SRAM cell according to claim 13, wherein the word line signal applied to the gate of the pass transistor has a boosting voltage level higher than the supply voltage.

15. The 5T CMOS SRAM cell according to claim 13, further comprising a power line that includes a metal layer disposed in each memory cell in the same direction as the bit line.

16. A stacked memory cell array for use in high-density static random access memory, the stacked memory cell array comprising: a first memory cell that includes a first pull-down transistor, a second pull-down transistor and a first pass transistor all three of which are formed in a first layer, and a first pull-up transistor and a second pull-up transistor both of which are formed in a second layer located over the first layer;a second memory cell that includes a third pull-down transistor, a fourth pull-down transistor and a second pass transistor all three of which are formed in the first layer, and a third pull-up transistor and a fourth pull-up transistor both of which are formed in the second layer;a bit line commonly connected to a drain of the first pass transistor and a drain of the second pass transistors; anda first word line and a second word line that are independently connected to gates of the first and second pass transistors.

17. A method for fabricating a stacked-type single port static random access memory (SRAM) cell, the method comprising: forming an SRAM cell having one or more pull-down transistors, one or more pull-up transistors and a single access transistor in a single or double stacked cell structure; andforming a single bit line without forming a bit line having complementary relationship.