Patent Application
20240006735
Embodiments of the present disclosure generally relate to the field of package assemblies, and in particular package assemblies that include mmWave transceivers.
Higher data bandwidth and increased data speed between computing components, in particular within data centers, will become increasingly important. As a result, architectures will need to adapt to increased speed and higher frequency signal transmission, while minimizing cost. These higher frequency signal transmissions may occur, for example, within high-speed interconnects in racks in a data center, between blades in a server, or between sockets.
Embodiments of the present disclosure may generally relate to systems, apparatus, and/or processes directed to packages that include transceivers that are at least partly positioned underneath a waveguide launcher array to decrease the maximum signal transmission distance between the transceiver and the waveguide launcher array. Embodiments described herein may increase the overall data transmission rate between a die, such as a central processor unit (CPU), a graphics processor unit (GPU), or a SOC, and waveguides coupled with the waveguide launcher array. Embodiments described herein may facilitate new architectures that allow for a higher bandwidth density at a lower cost compared to optical systems, with increased design flexibility that includes modularizing TRX and waveguide launcher array packages.
In embodiments, a transceiver may include digital circuitry and analog circuitry, and may be divided into multiple dies. For example, one die may contain digital circuitry to send or receive digital signals from/to a CPU, and another die may include analog/radiofrequency (RF) circuitry that is coupled with the waveguide launcher array, which in turn is coupled with a plurality of waveguides.
In embodiments, a separate package may be created that includes the transceiver, one or more routing layers above the transceiver that includes the waveguide launcher array, and waveguide connectors coupled with the waveguide launcher array. The package may then be placed on a substrate that includes a bridge in the substrate that electrically couples the transceiver with a CPU on the substrate. In embodiments, a metallic-shielded dielectric waveguide may be coupled with the waveguide connectors.
In other embodiments, a dielectric clad dielectric waveguide, which may be referred to as a dielectric waveguide, may be coupled with the waveguide connectors. The dielectric waveguide may include a small diameter dielectric surrounded by a larger dielectric of different material. In some embodiments, a metal shielded dielectric waveguide, which may be referred to as a metallic shielded dielectric waveguide or a metallic waveguide, may have a smaller overall diameter compared to a dielectric waveguide. In embodiments the metallic shielded dielectric waveguide may be coupled with a dielectric clad dielectric waveguide using a waveguide connector.
In embodiments, the dielectric clad dielectric waveguide may extend the reach of the interconnect system by several meters. In addition, embodiments may be directed to architectures to combine analog/RF and digital, deep-scaled nodes, or integrated circuits, for optimized performance with waveguide launcher arrays. In embodiments, using dielectric clad dielectric waveguides may have a large cross-section area that may increase the package area around a main CPU. In other embodiments, decoupling the substrate that includes the CPU from a substrate that includes the transceiver and the waveguide launcher arrays will address the area increase.
Legacy servers use low-frequency, for example below mm-wave frequencies, high-speed interconnects for communication within data centers. This communication may include rack to rack, blade to blade, and/or socket to socket communication. The electrical fabrics used in these legacy implementations are limited in their ability to trade off data rate versus distance. For example, the distance reduces significantly as the data rate goes up, unless substantial equalization and complex error correction algorithms is used. In general, in these legacy implementations cost and cable cross-sectional size increase with increasing data rates and increases interconnect reaches.
As a result, embodiments may achieve a higher bandwidth density, and optimized performance, for example reduced area and increased power, by implementing a digital-intensive functions on a deep scaled node, and analog-intensive operations to an RF-optimized node. In addition, decoupling the CPU substrate from the transceiver/waveguide launcher array substrate may achieve lower costs, and decoupling the digital circuitry from the analog circuitry within the transceiver for independent operation may achieve higher link performance, lower insertion loss, and better area utilization.
In legacy implementations, to overcome such limitations and increase transmission distance, error correction schemes on traditional electrical fabrics are used. However, this may lead to substantial latency increases, which may be on the order of several hundreds of nanoseconds. For example, at 224 Gb per second generation, reach distances for transmission over legacy twinaxial electrical cables have reduced to around 1 meter or less from five meters at the 56 Gbps generation.
Other legacy implementations include optical interconnect fabrics that use silicon photonics and various semiconductor technologies along with optical fibers. These legacy implementations enable extremely high data rates over very long distances. However, for medium distance communications, for example within a server farm, the overhead power requirements associated with the optical fabric may be too high. In addition, there is a low misalignment tolerance for optical connections, and also a reduced temperature range for operation, which together lead to increased total cost of ownership. This is particularly true as the number of waveguides scale into the hundreds or thousands. As a result, the legacy implementation techniques, traditional electrical and optical, may not be optimal for server architectures where transmission ranges are between two and five meters and include several hundreds of lanes operating simultaneously.
In the following detailed description, reference is made to the accompanying drawings which form a part hereof, wherein like numerals designate like parts throughout, and in which is shown by way of illustration embodiments in which the subject matter of the present disclosure may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense, and the scope of embodiments is defined by the appended claims and their equivalents.
For the purposes of the present disclosure, the phrase “A and/or B” means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).
The description may use perspective-based descriptions such as top/bottom, in/out, over/under, and the like. Such descriptions are merely used to facilitate the discussion and are not intended to restrict the application of embodiments described herein to any particular orientation.
The description may use the phrases “in an embodiment,” or “in embodiments,” which may each refer to one or more of the same or different embodiments. Furthermore, the terms “comprising,” “including,” “having,” and the like, as used with respect to embodiments of the present disclosure, are synonymous.
The term “coupled with,” along with its derivatives, may be used herein. “Coupled” may mean one or more of the following. “Coupled” may mean that two or more elements are in direct physical or electrical contact. However, “coupled” may also mean that two or more elements indirectly contact each other, but yet still cooperate or interact with each other, and may mean that one or more other elements are coupled or connected between the elements that are said to be coupled with each other. The term “directly coupled” may mean that two or more elements are in direct contact.
Various operations may be described as multiple discrete operations in turn, in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as to imply that these operations are necessarily order dependent.
As used herein, the term “module” may refer to, be part of, or include an ASIC, an electronic circuit, a processor (shared, dedicated, or group) and/or memory (shared, dedicated, or group) that execute one or more software or firmware programs, a combinational logic circuit, and/or other suitable components that provide the described functionality.
Various Figures herein may depict one or more layers of one or more package assemblies. The layers depicted herein are depicted as examples of relative positions of the layers of the different package assemblies. The layers are depicted for the purposes of explanation, and are not drawn to scale. Therefore, comparative sizes of layers should not be assumed from the Figures, and sizes, thicknesses, or dimensions may be assumed for some embodiments only where specifically indicated or discussed.
A length of an edge 105a of transceiver 105 may be referred to as a shoreline width, and may range from 5 mm to 20 mm. As shown, the shoreline length is 10 mm. In implementations, a size of the transceivers 104, 105 may range from 10×5 mm to 10×10 mm. In other implementations, the size may be larger.
In implementations, a first group of waveguides 110 may be coupled with the first transceiver 104, and a second group of waveguides 111 maybe coupled with the second transceiver 105. An individual waveguide 114, which is a dielectric clad dielectric waveguide, may include an inner dielectric layer 116 that is surrounded by an outer dielectric layer 118. In implementations, the inner dielectric layer 116 may have a thin core, for example 1 mm, and may be surrounded by the outer dielectric layer 118 that may have an outer dimension of 1500 to 3000 μm, which serves as a cladding around the inner dielectric layer 116. Note that the inner dielectric layer 116 is shown as a rectangle, however it may have any cross-section shape. In other embodiments a bundle of waveguide of any cross-section shape may be embedded under a common cladding material.
Note that the overall diameter of the dielectric clad dielectric waveguide may be less than 10 mm, however this may vary based upon frequencies of operation and the dielectric material properties. For example at 140 GHz the diameter of the waveguide 114 may range from 1.5 mm to 6 mm when employing a dielectric with a low-dielectric constant (Dk), for example a Dk on the order of 2. In another example at 140 GHz, the diameter of the waveguide 114 may range from 0.5 to 3 mm when employing high-dielectric constant materials, for example with a Dk˜10. In higher frequency of operations, for example 280 GHz, waveguide 114 may range from 0.4 mm to 3 mm. In implementations, a width of the transceiver 104 may be on the order of 10 mm. In implementations (not shown), transceivers 104, 105 may support up to eight lanes, for example 8 receive waveguides and 8 transmit waveguides, for a total of 16 waveguides, which may make up one waveguide bundle.
Partial legacy package 150 is a cross section side view of partial legacy package 100 at A-A′. Bridge 108 is recessed into the substrate 102, and electrically couples the CPU 106 with the transceiver 104. The transceiver 104 is then electrically coupled with the waveguide launcher array 120, which is also at or near the surface of the substrate 102, using traces 122. Multiple waveguides 114 may then couple with the waveguide launcher array 120, to send and receive signals along the multiple waveguides 114. The waveguide launcher array 120 may be electromagnetic launchers, which may be of a stacked-pitch type, patch, monopole, dipole, Vivaldi-like, tapered-slot launchers, multimode launchers, and dual polarization launchers, and the like. A connector mechanism (not shown) is used to interface the first group of waveguides 110 to the waveguide launcher array 120, and has been omitted for clarity. The connector mechanism may be made out of metallic, conductive plastic or semi-insulative plastic materials to facilitate a robust interface between the waveguide launcher array 120 and a waveguide bundle of waveguides 110.
Note that because the transceiver 104 is at a side of the first group of waveguides 110, a distance d1 between the transceiver 104 and a first waveguide 114a may be significantly shorter than a distance d2 between the transceiver 104 and a second waveguide 114b. In particular, if the diameter of the waveguide 114 is approximately 4 mm, then the distance of a signal traveling from the transceiver 104 to the second waveguide 114b may travel an additional 12 to 16 mm as compared to the signal traveling from the transceiver 104 to the first waveguide 114a. In implementations (not shown) where a total of eight waveguides 114 may be in a line, the difference in length of signal travel may be on the order of 30 to 32 mm. As a result, there may be a significant insertion loss experienced by the signal traveling between the transceiver 104 and waveguides 114b. Moreover, there may be a significant time delay in the signal traveling between the transceiver 104 and the second waveguide 114b, as compared to the time it takes the signal to travel between the transceiver 104 and the first waveguide 114a which may increase the complexity of the digital correction and equalization of the link
Diagram 170 shows a detailed diagram of transceiver 104, that includes an area for input/output (I/O) 130. It also includes an area 132 for digital signal processing (DSP), analog digital conversion (ADC), and equalizer (EQ) functions that is coupled with individual Tx/Rx channels 134, which may electrically couple with traces 122, to in turn electrically couple with the waveguide launcher array 120. In some embodiments the area 132 may include a multi-input multi-output equalizer.
In embodiments, TRX functionalities are split into a digital circuitry 204a die and an analog/RF circuitry 204b die in order to optimize the performance of the respective subsystems by using a dedicated process for each. In embodiments, the digital circuitry 204a may be developed on a scaled digital node, for example using 7 nm, 5 nm, 4 nm, 3 nm, or 2 nm process implementations. The analog/RF circuitry 204b die may be developed on an RF-optimized node, for example using RF-silicon on insulator (SOI), RF-CMOS, SiGe, BiCMOS, or other similar process technologies, to achieve increased RF performance and power advantages.
In embodiments, the digital circuitry 204a and the analog/RF circuitry 204b may each be embedded into an oxide material 246, such as SiO2 or some other similar oxide material within a TRX layer 242. In embodiments, other silicon or dummy dies (not shown) may also be embedded into the oxide material 246 to provide quasi-monolithic stitching. In embodiments, the TRX layer 242 may be a ceramic or a glass interposer that includes cavities into which the dies that include the digital circuitry 204a and the analog/RF circuitry 204b may be embedded.
The front side layers 244 may be created using back-end-of-line (BEOL) processes that may have thick inter-layer dielectrics (not shown but discussed further below), for example 1 to 5 μm, and thick copper metallization (not shown but discussed further below), for example 1 to 5 μm that may be deposited. In embodiments, the front side layers 244 may include organic redistribution layers (RDL) (not shown but discussed further below) at a thickness which may reach several tens of micrometers. As a result, a waveguide launcher array 220, which may be similar to waveguide launcher array 120 of
The package 240 may be placed on a substrate 202, which may be similar to substrate 102 of
In embodiments, the digital circuitry 204a may communicate with the analog/RF circuitry 204b through routings (not shown) in the front side layers 244, or through routings (not shown) proximate to a surface of the substrate 202. In embodiments, the analog/RF circuitry 204b may be implemented as a die that may face upwards in order to have the shortest interconnect distance to the waveguide launcher array 220 in order to minimize routing loss. In embodiments, the digital circuitry 204a may be implemented as a die that may face either up or down. Power may be routed to the digital circuitry 204a or to the analog/RF circuitry 204b, either through the substrate 202 or through the front side layers 244.
Note that in embodiments, if both the digital circuitry 204a and the analog/RF circuitry 204b are placed in a same orientation, for example both facing upwards, then either the front side layers or the backside layers of the dies may be specially designed to ensure low loss, wideband connections and routing. For example thru-silicon vias (TSVs) may be optimized for transmission of power or RF signals.
Note also that the position of the analog/RF circuitry 204b may be configured to be underneath the group of waveguides 210 that include individual waveguides 214, which may be similar to the first group of waveguides 110 and waveguides 114 of
In embodiments, the TRX 304 may contain both digital circuitry and analog/RF circuitry. The TRX 304 may be electrically coupled with the CPU 306, which may be similar to CPU 206 of
As shown, the SOC 406 may be surrounded on all sides by a TRX packages 440, which may be similar to TRX package 340 of
The TRX layer 542 may include a digital circuitry die 504a and an analog/RF die 504b, which may be similar to digital circuitry 204a and analog/RF circuitry 204b of
The digital circuitry die 504a may include the main substrate of the die 504a1, a front-end-of-line (FEOL) portion 504a2, and a BEOL portion 504a3. In embodiments, the BEOL 504a3 may electrically couple with a bridge 508 that is within the substrate 502, which may be similar to bridge 208 and substrate 202 of
Similarly, the analog/RF circuitry die 504b may include the main substrate of the die 504b1, a FEOL portion 504b2, and a BEOL portion 504b3. In embodiments, the BEOL 504b3 may be at the top of the analog/RF circuitry die 504b and electrically couple with the waveguide launcher array 520, to provide a shorter electrical path to the waveguide launcher array 520. In embodiments, the analog/RF circuitry die 504b may electrically couple with the digital circuitry die 504a using electrical routings 522, which may be similar to electrical routings 122 of
In embodiments, power and/or signals may be routed using through silicon vias (TSV) 552 to electrically couple the substrate 502 with the analog/RF circuitry die 504b. In embodiments, power and/or signals may be routed through TSV 553 to electrically couple the front side layers 544 with the digital circuitry die 504a. In other embodiments, through dielectric vias (TDV) 543 may route power or signals between the substrate 502 and the front side layers 544.
In embodiments, the waveguide launcher array 520 may couple into a metallic based connector, and the group of waveguides 510, which may be similar to the group of waveguides 210 of
For example, at 110 GHz to 170 GHz, the area occupied by the group of waveguides 510 on a surface of the waveguide launcher array 520 may be approximately 1.7×0.85 mm, which is significantly less than the area of the group of waveguides 210 of
In embodiments, the group of waveguides 510 may include one or more metallic waveguide connectors (not shown) which may be used to change the physical direction of the various waveguides 514. In embodiments, a coupler (not shown) may attach to the end of one or more waveguides 514 to be used to convert from a metallic shielded dielectric waveguide 514 to a dielectric clad dielectric waveguide (not shown), which may be similar to waveguide 214 of
In this embodiment, an interposer layer 647a may be between the TRX layer 642 and the substrate 602, which may include routings 649a1 and vias 649a2 to facilitate electrical routing between the components in the TRX layer 642, the substrate 602, and the bridge 608, which may be similar to bridge 508 of
In embodiments, the interposer layer 647a may include through silicon vias (TSV) (not shown) to pass power and/or I/O signals between the substrates 602 and any dies or die complexes within the package 641a. In embodiments, routing 649a1 may also connect between various dies within the package 641a using a through dielectric via (TDV) 642a. In embodiments, the interposer layer 647a may have active structures (not shown), which may include memory, or other digital functions.
With respect to the embodiments discussed with respect to
At block 702, the process may include providing a substrate. In embodiments, the substrate may be similar to substrate 202 of
At block 704, the process may further include placing a transceiver on a side of the substrate. In embodiments, the transceiver may be similar to transceiver 104 of
At block 706, the process may further include placing a waveguide launcher array on the transceiver, where at least a portion of the transceiver is between the waveguide launcher array and the side of the substrate. In embodiments, the waveguide launcher array may be similar to waveguide launcher array 220 of
In an embodiment, the electronic system 800 is a computer system that includes a system bus 820 to electrically couple the various components of the electronic system 800. The system bus 820 is a single bus or any combination of busses according to various embodiments. The electronic system 800 includes a voltage source 830 that provides power to the integrated circuit 810. In some embodiments, the voltage source 830 supplies current to the integrated circuit 810 through the system bus 820.
The integrated circuit 810 is electrically coupled to the system bus 820 and includes any circuit, or combination of circuits according to an embodiment. In an embodiment, the integrated circuit 810 includes a processor 812 that can be of any type. As used herein, the processor 812 may mean any type of circuit such as, but not limited to, a microprocessor, a microcontroller, a graphics processor, a digital signal processor, or another processor. In an embodiment, the processor 812 includes, or is coupled with, a stacked transceiver and waveguide launcher array, as disclosed herein. In an embodiment, SRAM embodiments are found in memory caches of the processor. Other types of circuits that can be included in the integrated circuit 810 are a custom circuit or an application-specific integrated circuit (ASIC), such as a communications circuit 814 for use in wireless devices such as cellular telephones, smart phones, pagers, portable computers, two-way radios, and similar electronic systems, or a communications circuit for servers. In an embodiment, the integrated circuit 810 includes on-die memory 816 such as static random-access memory (SRAM). In an embodiment, the integrated circuit 810 includes embedded on-die memory 816 such as embedded dynamic random-access memory (eDRAM).
In an embodiment, the integrated circuit 810 is complemented with a subsequent integrated circuit 811. Useful embodiments include a dual processor 813 and a dual communications circuit 815 and dual on-die memory 817 such as SRAM. In an embodiment, the dual integrated circuit 810 includes embedded on-die memory 817 such as eDRAM.
In an embodiment, the electronic system 800 also includes an external memory 840 that in turn may include one or more memory elements suitable to the particular application, such as a main memory 842 in the form of RAM, one or more hard drives 844, and/or one or more drives that handle removable media 846, such as diskettes, compact disks (CDs), digital variable disks (DVDs), flash memory drives, and other removable media known in the art. The external memory 840 may also be embedded memory 848 such as the first die in a die stack, according to an embodiment.
In an embodiment, the electronic system 800 also includes a display device 850, an audio output 860. In an embodiment, the electronic system 800 includes an input device such as a controller 870 that may be a keyboard, mouse, trackball, game controller, microphone, voice-recognition device, or any other input device that inputs information into the electronic system 800. In an embodiment, an input device 870 is a camera. In an embodiment, an input device 870 is a digital sound recorder. In an embodiment, an input device 870 is a camera and a digital sound recorder.
As shown herein, the integrated circuit 810 can be implemented in a number of different embodiments, including a package substrate having a stacked transceiver and waveguide launcher array, according to any of the several disclosed embodiments and their equivalents, an electronic system, a computer system, one or more methods of fabricating an integrated circuit, and one or more methods of fabricating an electronic assembly that includes a package substrate having a stacked transceiver and waveguide launcher array, according to any of the several disclosed embodiments as set forth herein in the various embodiments and their art-recognized equivalents. The elements, materials, geometries, dimensions, and sequence of operations can all be varied to suit particular I/O coupling requirements including array contact count, array contact configuration for a microelectronic die embedded in a processor mounting substrate according to any of the several disclosed package substrates having a stacked transceiver and waveguide launcher array embodiments and their equivalents. A foundation substrate may be included, as represented by the dashed line of
The following paragraphs describe examples of various embodiments.
Example 1 is a package comprising: a waveguide launcher array; transceiver circuitry electrically coupled with the waveguide launcher array; and wherein the waveguide launcher array and at least a portion of the transceiver circuitry are in a stack formation with respect to a plane of the waveguide launcher array.
Example 2 includes the package of example 1, or of any other example or embodiment herein, wherein the transceiver circuitry includes digital circuitry and analog circuitry.
Example 3 includes the package of example 2, or of any other example or embodiment herein, wherein the waveguide launcher array and at least a portion of the analog circuitry are in the stack formation.
Example 4 includes the package of example 2, or of any other example or embodiment herein, wherein the digital circuitry is in a first die and the analog circuitry is in a second die that is separate and distinct from the first die.
Example 5 includes the package of example 4, or of any other example or embodiment herein, wherein the second die is electrically coupled with the waveguide launcher array through backside metal layers of the second die.
Example 6 includes the package of example 4, or of any other example or embodiment herein, wherein a backside metal layer of the first die is facing in a first direction away from the waveguide launcher array, and wherein a backside metal layer of the second die is facing in a second direction toward the waveguide launcher array.
Example 7 includes the package of example 4, or of any other example or embodiment herein, wherein the first die is implemented in a scaled digital node, and wherein the second die is an RF-optimized node.
Example 8 includes the package of example 4, or of any other example or embodiment herein, wherein the first die and the second die are embedded in a selected one of: a ceramic interposer or a glass interposer.
Example 9 includes the package of example 1, or of any other example or embodiment herein, wherein the waveguide launcher array is in a layer that includes electrical routings; and wherein the layer is physically coupled with the transceiver circuitry.
Example 10 includes the package of example 9, or of any other example or embodiment herein, wherein the electrical routings in the layer provide power to the transceiver circuitry.
Example 11 includes the package of example 1, or of any other example or embodiment herein, further comprising a connector for a plurality of waveguides coupled with the waveguide launcher array.
Example 12 includes the package of example 11, or of any other example or embodiment herein, wherein a first subset of the plurality of waveguides are transmit waveguides, and a second plurality of the waveguides are receive waveguides.
Example 13 includes the package of example 11, or of any other example or embodiment herein, wherein the connector for the plurality of waveguides further includes a connector for a selected one or more of: a dielectric clad dielectric waveguide or a metallic shielded dielectric waveguide.
Example 14 includes the package of example 13, or of any other example or embodiment herein, further comprising: the metallic shielded dielectric waveguide that has a first end at the connector, and a second end opposite the first end; and a dielectric clad dielectric waveguide converter at the second and of the metallic shielded dielectric waveguide, wherein the dielectric clad dielectric waveguide converter couples the metallic shielded dielectric waveguide with a dielectric clad dielectric.
Example 15 includes the package of example 14, or of any other example or embodiment herein, wherein the package is coupled with a substrate, wherein the substrate further includes a die on the substrate, the die electrically coupled with the transceiver circuitry.
Example 16 includes the package of example 15, or of any other example or embodiment herein, wherein the die is electrically coupled with the transceiver circuitry using a selected one or more of: a bridge, an interconnect, conductive traces, or a routing layer proximate to a side of the substrate.
Example 17 is a system comprising: a substrate; a system on chip (SOC) on a side of the substrate; a transceiver die complex on the side of the substrate, wherein the transceiver die complex is electrically coupled to the SOC; and a waveguide launcher array on the transceiver die complex, wherein at least a portion of the transceiver die complex is between the waveguide launcher array and the side of the substrate in a direction perpendicular to the side of the substrate.
Example 18 includes the system of example 17, or of any other example or embodiment herein, wherein the transceiver die complex includes digital die and an analog die, and wherein at least a portion of the analog die is between the waveguide launcher and the side of the substrate.
Example 19 includes the system of example 17, or of any other example or embodiment herein, wherein the SOC is electrically coupled with the transceiver die complex using a selected one or more of: a bridge, an interposer, an interconnect, or a routing layer proximate to the side of the substrate.
Example 20 includes the system of example 17, or of any other example or embodiment herein, wherein the SOC includes a selected one or more of: a CPU, an XPU, or a graphics processor.
Example 21 includes the system of example 17, or of any other example or embodiment herein, wherein the transceiver die complex includes a plurality of transceiver die complexes, and wherein the waveguide launcher array includes a plurality of waveguide launcher arrays.
Example 22 includes the system of example 21, or of any other example or embodiment herein, wherein the plurality of transceiver die complexes are electrically coupled with the SOC along two or more edges of the SOC.
Example 23 is a method comprising: providing a substrate; placing a transceiver on a side of the substrate; and placing a waveguide launcher array on the transceiver, wherein at least a portion of the transceiver is between the waveguide launcher array and the side of the substrate.
Example 24 includes the method of example 23, or of any other example or embodiment herein, wherein the transceiver includes digital circuitry and analog circuitry, and wherein at least a portion of the analog circuitry is between the waveguide launcher array and the side of the substrate.
Example 25 includes the method of example 23, or of any other example or embodiment herein, further comprising: placing a die on the side of the substrate; and electrically coupling the die to the transceiver.
Various embodiments may include any suitable combination of the above-described embodiments including alternative (or) embodiments of embodiments that are described in conjunctive form (and) above (e.g., the “and” may be “and/or”). Furthermore, some embodiments may include one or more articles of manufacture (e.g., non-transitory computer-readable media) having instructions, stored thereon, that when executed result in actions of any of the above-described embodiments. Moreover, some embodiments may include apparatuses or systems having any suitable means for carrying out the various operations of the above-described embodiments.
The above description of illustrated embodiments, including what is described in the Abstract, is not intended to be exhaustive or to limit embodiments to the precise forms disclosed. While specific embodiments are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the embodiments, as those skilled in the relevant art will recognize.
These modifications may be made to the embodiments in light of the above detailed description. The terms used in the following claims should not be construed to limit the embodiments to the specific implementations disclosed in the specification and the claims. Rather, the scope of the invention is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.
