Patent Application
20250212508
The present application relates to semiconductors, and more specifically, to techniques for forming semiconductor structures. Semiconductors and integrated circuit chips have become ubiquitous within many products, particularly as they continue to decrease in cost and size. There is a continued desire to reduce the size of structural features and/or to provide a greater amount of structural features for a given chip size. Miniaturization, in general, allows for increased performance at lower power levels and lower cost. Present technology is at or approaching atomic level scaling of certain micro-devices such as logic gates, field-effect transistors (FETs), and capacitors.
A field-effect transistor (FET) is a three-terminal device having a source, a gate, and a drain, and having action that depends on the flow of carriers (electrons or holes) along a channel that runs between the source and drain. Current through the channel between the source and drain may be controlled by a transverse electric field under the gate.
FETs are widely used for switching, amplification, filtering, and other tasks. FETs include metal-oxide-semiconductor (MOS) FETs (MOSFETs). Complementary MOS (CMOS) devices are widely used, where both n-type and p-type transistors (nFET and pFET) are used to fabricate logic and other circuitry. Source and drain regions of a FET are typically formed by adding dopants to target regions of a semiconductor body on either side of a channel, with the gate being formed above the channel. The gate includes a gate dielectric over the channel and a gate conductor over the gate dielectric. The gate dielectric is an insulator material that prevents large leakage current from flowing into the channel when voltage is applied to the gate conductor while allowing applied gate voltage to produce a transverse electric field in the channel.
Various techniques may be used to reduce the area of FETs. One technique is through the use of fin-shaped channels in FinFET devices. Before the advent of FinFET arrangements, CMOS devices were typically substantially planar along the surface of the semiconductor substrate, with the exception of the FET gate disposed over the top of the channel. FinFETs utilize a vertical channel structure, increasing the surface area of the channel exposed to the gate. Thus, in FinFET structures the gate can more effectively control the channel, as the gate extends over more than one side or surface of the channel. In FinFET arrangements, the gate encloses three surfaces of the three-dimensional channel, rather than being disposed over just the top surface of a traditional planar channel.
Another technique useful for reducing the size of FETs is through the use of stacked nanosheet channels formed over a semiconductor substrate. Stacked nanosheets may be two-dimensional nanostructures, such as sheets having a thickness range on the order of 1 to 100 nanometers (nm). Nanosheets and nanowires are viable options for scaling to 7 nm node and beyond. A general process flow for formation of a nanosheet stack involves removing sacrificial layers, which may be formed of Silicon Germanium (SiGe), between sheets of channel material, which may be formed of Silicon (Si).
For continued scaling and area improvement, stacked transistor structures may be used. A stacked transistor structure may include multiple transistors stacked over one another vertically.
Embodiments of the invention provide techniques for forming stacked transistor structures where top and bottom transistor devices have aligned cell or device boundaries, and where channels for the top and bottom transistor devices are shifted relative to one another within the aligned cell or device boundaries.
In one embodiment, a semiconductor structure includes a first transistor and a second transistor vertically stacked over the first transistor. The first transistor and the second transistor have horizontally aligned cell boundaries. A first set of one or more channels of the first transistor are horizontally offset from a second set of one or more channels of the second transistor within the horizontally aligned cell boundaries.
In another embodiment, a semiconductor structure includes a first stacked transistor cell including a first transistor and a second transistor vertically stacked over the first transistor, where a first set of one or more channels of the first transistor are horizontally offset from a second set of one or more channels of the second transistor within cell boundaries of the first stacked transistor cell. The semiconductor structure also includes a second stacked transistor cell including a third transistor and a fourth transistor vertically stacked over the third transistor, where a third set of one or more channels of the third transistor are horizontally offset from a fourth set of one or more channels of the fourth transistor within cell boundaries of the second stacked transistor cell. The second stacked transistor cell is laterally adjacent the first stacked transistor cell.
In another embodiment, a semiconductor structure includes a first transistor, a second transistor vertically stacked over the first transistor, a first dielectric spacer at a first lateral edge of the first and second transistors, and a second dielectric spacer at a second lateral edge of the first and second transistors. A first set of one or more channels of the first transistor are laterally closer to the first dielectric spacer than the second dielectric spacer. A second set of one or more channels of the second transistor are laterally closer to the second dielectric spacer than the first dielectric spacer.
In another embodiment, a stacked transistor structure includes a first stacked transistor cell including a first transistor and a second transistor stacked vertically over the first transistor, a second stacked transistor cell including a third transistor and a fourth transistor stacked vertically over the third transistor, and a dielectric wall separating the first stacked transistor cell and the second stacked transistor cell. A first set of one or more channels of the first transistor have a first lateral distance to the dielectric wall and a second set of one or more channels of the second transistor have a second lateral distance to the dielectric wall, the first lateral distance being different than the second lateral distance. A third set of one or more channels of the third transistor have a third lateral distance to the dielectric wall and a fourth set of one or more channels of the fourth transistor have a fourth lateral distance to the dielectric wall, the third lateral distance being different than the fourth lateral distance.
In another embodiment, an integrated circuit includes a semiconductor structure including a first transistor and a second transistor vertically stacked over the first transistor. The first transistor and the second transistor have horizontally aligned cell boundaries. A first set of one or more channels of the first transistor are horizontally offset from a second set of one or more channels of the second transistor within the horizontally aligned cell boundaries.
Illustrative embodiments of the invention may be described herein in the context of illustrative methods for forming stacked transistor structures with aligned cell or device boundaries and shifted channels, along with illustrative apparatus, systems and devices formed using such methods. However, it is to be understood that embodiments of the invention are not limited to the illustrative methods, apparatus, systems and devices but instead are more broadly applicable to other suitable methods, apparatus, systems and devices.
It is to be understood that the various features shown in the accompanying drawings are schematic illustrations that are not necessarily drawn to scale. Moreover, the same or similar reference numbers are used throughout the drawings to denote the same or similar features, elements, or structures, and thus, a detailed explanation of the same or similar features, elements, or structures will not be repeated for each of the drawings. Further, the terms “exemplary” and “illustrative” as used herein mean “serving as an example, instance, or illustration.” Any embodiment or design described herein as “exemplary” or “illustrative” is not to be construed as preferred or advantageous over other embodiments or designs.
According to an aspect of the invention, there is provided a semiconductor structure including a first transistor and a second transistor vertically stacked over the first transistor. The first transistor and the second transistor have horizontally aligned cell boundaries. A first set of one or more channels of the first transistor are horizontally offset from a second set of one or more channels of the second transistor within the horizontally aligned cell boundaries. The shifted first and second sets of one or more channels of the semiconductor structure advantageously allows for integrating connections to the first and second transistors within the horizontally aligned cell boundaries.
In embodiments, the first set of one or more channels of the first transistor have a first distance to the horizontally aligned cell boundaries at a first lateral side of the semiconductor structure and a second distance to the horizontally aligned cell boundaries at a second lateral side of the semiconductor structure opposite the first lateral side of the semiconductor structure, the first distance being greater than the second distance. The second set of one or more channels of the second transistor have a third distance to the horizontally aligned cell boundaries at the first lateral side of the semiconductor structure and a fourth distance to the horizontally aligned cell boundaries at the second lateral side of the semiconductor structure opposite the first lateral side of the semiconductor structure, the third distance being less than the fourth distance. Such spacing of the first and second sets of one or more channels from the horizontally aligned cell boundaries advantageously allows for forming backside contacts to the second transistor within the horizontally aligned cell boundaries.
In embodiments, the semiconductor structure further includes a gate merge contact between a first gate region of the first transistor and a second gate region of the second transistor, where the gate merge contact is disposed within the horizontally aligned cell boundaries on a first side of the second set of channels and over a portion of the first set of channels. The gate merge contact advantageously allows for combined connections or contacts to the first and second gate regions which saves area.
In embodiments, the first transistor is proximate a backside of the semiconductor structure and the second transistor is proximate a frontside of the semiconductor structure, and the semiconductor structure further includes at least one contact extending from a backside power delivery network of the semiconductor structure to at least one semiconductor terminal of the second transistor, the at least one contact being underneath at least a portion of the at least one semiconductor terminal, the portion of the at least one semiconductor terminal being laterally adjacent to the second set of one or more channels. The at least one contact which extends from the backside of the semiconductor structure advantageously allows for reduced area footprint of the semiconductor structure. Further advantages are provided in that the at least one contact may be hidden or tucked under the second transistor within the horizontally aligned cell boundaries.
In embodiments, the first transistor is proximate a backside of the semiconductor structure and the second transistor is proximate a frontside of the semiconductor structure, and the semiconductor structure further includes a contact which connects to a semiconductor terminal of the first transistor at the backside of the semiconductor structure, the contact having a first portion with a first width proximate a bottom surface of the first semiconductor terminal of the first transistor and a second portion with a second width proximate a backside of the first portion, the first width being greater than the second width. The structure of the first contact having the different first and second widths for first and second portions thereof advantageously can reduce the risk of shorting with other electrical contacts.
In embodiments, the semiconductor structure further includes at least one contact to at least one of the first transistor and the second transistor which is within the horizontally aligned cell boundaries. The at least one contact being within the horizontally aligned cell boundaries advantageously provides area savings for the semiconductor structure.
In embodiments, the semiconductor structure further includes a first power rail which connects to a first semiconductor terminal of one of the first transistor and the second transistor and a second power rail which connects to a second semiconductor terminal of one of the first transistor and the second transistor, where the first power rail has a different width than the second power rail. The first and second power rails having different widths (also referred to having asymmetric first and second power rails) advantageously allows for optimizing the overlap of contacts to the first and second semiconductor terminals.
According to an aspect of the invention, there is provided a semiconductor structure including a first stacked transistor cell including a first transistor and a second transistor vertically stacked over the first transistor, where a first set of one or more channels of the first transistor are horizontally offset from a second set of one or more channels of the second transistor within cell boundaries of the first stacked transistor cell. The semiconductor structure also includes a second stacked transistor cell including a third transistor and a fourth transistor vertically stacked over the third transistor, where a third set of one or more channels of the third transistor are horizontally offset from a fourth set of one or more channels of the fourth transistor within cell boundaries of the second stacked transistor cell. The second stacked transistor cell is laterally adjacent the first stacked transistor cell. The shifted first and second sets of one or more channels of the first and second transistors of the first stacked transistor cell and the shifted third and fourth sets of one or more channels of the third and fourth transistors of the second stacked transistor cell advantageously allow for integrating connections to the first, second, third and fourth transistors both within the cell boundaries of the first and second stacked transistor cells as well as for one or more connections or contacts which span the laterally adjacent first and second stacked transistor cells.
In embodiments, the first set of one or more channels of the first transistor have a first lateral distance from the third set of one or more channels of the third transistor, the second set of one or more channels of the second transistor have a second lateral distance from the fourth set of one or more channels of the fourth transistor, and the first lateral distance is different than the second lateral distance. Such spacing of the first, second, third and fourth sets of one or more channels advantageously allows for forming backside contacts to the second and fourth transistors.
In embodiments, a first lateral distance between the first set of one or more channels of the first transistor and the third set of one or more channels of the third transistor than second set of one or more channels is less than a second lateral distance between the second set of one or more channels of the first transistor and the fourth set of one or more channels of the fourth transistor. The semiconductor structure further includes at least one of: a first semiconductor terminal of the first transistor which is merged with a second semiconductor terminal of the third transistor; and a merged contact to the first semiconductor terminal of the first transistor and the second semiconductor terminal of the third transistor. Such merged semiconductor terminals and/or merged contacts advantageously enable improved connections for the first and third transistors.
In embodiments, a first lateral distance between the first set of one or more channels of the first transistor and the third set of one or more channels of the third transistor than second set of one or more channels is greater than a second lateral distance between the second set of one or more channels of the first transistor and the fourth set of one or more channels of the fourth transistor. The semiconductor structure further includes at least one of: a first semiconductor terminal of the second transistor which is merged with a second semiconductor terminal of the fourth transistor; and a merged contact to the first semiconductor terminal of the second transistor and the second semiconductor terminal of the fourth transistor. Such merged semiconductor terminals and/or merged contacts advantageously enable improved connections for the second and fourth transistors.
In embodiments, the semiconductor structure further includes at least one power rail that is merged across the cell boundaries of the first stacked transistor cell and the second stacked transistor cell. The merged power rail is advantageously wider than separate power rails, providing benefits in terms of electrical resistance and capacitance.
According to an aspect of the invention, there is provided a semiconductor structure including a first transistor, a second transistor vertically stacked over the first transistor, a first dielectric spacer at a first lateral edge of the first and second transistors, and a second dielectric spacer at a second lateral edge of the first and second transistors. A first set of one or more channels of the first transistor are laterally closer to the first dielectric spacer than the second dielectric spacer. A second set of one or more channels of the second transistor are laterally closer to the second dielectric spacer than the first dielectric spacer. The semiconductor structure advantageously allows for integrating connections to the first and second transistors between the first and second dielectric spacers, which define cell boundaries for the first and second transistors.
In embodiments, the first dielectric spacer includes a first portion surrounding the first set of one or more channels of the first transistor and a second portion above the first portion, where the first portion of the first dielectric spacer has a first width, where the second portion of the first dielectric spacer has a second width, and where the second width is greater than the first width. In embodiments, the first portion of the first dielectric spacer has a high-k dielectric liner and the second portion of the first dielectric spacer does not have the high-k dielectric liner. In embodiments, the second dielectric spacer includes a first portion surrounding the second set of one or more channels of the second transistor and a second portion below the first portion, where the first portion of the second dielectric spacer has a third width, where the second portion of the second dielectric spacer has a fourth width, and where the third width is less than the fourth width. These structures of the first and second dielectric spacers enable forksheet-like sequential integration processing for stacked transistors with aligned cell boundaries and shifted channels.
According to an aspect of the invention, there is provided a stacked transistor structure including a first stacked transistor cell including a first transistor and a second transistor stacked vertically over the first transistor, a second stacked transistor cell including a third transistor and a fourth transistor stacked vertically over the third transistor, and a dielectric wall separating the first stacked transistor cell and the second stacked transistor cell. A first set of one or more channels of the first transistor have a first lateral distance to the dielectric wall and a second set of one or more channels of the second transistor have a second lateral distance to the dielectric wall, the first lateral distance being different than the second lateral distance. A third set of one or more channels of the third transistor have a third lateral distance to the dielectric wall and a fourth set of one or more channels of the fourth transistor have a fourth lateral distance to the dielectric wall, the third lateral distance being different than the fourth lateral distance. The stacked transistor structure advantageously allows for integrating connections to the first, second, third and fourth transistors within the cell boundaries of the first and second stacked transistor cells, where the cell boundary of the adjacent first and second stacked transistor cells is defined by the dielectric wall.
In embodiments, the first lateral distance is smaller than the second lateral distance and the third lateral distance is smaller than the fourth lateral distance. Such spacing advantageously enables formation of backside contacts to the second and fourth transistors.
In embodiments, at least one of: the first lateral distance is different than the third lateral distance; and the second lateral distance is different than the fourth lateral distance. Such spacing allows for different spacing between the first, second, third and fourth transistors and the dielectric wall, advantageously allowing for processing flexibility.
In embodiments, the first transistor and the third transistor are one of n-type transistors and p-type transistors, and the second transistor and the fourth transistor are the other one of n-type transistors and p-type transistors. Such configurations allow for the first and second stacked transistor cells to provide complementary field-effect transistors (CFET) cells.
According to an aspect of the invention, there is provided an integrated circuit including a semiconductor structure including a first transistor and a second transistor vertically stacked over the first transistor. The first transistor and the second transistor have horizontally aligned cell boundaries. A first set of one or more channels of the first transistor are horizontally offset from a second set of one or more channels of the second transistor within the horizontally aligned cell boundaries. The shifted first and second sets of one or more channels of the semiconductor structure advantageously allows for integrating connections to the first and second transistors within the horizontally aligned cell boundaries.
In embodiments, the first set of one or more channels of the first transistor have a first distance to the horizontally aligned cell boundaries at a first lateral side of the semiconductor structure and a second distance to the horizontally aligned cell boundaries at a second lateral side of the semiconductor structure opposite the first lateral side of the semiconductor structure, the first distance being greater than the second distance, and the second set of one or more channels of the second transistor have a third distance to the horizontally aligned cell boundaries at the first lateral side of the semiconductor structure and a fourth distance to the horizontally aligned cell boundaries at the second lateral side of the semiconductor structure opposite the first lateral side of the semiconductor structure, the third distance being less than the fourth distance. Such spacing of the first and second sets of one or more channels from the horizontally aligned cell boundaries advantageously allows for forming backside contacts to the second transistor within the horizontally aligned cell boundaries.
In embodiments, the semiconductor structure further includes a gate merge contact between a first gate region of the first transistor and a second gate region of the second transistor, wherein the gate merge contact is disposed within the horizontally aligned cell boundaries on a first side of the second set of channels and over a portion of the first set of channels. The gate merge contact advantageously allows for combined connections or contacts to the first and second gate regions which saves area.
In embodiments, the semiconductor structure further includes at least one contact to at least one of the first transistor and the second transistor which is within the horizontally aligned cell boundaries. The at least one contact being within the horizontally aligned cell boundaries advantageously provides area savings for the semiconductor structure.
As discussed above, stacked transistor structures provide an opportunity for continued scaling and area improvement. Stacked transistor structures may utilize sequential integration fabrication processes. Sequential integration includes forming “bottom” (also referred to as “lower”) transistors of a stacked transistor structure, followed by wafer bonding and formation of “top” (also referred to as “upper”) transistors of the stacked transistor structure. The bottom and top transistors of the stacked transistor structure may also be referred to as being different “tiers” or “levels” of the stacked transistor structure (e.g., where the bottom transistors are a first tier or level of the stacked transistor structure and the top transistors are a second tier or level of the stacked transistor structure). Sequential integration fabrication processes provide various advantages relative to monolithic fabrication processes. For example, sequential integration allows for: an increased effective width (Weff) with the same device footprint; increasing the number of channels (e.g., nanosheet channels); and further critical dimension (CD) scaling. Since the top and bottom tiers are integrated separately, sequential integration allows for unique transistor architectures (e.g., shifted, staggered, etc.), split gate schemes, multiple threshold voltage (multi-Vt) replacement metal gate (RMG) learning from nanosheets, channel engineering for the top and bottom tiers (e.g., mobility), and reduced process complexity.
Stacked transistor structures may use different transistor architectures, such as a “stepped” architecture (e.g., where nanosheet channels for the top transistors of a stacked transistor structure are narrower than nanosheet channels for the bottom transistors of the stacked transistor structure) and an “aligned” architecture (e.g., where nanosheet channels for the top and bottom transistors of a stacked transistor structure have the same size and are horizontally or laterally aligned with one another). Wafer bonding approaches used in sequential integration fabrication processes further allow for a “shifted” architecture (e.g., where the active regions or nanosheet channels for the top and bottom transistors of the stacked transistor structure are horizontally or laterally offset from one another) and a “staggered” architecture (e.g., where cell or device boundaries for the top and bottom transistors of the stacked transistor structure are offset from one another). Both the shifted and staggered architectures provide for lower aspect ratio (AR) for middle-of-line (MOL) contact formation, and also provide a Weff benefit with respect to the aligned active regions.
In some embodiments, a stacked transistor structure includes top transistors and bottom transistors with aligned cell boundaries (e.g., within lithography tolerance), where the top and bottom transistors in the stacked transistor structure have gate-all-around (GAA) channels (e.g., nanosheet channels) which are horizontally shifted relative to one another along the gate axis. The top and bottom transistors may have a first smaller distance to laterally adjacent transistors on a first lateral side and a second larger distance to laterally adjacent transistors on a second lateral side. For example, the top transistors may have the first smaller distance to first laterally adjacent transistors on the first lateral side and the second larger distance to laterally adjacent transistors on the second lateral side, while the bottom transistors have the second larger distance to the first laterally adjacent transistors on the first lateral side and the first smaller distance to laterally adjacent transistors on the second lateral side, or vice versa. The laterally adjacent transistors with the first smaller distance may be of the same polarity (e.g., n-type or p-type) while the laterally adjacent transistors with the second larger distance may be of different polarity. The aligned cell boundaries of the top and bottom transistors of the stacked transistor structure may be defined by gate cut dielectric layers.
In some embodiments, a first dielectric wall separates the gates of laterally adjacent transistors which are the first smaller distance away, with the first dielectric wall being at least partially covered by a high-k dielectric material. A second dielectric wall may separate the gates of laterally adjacent transistors which are the second larger distance away, and the second dielectric wall may not be covered by a high-k dielectric material. Dielectric walls between adjacent transistors having the first smaller distance from one another may have a bottom portion which is covered with a high-k dielectric material and a top portion which is not covered with the high-k dielectric material. The top portion may be wider than the bottom portion. A first distance between the channels and a dielectric wall of transistors of a same polarity may be different than a second distance between the channels and a dielectric wall of transistors with a different polarity. In some embodiments, distances between the channels and dielectric walls of the bottom transistors are different than the distances between the channels and dielectric walls of the top transistors.
In some embodiments, in a bottom region of the stacked transistor structure where the bottom transistors are formed, a backbone dielectric wall is covered by a silicon oxide material (e.g., with a thickness of 2 nm or greater), while in a top region of the stacked transistor structure where the top transistors are formed the backbone dielectric wall is not covered by the silicon oxide material or is covered with a silicon oxide material having a thickness less than 2 nm.
A process flow for forming a stacked transistor structure with aligned cell boundaries and shifted channels includes forming a nanosheet stack (e.g., of alternating Si/SiGe layers, or more generally nanosheet channel layers and sacrificial layers), and patterning the nanosheet stack so as to have the first smaller distance and the second larger distance between laterally adjacent active regions. Shallow trench isolation (STI) regions are then formed, followed by conformal deposition of an oxide layer (e.g., with a thickness that is about the same as a combined thickness of a gate dielectric layer and a gate work function metal (WFM) layer which will be used in a gate stack), followed by deposition of a nitride layer such that it pinches off the first smaller distance forming a dielectric “backbone” or wall.
The stacked transistor structures with aligned cell boundaries and shifted channels advantageously solve critical issues of integrating connections for stacked transistor structures, and advantageously enables both merged gates and split gates with significant area gains.
In some embodiments, a stacked transistor structure includes top and bottom transistors with channels that are horizontally or laterally shifted relative to one another within aligned cell boundaries for the top and bottom transistors. The stacked transistor structure may include a gate merge contact structure where gate regions for the top and bottom transistors within a stacked transistor cell are merged. This may be achieved through forming the gate contact structure in large gate extension regions, where the large gate extension regions for the top and bottom transistors are on opposed sides.
In some embodiments, a semiconductor terminal of the top transistor (e.g., a top source) is contacted from the bottom by a via which extends to a backside of the structure. Adjacent stacked transistor cells may have adjacent vias connecting to the top transistors of the stacked transistor cells. The adjacent vias may, in some embodiments, by merged to form a single large via rather than individualized vias. Further, in some embodiments, there may be only a single via for adjacent stacked transistor cells, such that only the “right” or “left” top transistor is connected through the single via to the backside of the structure. Still further, in some embodiments, only one via connects to the bottom of a semiconductor terminal of the top transistor (e.g., a top source), where the semiconductor terminal is merged with a semiconductor terminal for an adjacent top transistor.
In some embodiments, both top and bottom transistors of the stacked transistor structure are contacted from the bottom or backside of the structure. For example, sources of the top and bottom transistors of the stacked transistor structure may be contacted from the bottom or backside of the structure.
In some embodiments, power rail contacts are formed “inbound” within cell boundaries for the stacked transistor cells. In other embodiments, power rail contacts are formed “outbound” at least partially outside cell boundaries for the stacked transistor cells. Such power rail contacts may be symmetric or asymmetric.
In some embodiments, contacts to bottom transistors of the stacked transistor structure have kinks to avoid shorting to power rails from the top transistors. Such kinks may be formed by having backside contacts with two portions, a first wider portion adjacent to bottom or backside surfaces of sources of the bottom transistors of the stacked transistor structure, and a second narrower portion adjacent power rails of a backside power delivery network (BSPDN), where the second narrower portion is surrounded by a backside interlayer dielectric (ILD) layer.
In some embodiments, power rails for top and bottom transistors of the stacked transistor structure are merged across cell boundaries. Further, in some embodiments, different ones of the power rails may have different cross-section dimensions or widths. Backside contacts in the stacked transistor structure may be used for power delivery (e.g., VDD and VSS).
In some embodiments, source/drain regions of adjacent transistors (either bottom or top transistors of the stacked transistor structure) with a short separation distance can be merged with one another.
In some embodiments, two separate vias or contacts extending from the top transistors of the stacked transistor structure touch the same power rail. Similarly, in some embodiments two separate contacts from the bottom transistors of the stacked transistor structure may touch the same power rail.
The first substrate 102 and the second substrate 106 may be formed of any suitable semiconductor structure, including various silicon-containing materials including but not limited to silicon (Si), silicon germanium (SiGe), silicon germanium carbide (SiGeC), silicon carbide (SiC) and multi-layers thereof. Although silicon is the predominantly used semiconductor material in wafer fabrication, alternative semiconductor materials can be employed as additional layers, such as, but not limited to, germanium (Ge), gallium arsenide (GaAs), gallium nitride (GaN), SiGe, cadmium telluride (CdTe), zinc selenide (ZnSe), etc. The first substrate 102 and the second substrate 106 may have respective heights (in direction Z) and widths (in directions X/Y) which vary as needed based on the type of structures to be formed.
The etch stop layer 104 may comprise a buried oxide (BOX) layer formed of silicon dioxide (SiO2) or a layer formed by silicon germanium (SiGe), or another suitable material such as a III-V semiconductor epitaxial layer. The etch stop layer 104 may have a height (in direction Z) in the range of 10 to 50 nm.
The sacrificial layers 108 may be formed of SiGe. Each of the sacrificial layers 108 may have a thickness (in direction Z) in the range of 5-15 nm.
In some embodiments, both the etch stop layer 104 and the sacrificial layers 108 are formed of SiGe, with a germanium (Ge) concentration in the range of 20-40%. It should be noted, however, that this is not a requirement, and that the etch stop layer 104 and the sacrificial layers 108 may be formed of different materials, or may both be formed of SiGe but with different percentages of Ge.
The nanosheet channel layers 110 will provide channels for bottom transistors (e.g., nanosheet transistors) of the stacked transistor structure. The nanosheet channel layers 110 may be formed of Si or another suitable material (e.g., a material similar to that used for the first substrate 102 and the second substrate 106). Each of the nanosheet channel layers 110 may have a thickness (in direction Z) in the range of 4-15 nm.
The oxide layer 112 may have a thickness in the range of 1-4 nm, and may be formed of any suitable oxide such as SiO2.
The nitride layer 114 is deposited over the oxide layer 112. The nitride layer 114 may have a thickness in the range of 2-8 nm, and may be formed of any suitable nitride such as SiN.
The STI regions 116 are deposited over the nitride layer 114. The STI regions 116 may be formed of a dielectric material such as silicon dioxide (SiO2), silicon oxycarbide (SiOC), silicon oxynitride (SiON), etc. The STI regions 116 may have a thickness (in direction Z) in the range of 15-100 nm.
To form the STI regions 116, a hard mask (HM) may be patterned over the structure, followed by etching (e.g., using reactive-ion etching (RIE) or other suitable etch processing) portions of the structure exposed by the patterned HM to pattern active regions for the bottom transistors of the stacked transistor structure. The oxide layer 112 and nitride layer 114 may then be deposited, followed by deposition, planarization (e.g., using chemical mechanical planarization (CMP)) and recess of the material of the STI regions 116 below a bottommost one of the sacrificial layers 108. The HM may then be removed.
As illustrated in
Prior to formation of the source/drain regions 118, dummy gate structures (not shown) may be formed. The dummy gate structures may include dummy gates and a gate HM. The dummy gates may be formed of amorphous silicon (a-Si) or another suitable material such as amorphous silicon germanium (a-SiGe), etc. The gate HM (e.g., which may be formed of a multi-layer structure, such as an oxide-nitride-oxide multi-layer structure) may be patterned over the dummy gates. Although not shown, an outer spacer may deposited over the structure (e.g., formed of silicon boron carbide nitride (SiBCN) or another suitable material such as SiN, SiCO, etc.), with the outer spacer then being etched-back followed by an indent etch of the sacrificial layers 108 of the nanosheet stack and formation of inner spacers (not shown) in the indent regions formed by the indent etch of the sacrificial layers 108 of the nanosheet stack. The inner spacers may be formed of SiN, SiBCN, SiCO, combinations thereof, etc. The inner spacers may include an oxide liner with a thickness in the range of 1-2 nm before the nitride-base material deposition.
Following formation of the inner spacers, the source/drain regions 118 may be formed using an epitaxial growth process. The source/drain regions 118 may be suitably doped, such as using ion implantation, gas phase doping, plasma doping, plasma immersion ion implantation, cluster doping, infusion doping, liquid phase doping, solid phase doping, etc. N-type dopants may be selected from a group of phosphorus (P), arsenic (As) and antimony (Sb), and p-type dopants may be selected from a group of boron (B), gallium (Ga), indium (In), and thallium (Tl). In some embodiments, the epitaxy process used to form the source/drain regions 132 comprises in-situ doping (dopants are incorporated in epitaxy material during epitaxy). Epitaxial materials may be grown from gaseous or liquid precursors. Epitaxial materials may be grown using vapor-phase epitaxy (VPE), molecular-beam epitaxy (MBE), liquid-phase epitaxy (LPE), rapid thermal chemical vapor deposition (RTCVD), metal organic chemical vapor deposition (MOCVD), ultra-high vacuum chemical vapor deposition (UHVCVD), low-pressure chemical vapor deposition (LPCVD), limited reaction processing CVD (LRPCVD), or other suitable processes. Epitaxial silicon, silicon germanium (SiGe), germanium (Ge), and/or carbon doped silicon (Si: C) silicon can be doped during deposition (in-situ doped) by adding dopants, such as n-type dopants (e.g., phosphorus or arsenic) or p-type dopants (e.g., boron or gallium), depending on the type of transistor to be formed. The dopant concentration in the source/drain can range from 1×1019 cm−3 to 3×1021 cm−3, or preferably between 2×1020 cm−3 to 3×1021 cm−3. The source/drain regions 118 may have widths (in direction Y) which are at least the widths of the nanosheet channel layers 110 and heights (in direction Z) which are at least the height of the nanosheet stack for the bottom transistors of the stacked transistor structure.
Following formation of the source/drain regions 118, optional source/drain cut processing may be performed. The source/drain cut is an optional process, which may be advantageous for very scaled cells in order to mitigate shorting to metal contacts of the top transistors of the stacked transistor structure which connect to the backside of the structure, as will be discussed in further detail below. The source/drain cut process can be asymmetric with respect to the channel position, in the sense that the source/drain cut process may cut the source and/or the drain closer to channels on one side than the other side. The source/drain cut may also be done only on one side of the source and/or the drain for a particular transistor or multiple transistors. The source/drain cut can also be used to separate merged source/drain regions if desired. In some embodiments, the source/drain cut width and position may be different for the source and the drain of the same transistor, in order to facilitate contact formation as described in further detail below. The source/drain cut processing may include a fill material and planarization over the source/drain regions 118 and patterning a mask layer over the structure, where the mask layer may comprise photoresist, an organic planarization layer (OPL) or a HM, a combination of an OPL and a HM, etc. Portions of the source/drain regions 118 exposed by the patterned mask layer are then etched to result in cut or patterned source/drain regions 118.
Following the optional source/drain cut processing, a liner layer 120 is deposited over the structure. The liner layer 120 may be formed of materials similar to that of the nitride layer 114. The liner layer 120 may have a thickness in the range of 2-4 nm. An oxide layer 122 is formed using flowable chemical vapor deposition (FCVD) or other suitable processing to overfill the structure, followed by planarization (e.g., using CMP). The oxide layer 122 may be formed of an oxide plasma material, such as HARP or HDP oxides, or another suitable material.
Gate cut processing may then be performed to form the gate cut dielectric layers 124. The gate cut processing may include patterning of a HM (not shown) over the structure, followed by etching portions of the structure exposed by the HM down to the STI regions 116 to form gate cut trenches. The gate cut trenches are then filled with a dielectric material to form the gate cut dielectric layers 124, followed by removal of the HM. In some embodiments, the HM is removed before fill of the gate cut trenches. The dielectric material used for the gate cut dielectric layers 124 may be an oxide (e.g., SiO2) formed using chemical vapor deposition (CVD) processing, or another suitable material such as SiN or a multilayer of SiN and SiO2. The gate cut dielectric layers 124 are examples of “dielectric walls” which define cell boundaries in stacked transistor structures as discussed elsewhere herein.
As illustrated in
The gate stack for the bottom transistors of the stacked transistor structure is then formed. The gate stack for the bottom transistors of the stacked transistor structure includes a gate dielectric layer 126, a gate work function metal (WFM) layer 128 and a gate metal layer 130. Optional gate self-aligned contact (SAC) capping layers 132 may be formed over the gate stack for the bottom transistors of the stacked transistor structure.
The gate stacks for the bottom transistors of the stacked transistor structure may be formed using replacement metal gate (RMG) processing. The dummy gate structures (e.g., the gate HM and the underlying dummy gates, not shown) are removed using CMP and any suitable etch processing. A channel release is then performed by etching or otherwise removing the sacrificial layers 108 of the nanosheet stack. The gate stacks are then formed. The gate stacks include an interlayer (IL) oxide layer (not shown), the gate dielectric layer 126, the gate WFM layer 128, and the gate metal layer 130. The gate stacks may then be recessed, followed by formation of the gate SAC capping layers 132. It should be noted that, in some embodiments, the gate SAC capping layers 1326 are not used. In other words, the gate SAC capping layers 132 are optional layers. The gate SAC capping layers 132 are advantageously used in some embodiments for enabling self-aligned contacts in ultra scaled cells.
The IL oxide (not labeled) may be formed of SiO2 or another suitable material, and may have a thickness in the range of 1-5 nm. The gate dielectric layer 126 may be conformally deposited in the structure, and may be formed of a high-k material. Examples of high-k materials include but are not limited to metal oxides such as HfO2, hafnium silicon oxide (Hf-Si-O), hafnium silicon oxynitride (HfSiON), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAlO3), zirconium oxide (ZrO2), zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide (Ta2O5), titanium oxide (TiO2), barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide (Y2O3), aluminum oxide (Al2O3), lead scandium tantalum oxide, and lead zinc niobate. The high-k material may further include dopants such as lanthanum (La), aluminum (Al), and magnesium (Mg). The gate dielectric layer 126 may have a uniform thickness in the range of 1 nm to 3 nm.
The gate conductor includes the gate WFM layer 128 and the gate metal layer 130. The gate WFM layer 128 may be formed of a WFM such as titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), aluminum (Al), titanium aluminum (TiAl), titanium aluminum carbon (TiAIC), a combination of Ti and Al alloys, a stack which includes a barrier layer (e.g., of TiN, TaN, etc.) followed by one or more of the aforementioned WFM materials, etc. The gate WFM layer 128 may have a uniform thickness in the range of 5-10 nm. The gate metal layer 130 may comprise a conductive metal (e.g., tungsten (W)).
The gate SAC capping layers 132 may be formed of SiN, silicon carbide (SiC) or another suitable material. The gate SAC capping layers 132 may have a height (in direction Z) in the range of 10-20 nm.
The placeholder layers 134 may be formed by patterning a HM (which may comprise a multi-layer structure, such as an oxide-nitride or oxide-nitride-oxide multi-layer structure, not shown) over the structure, followed by etching through exposed portions of the structure down to the nitride layer 114 to form placeholder vias. Material for the placeholder layers 134 is then deposited in the placeholder vias and planarized (e.g., using CMP). The HM used in patterning of the placeholder vias may be removed using WET or dry etch processing, using CMP or other planarization techniques, combinations thereof, etc. The placeholder layers 134 advantageously allow for contacting terminals of the top transistors of the stacked transistor structure from the backside without using additional cell space, as the placeholder layers 134 are “hidden” or tucked under the top transistors.
In some embodiments, some of the placeholder layers 134 illustrated in
The placeholder layers 134 may be filled in the placeholder vias using various deposition methods, including but not limited to CVD, plasma enhanced CVD (PECVD), atomic layer deposition (ALD), epitaxy processing, metal-organic CVD (MOCVD), etc. After deposition of the material for the placeholder layers 134, a thermal treatment may be applied. CMP may be used to planarize the surface of the placeholder layers 134 and remove excess deposited material. The placeholder layers 134 may comprise Si, SiGe, a doped semiconductor such as boron-doped silicon (Si:B) or boron-doped silicon germanium (SiGe:B). In some embodiments, the placeholder layers 134 are formed of a dielectric material with a different composition than surrounding dielectrics, such that the placeholder layers 134 may later be selectively etched from the backside.
A liner layer 136 is deposited over the structure, followed by formation of a bonding dielectric layer 138. The liner layer 136 may be formed of SiN or another suitable material such as SiBCN, SiC, SiCO, SiON or other combinations of Si, oxygen (O), carbon (C) and nitrogen (N). The bonding dielectric layer 138 may be formed of one or more dielectric layers, such as SiN and SiO2, SiC, SiBCN, SiON, or other combinations of Si, oxygen (O), carbon (C) and nitrogen (N). In some embodiments, the liner layer 136 includes a 1-10 nm thick layer of SiN, SiCN or SiBCN, and the bonding dielectric layer 138 includes a 5-50 nm thick layer of SiO2.
The nanosheet stack for the top transistors of the stacked transistor structure includes the alternating sacrificial layers 140 and nanosheet channel layers 142, which may be formed of similar materials and with similar sizing as the sacrificial layers 108 and the nanosheet channel layers 110, respectively. The nanosheet stack for the top transistors of the stacked transistor structure may be grown on a donor substrate (not shown), followed by bonding of the donor substrate to the existing structure and removing the donor substrate from the back side. In some embodiments, the donor substrate comprises 001-Si or 110-Si. The backside removal of the donor substrate may include: (1) backside grinding from typically 775 micrometers (μm) to about 5-30 μm; (2) polishing such as using CMP to remove grinding defects such as scratches to obtain a mirror-like surface; and (3) removal of the remaining Si using a wet etch chemistry such as an ammonia-based chemistry, TEAH or TMAH. Such wet etch chemistries are advantageously selective to the sacrificial layers 154 (e.g., formed of SiGe). One or more etch stopping layers (not shown) may be used to obtain a flat surface, with the last etch stopping layer then being removed to expose the topmost one of the nanosheet channel layers 142.
In some embodiments, a process that can be used to detach the surface layer from the donor substrate is Smart-cut, which is based on a controlled cleavage layer made by implantation of hydrogen (H), which may be combined with helium (He) implantation, and thermal treatment. The ion implantation may be done before bonding of the donor substrate to the bonding dielectric layer 138, and the thermal treatment may be done after such bonding to cleave and separate the nanosheet stack for the top transistors of the stacked transistor structure from the donor substrate. This may be followed by CMP and wet etch removal of any remaining portion of the donor substrate and the etch stopping layer.
Once the nanosheet stack for the top transistors of the stacked transistor structure is attached to the bonding dielectric layer 138, it may be patterned using processing similar to that described above with respect to patterning of the nanosheet stack for the bottom transistors of the stacked transistor structure. As illustrated in
The dummy gate structures include an oxide layer 144, a dummy gate layer 146, and a gate HM including oxide layer 148 and nitride layer 150. Such layers may be formed using similar processing, and with similar materials, as the dummy gate structures for the bottom transistors (not shown, discussed above). However, following etch-through of the nanosheet stack for the top transistors of the stacked transistor structure, the bonding dielectric layer 138 and the liner layer 136 are etched through, exposing the top of the placeholder layers 134, before the source/drain epitaxy processing for the source/drain regions 152 for the top transistors of the stacked transistor structure (which may use processing similar to that described above with respect to the source/drain regions 118 for the bottom transistors of the stacked transistor structure). Thus, the placeholder layers 134 provide a template for the epitaxy of the terminal to grow directly from the placeholder layers 134 in addition to growing from the exposed edges of the nanosheet channel layers 142. Further, as shown in the regions 403 and 405 of
In some embodiments, optional gate merge vias may be formed. To form the gate merge vias, the dummy gate structures may be removed (e.g., the gate HM including oxide layer 148 and nitride layer 150, the dummy gate layers 146, and the oxide layer 144), followed by a channel release which removes the sacrificial layers 140. An IL oxide layer (not shown) is then conformally deposited, followed by formation of a gate dielectric layer 160 which is formed of similar materials and with similar sizing as the gate dielectric layer 126. A sacrificial layer may then be patterned over the structure, followed by etching through exposed portions of the structure down to the gate metal layer 138 for the bottom transistors of the stacked transistor structure to form gate merge vias. Subsequent metallization of the gate cavity for the top transistors of the stacked transistor structure creates a conductive metal connection between gates of the top and bottom transistors of the stacked transistor structure, as highlighted in regions 501 shown in
To complete formation of the gate stack for the top transistors of the stacked transistor structure, the sacrificial layer is removed, followed by formation of a gate WFM layer 162 and a gate metal layer 164 which are formed of similar materials and with similar sizing as the gate WFM layer 128 and the gate metal layer 130, respectively. Optional gate SAC capping layers 166 are then formed using similar processing, and with similar sizing and materials, as the gate SAC capping layers 132.
A dielectric layer 168 is then formed, which may be formed of a suitable dielectric such as an oxide material. To form the MOL contacts 170, one or more mask layers are patterned over the structure, followed by etching through portions of the structure exposed by such mask layers to form vias to the semiconductor terminals that the MOL contacts 170 connect to. A silicide layer is formed in the surface of the exposed semiconductor material of the source/drain terminals in the vias for the MOL contacts 170-1 and 170-2, followed by fill of a conductive material such as tungsten (W) or another suitable material. The vias for the MOL contacts 170-3 are filled of a conductive material such as tungsten (W) or another suitable material. The MOL contacts 170-1 connect to the source/drain regions 118 of the bottom transistors of the stacked transistor structure, the MOL contacts 170-2 connect to the source/drain regions 152 of the top transistors of the stacked transistor structure, and the MOL contacts 170-3 connect to the gate metal layer 164 of the gate stack of the top transistors of the stacked transistor structure. The gate merge vias in regions 501 allow the MOL contacts 170-3 to also connect to the gate metal layer 130 of the gate stack of the bottom transistors of the stacked transistor structure (e.g., the top and bottom transistors of the stacked transistor structure may have merged gates). BEOL interconnects 172 are then formed. The BEOL interconnects 172 may include one or more via and metal levels as needed to performed desired interconnections.
The structure is bonded to a carrier wafer (not shown), which may be formed of Si or another suitable material, and is then flipped to perform backside processing. This includes etching (e.g., using grinding, CMP, RIE and WET) the first substrate 102, the etch stop layer 104, and the second substrate 106. Different WETs or other etching processes may be used to sequentially remove the first substrate 102 (e.g., formed of Si), the etch stop layer 104 (e.g., formed of SiGe), and the second substrate (e.g., formed of Si). Such processing exposes the source/drain regions 118 for the bottom transistors of the stacked transistor structure.
Material for the backside ILD layer 174 may be deposited to overfill the structure, followed by planarization (e.g., using CMP). The backside ILD layer 174 may be formed of a dielectric material such as SiN, a flowable oxide, Si-C-O-N based materials, etc.
The backside contacts 176 are formed in a multi-step process. First, a mask layer may be patterned over the backside of the structure, exposing portions of the backside ILD layer 174 where the backside contacts 176 will be formed. The exposed portions of the backside ILD layer 174 are then etched to expose the backside of the source/drain regions 118, followed by formation of a silicide and metal fill and planarization in the trenches formed by the removal of the exposed portions of the backside ILD layer 174, and recess of the metal filled in the trenches. This forms a first portion of the backside contacts 176 having the width 601 (e.g., the portion proximate the backside surfaces of the source/drain regions 118 for the bottom transistors of the stacked transistor structure). Material for the backside ILD layer 174 is then redeposited to fill the structure, and is planarized. Next, another mask layer is patterned over the structure to reveal only a portion of the backside ILD layer 174 filled over the first portion of the backside contacts 176. The exposed portions of the backside ILD layer 174 are then etched to form trenches for a second portion of the backside contacts 176. A metal fill and planarization process is then performed to form the second portion of the backside contacts 176 having the width 603 (e.g., the portion which is adjacent the backside ILD layer 176). The backside contacts 176 may be formed of W or another suitable material.
The backside contacts 701 are formed by patterning a mask over the structure and removing exposed portions of the backside ILD layer 174 to reveal the backside surfaces of the source/drain regions 118 for the bottom transistors of the stacked transistor structure. The backside contacts 701 are then filled in the trenches formed by removal of the exposed portions of the backside ILD layer 174 as illustrated. The backside contacts 701 may be formed of similar materials as the backside contacts 176 (including a silicide layer and a conductive material such as W). The backside contacts 701 may also be formed by removing optional placeholder layers.
To form the backside contacts 178, the placeholder layers 134 are first removed (e.g., using any suitable etch processing). Material for the backside contacts 178 is then deposited in the vias formed by removal of the placeholder layers 134. The backside contacts 178 may be formed of similar materials as the backside contacts 176. A silicidation of the exposed backside surfaces of the source/drain regions 152 of the top transistors of the stacked transistor structure may be performed prior to metal fill of the backside contacts 178. In some embodiments, the backside contacts 178 are formed prior to the backside contacts 176 (or, alternatively, the backside contacts 701 of
The BSPDN 180 may include one or more metal levels, although only a single metal level is shown in
As shown in
It should be noted that, in some embodiments the bottom transistors of one or more of the stacked transistors cells 801 comprise one of nFETs and pFETs and the top transistors of the stacked transistor cells 801 comprise the other one of nFETs and pFETs (e.g., the bottom transistors may be nFETs and the top transistors may be pFETS, or the bottom transistors may be pFETs and the top transistors may be nFETs). The nFETs utilize nFET WFM materials in their gate stacks and n-type dopants in their source/drain regions, while the pFETS utilize pFET WFM materials in their gate stacks and p-type dopants in their source/drain regions. In other embodiments, the bottom transistors and top transistors of one or more of the stacked transistor cells 801 may be a same type (e.g., both nFETs or both pFETs).
The alternate configurations shown in
The placeholder layers 1001 may be formed following nanosheet source/drain recess, or after formation of the inner spacers. The placeholder layers 1001 may be formed by etching into the second substrate 106 to create trenches, followed by deposition of material for the placeholder layers 1001. The material for the placeholder layers 1001 may comprise a semiconductor material which may be obtained by the deposition or epitaxial growth of SiGe, SiGe: B, Si: B, combinations thereof, a dielectric material such as SiO2 or SiN based materials, etc. If needed, the material of the placeholder layers 1001 may be etched back such that top surfaces thereof are under or below the bottommost one of the nanosheet channel layers 110. The placeholder layers 1001 may be formed in one or both sides of the transistors, and may include forming a spacer to protect gate regions. The placeholder layers 1001 facilitate later formation of the backside contacts (e.g., backside contacts 176/701).
A process flow for forming stacked transistor structures with aligned cell boundaries and shifted channels with another type of gate-all-around (GAA) structure will now be described.
The structure of
Following formation of the STI regions 1316, a liner layer 1317 is deposited over the structure. The liner layer 1317 may be referred to as a dielectric wall liner for the bottom transistors of the stacked transistor structure, and may be formed of SiO2. The liner layer 1317 may have a uniform thickness in the range of 4-10 nm.
The dielectric wall layer 1319 may be formed of SiN or another suitable material such as SiBCN, SiCO, SiC, etc. The material for the dielectric wall layer 1319 may initially be deposited over the entire structure, followed by an isotropic etch of the material of the dielectric wall layer 1319 to reveal the nanosheet stack. The dielectric wall layer 1319 pinches off, and is thus not completely removed during this isotropic etch. Next, an isotropic etch of the liner layer 1317 is performed to reveal the top surfaces of the STI regions 116 and the nanosheet stack.
The source/drain regions 1318, the liner layer 1320, the oxide layer 1322, and the gate cut dielectric layers 1324 may be formed of similar materials and using similar processing as that described above with respect to the source/drain regions 118, the liner layer 120, the oxide layer 122 and the gate cut dielectric layers 124, respectively. Following removal of the dummy gate structures, an isotropic etch which removes portions of the liner layer 1317 is then performed.
In the structure of
The source/drain regions 1352, the liner layer 1354, the oxide layer 1356, the gate cut dielectric layers 1358, the gate dielectric layer 1360, the gate WFM layer 1362, the gate metal layer 1364, the gate SAC capping layers 1366, the MOL contacts 1370, the BEOL interconnects 1372, the backside ILD layer 1374, the backside contacts 1376, the backside contacts 1378, the BSPDN 1380, the power rails 1382 and the dielectric layers 1384 are formed of similar materials and with similar sizing and processing as that described above with respect to the source/drain regions 152, the liner layer 154, the oxide layer 156, the gate cut dielectric layers 158, the gate dielectric layer 160, the gate WFM layer 162, the gate metal layer 164, the gate SAC capping layers 166, the MOL contacts 170, the BEOL interconnects 172, the backside ILD layer 174, the backside contacts 176, the backside contacts 178, the BSPDN 180, the power rails 182 and the dielectric layers 184, respectively.
As shown in
Semiconductor devices and methods for forming the same in accordance with the above-described techniques can be employed in various applications, hardware, and/or electronic systems. Suitable hardware and systems for implementing embodiments of the invention may include, but are not limited to, personal computers, communication networks, electronic commerce systems, portable communications devices (e.g., cell and smart phones), solid-state media storage devices, functional circuitry, etc. Systems and hardware incorporating the semiconductor devices are contemplated embodiments of the invention. Given the teachings provided herein, one of ordinary skill in the art will be able to contemplate other implementations and applications of embodiments of the invention.
In some embodiments, the above-described techniques are used in connection with semiconductor devices that may require or otherwise utilize, for example, complementary metal-oxide-semiconductor (CMOS) transistors, metal-oxide-semiconductor field-effect transistors (MOSFETs), and/or fin field-effect transistors (FinFETs). By way of non-limiting example, the semiconductor devices can include, but are not limited to CMOS, MOSFET, and FinFET devices, and/or semiconductor devices that use CMOS, MOSFET, and/or FinFET technology.
Various structures described above may be implemented in integrated circuits. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either: (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.
It should be understood that the various layers, structures, and regions shown in the figures are schematic illustrations that are not drawn to scale. In addition, for ease of explanation, one or more layers, structures, and regions of a type commonly used to form semiconductor devices or structures may not be explicitly shown in a given figure. This does not imply that any layers, structures, and regions not explicitly shown are omitted from the actual semiconductor structures. Furthermore, it is to be understood that the embodiments discussed herein are not limited to the particular materials, features, and processing steps shown and described herein. In particular, with respect to semiconductor processing steps, it is to be emphasized that the descriptions provided herein are not intended to encompass all of the processing steps that may be required to form a functional semiconductor integrated circuit device. Rather, certain processing steps that are commonly used in forming semiconductor devices, such as, for example, wet cleaning and annealing steps, are purposefully not described herein for economy of description.
Moreover, the same or similar reference numbers are used throughout the figures to denote the same or similar features, elements, or structures, and thus, a detailed explanation of the same or similar features, elements, or structures are not repeated for each of the figures. It is to be understood that the terms “approximately” or “substantially” as used herein with regard to thicknesses, widths, percentages, ranges, temperatures, times and other process parameters, etc., are meant to denote being close or approximate to, but not exactly. For example, the term “approximately” or “substantially” as used herein implies that a small margin of error is present, such as ±5%, preferably less than 2% or 1% or less than the stated amount.
In the description above, various materials, dimensions and processing parameters for different elements are provided. Unless otherwise noted, such materials are given by way of example only and embodiments are not limited solely to the specific examples given. Similarly, unless otherwise noted, all dimensions and process parameters are given by way of example and embodiments are not limited solely to the specific dimensions or ranges given.
The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
