Patent Grant
9360525
1. Field of the Invention
The present invention relates to electronic fuses (e-fuses). More specifically, the present invention relates to stacked via structures for metal fuse applications.
2. Description of the Related Art
In advanced technologies, e-fuses have been implemented at the polycrystalline silicon (PC) level. During programming, a high current pulse of short duration is passed through the structure. This irreversibly migrates silicide on top of the PC, causing a change in resistance and thus acting as a programmable fuse.
As scaling progresses, it is becoming harder to implement these e-fuses at the PC level due to drop in maximum allowable currents through the first metal layer or conductor. Also, the collateral damage associated with the event is becoming more difficult to contain. As a result, there is a drive to implement these fuses at the metal interconnect levels and use the phenomenon of electromigration (EM) to program the fuses.
The power requirements to cause EM in copper (Cu) interconnects are much larger than the typical PC level fuses. This is partly due to the fact that the liner materials used in Cu interconnects, such as tantalum (Ta) and tantalum nitride (TaN), must be blown along with the Cu in order to achieve proper fuse programming. Hence, there is a need to devise fuse structures that are susceptible to EM without compromising the reliability of the remaining interconnects.
In a conventional metal fuse approach, as shown in
With this design, some of the failures occur in via 21 while other failures occur in line 22, resulting in a lack of control over the failure location and leading to variability in the final resistance of the fuse structure after programming. Moreover, it is not possible to electrically determine whether the failure is in via 21 or line 22. Failures in line 22 are less desirable because cap layer 23 may be compromised during the programming process.
The programming process with this design may lead to damage in the surrounding dielectric layer 20. It is likely that material from the blown fuse area will be present in the damaged dielectric region. If this is the case, then there is concern that the material will migrate throughout the dielectric, causing a short circuit to neighboring lines.
Therefore, a structure is needed such that failures occur preferentially in the via and not the line. Also, a detection method is needed to determine whether the programming process causes damage in the via or the line. The structure should allow for determining whether material from the blown fuse area has migrated into the dielectric region. It would also be desirable to prevent further migration of the blown fuse material.
The present invention provides a back end of the line fuse structure. The fuse structure promotes failures in certain areas of a fuse. The present invention further provides a method for detecting where the failures occur in a fuse and a method for detecting damage in a fuse.
According to an embodiment of the present invention, a fuse structure is provided. The fuse structure includes: a first dielectric layer having a first conductive via and a first conductive line disposed in a first cavity formed in the first dielectric layer, the first conductive via and the first conductive line having a first liner disposed along at least vertical surfaces of the first cavity; a second dielectric layer above the first dielectric layer, the second dielectric layer having a second conductive via and a second conductive line disposed in a second cavity formed in the second dielectric layer, the second conductive via and the second conductive line being in electrical contact with the first conductive via and the first conductive line, and having a second liner disposed along at least vertical surfaces of the second cavity; wherein at least a portion of the first liner has a thickness less than the second liner.
According to a further embodiment of the present invention, another fuse structure is provided. The fuse structure includes: a first dielectric layer having a first conductive via and a first conductive line within a first dual damascene cavity formed in the first dielectric layer, the first conductive via and the first conductive line surrounded laterally by a first liner; a second dielectric layer above the first dielectric layer having a second conductive via and a second conductive line embedded within a second dual damascene cavity formed in the second dielectric layer, the second conductive via and second conductive line in electrical contact with the first conductive via and the first conductive line and surrounded laterally by a second liner; wherein the first liner surrounding laterally the first conductive via and the first conductive line has a thickness of less than about 30 nm, the second liner surrounding laterally the second conductive via and the second conductive line has a thickness of greater than about 30 nm.
According to another embodiment of the present invention, a further fuse structure is provided. The fuse structure includes: a first dielectric layer having a first conductive via and a first conductive line disposed in a first cavity formed in the first dielectric layer, the first conductive via and the first conductive line having a first liner disposed along at least vertical surfaces of the first cavity; a second dielectric layer disposed on the first dielectric layer, the second dielectric layer having a second conductive via and a second conductive line disposed in a second cavity formed in the second dielectric layer, the second conductive via and the second conductive line being in electrical contact with the first conductive via and the first conductive line, the second conductive line laterally extending around the second conductive via such that the conductive line extends in all directions wider than at least a diameter of an upper portion of the first conductive via, and having a second liner disposed along at least vertical surfaces of the second cavity; wherein the first liner has a thickness less than the second liner.
According to a further embodiment of the present invention, a method for electrically detecting failures in a conductive via and a conductive line is provided. The method includes the steps of: forcing current through a fuse structure between a positive current connection and a negative current connection; measuring voltage over each of a first voltage connection and a second voltage connection in the fuse structure; and detecting a failure in one of a conductive via and a conductive line; wherein failure occurs in the conductive via if an open circuit exists at both the first and second voltage connections such that there is no current flow at the voltage connections when current is forced; and wherein a failure occurs in the conductive line if an open circuit exists at only one of the first and second voltage connections such that there is no current flow at one of the voltage connections and an open circuit does not exist at the other when current is forced.
According to another embodiment of the present invention, a method for electrically detecting damage in dielectric regions of a fuse is provided. The method includes the steps of: applying voltage between a negative current connection and a positive current connection; measuring current between a positive current connection and a negative current connection; and detecting damage in a dielectric region wherein damage exists and has extended where a short circuit is measured between the positive current connection and the negative current connection.
According to a further embodiment of the present invention, a fuse structure for detecting material from damage by a blown fuse is provided. The fuse structure includes: a first dielectric layer disposed on the dielectric material having a first conductive via and a first conductive line disposed in a first cavity formed in the first dielectric layer, the first conductive via and the first conductive line having a first liner disposed along at least vertical surfaces of the first cavity; a second conductive via and a second conductive line disposed in a second cavity formed in the first dielectric layer and having a second liner disposed along at least vertical surfaces of the second cavity, wherein the second conductive via and the second conductive line are not in contact with the first conductive via and the first conductive line; a second dielectric layer disposed on the first dielectric layer, the second dielectric layer having a third conductive via and a third conductive line disposed in a third cavity formed in the second dielectric layer, the third conductive via and the third conductive line being in electrical contact with the first conductive via and the first conductive line, the second conductive line laterally extending around the third conductive via such that the third conductive line extends in all directions wider than at least a diameter of an upper portion of the first conductive via, and having a third liner disposed along at least vertical surfaces of the third cavity; wherein the first liner has a thickness less than the second liner.
According to another embodiment of the present invention, a method of manufacturing a fuse structure is provided. The method includes the steps of: forming a first cavity in a first dielectric layer, the first dielectric layer disposed on a dielectric material, the dielectric material having a conductor embedded therein, the first cavity in contact with the conductor; depositing a first liner on all surfaces of the first cavity; depositing a seed layer in the first cavity; filling the first cavity with a conductive material forming a first via and a first line; depositing a second dielectric layer laterally disposed on the first cavity; forming a second cavity in the second dielectric layer; depositing a second liner on all surfaces of the first cavity; depositing a second seed layer in the cavity; and filling the second cavity with a conductive material forming a second via and a second line, the second via and the second line being in electrical contact with the first via and the first line.
The features and elements of the present invention are set forth with respect to the appended claims and illustrated in the drawings.
The present invention provides a back end of the line (BEOL) fuse structure having a stack of vias. The stacking of vias leads to high aspect ratios, which makes liner and seed coverage inside of the vias poorer. This weakness in the liner and seed layers leads to a higher probability of electromigration (EM) failure. The present invention includes a fuse structure to address failures due to poor liner and seed coverage. Design features allow for determining the extent of the damaged region following fuse programming. Other design features make it possible to prevent further propagation of the damaged dielectric region.
The following describes embodiments of the present invention with reference to the drawings. The embodiments are illustrations of the invention, which can be embodied in various forms. The present invention is not limited to the embodiments described below, rather representative for teaching one skilled in the art how to make and use it. Some aspects of the drawings repeat from one drawing to the next. The aspects retain their same numbering from their first appearance throughout each of the preceding drawings.
With reference now to
Dielectric layer 130 is disposed above dielectric layer 120. Conductive via 132 and conductive line 133 are disposed in cavity 131 formed in dielectric layer 130. Conductive via 132 and line 133 are in electrical contact with conductive via 122 and conductive line 123. Liner 134 is disposed along at least vertical surfaces of cavity 131. Preferably, liner 134 is further disposed along a horizontal surface 135 beneath line 133, a bottom surface of cavity 131 and vertical surfaces of conductive line 133. The electron flow through the fuse structure is from the lower level metal, conductor 111, through conductive via 122, conductive line 123 and conductive via 132, to the upper level metal, conductive line 133.
Liner 124 preferably has poor coverage as compared to at least one portion of liner 134. Liner 124 preferably has a thickness less than the thickness of liner 134 such that upon application of high current between the positive current connection (I+) and negative voltage connection (I−) to induce electromigration (EM) failure, failure occurs preferentially in conductive via 122 rather than in conductive via 132 or conductive line 133. Specifically, liner 124 preferably has a thickness of less than about 30 nm and liner 134 preferably has a thickness of greater than about 30 nm. In this structure, EM failures are more likely to occur in conductive via 122 rather than in conductive via 132 or conductive line 133, because relatively lower power is required to cause a failure in conductive via 122 due to the poor coverage of liner 124.
Any suitable dielectric material may be used for dielectric material 110 and dielectric layers 120 and 130. The material used for each of dielectrics 110, 120 and 130 may be the same or different. Typical dielectric materials include any now known or later developed porous or non-porous dielectric material such as silicon oxide (SiO), silicon nitride (Si3N4), hydrogenated silicon oxycarbide (SiCOH), silsesquioxanes, carbon-doped oxides (i.e., organosilicates) that include atoms of silicon (Si), carbon (C), oxygen (O), and/or hydrogen (H), thermosetting polyarylene ethers, SiLK™ (a polyarylene ether available from Dow Chemical Corporation), spin-on silicon-carbon contained polymer material available from JSR Corporation, and other low dielectric constant (<3.9) materials or layers thereof.
A dielectric barrier layer or capping layer is disposed above each of dielectric material 110 and dielectric layers 120 and 130. The material used for each capping layer may be the same or different. Typical dielectric materials for the capping layer include any now known or later developed dielectric layer such a silicon carbide (SiC), silicon nitride (Si3N4), silicon dioxide (SiO2), and nitrogen or hydrogen doped silicon carbide (SiC(N,H)).
Any suitable liner material may be used for liners 124 and 134, and the material used for each of liners 124 and 134 may be the same or different. Typical liner materials include tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), tungsten (W), ruthenium (Ru) and ruthenium nitride (RuN).
Any suitable conductive material may be used for conductor 111, conductive via 122, conductive line 123, conductive via 132 and conductive line 133. The material used for each of conductor 111, conductive via 122, conductive line 123, conductive via 132 and conductive line 133 may be the same or different. Typical conductive materials include copper (Cu), aluminum (Al), silver (Ag), gold (Au) and alloys.
Due to the nature of the liner deposition process, liner coverage in the via depends on which via sidewall is being covered. In the case of Ta and TaN, a physical vapor deposition (PVD) process is used such that the line feature above the via will affect the liner coverage in the via. The same holds for the Cu seed layer that is deposited by PVD following liner deposition. In
In order to combat the shadowing effect, a further embodiment of the present invention permits good liner and seed coverage throughout conductive via 132, because failures may still occur in conductive via 132 and conductive line 133. In a preferred embodiment of the present invention, liner coverage can be influenced by the extent to which the line opening extends laterally beyond the via opening. As shown in
Extending conductive line 133 also provides the ability to electrically distinguish between failures in conductive via 122, conductive via 132 and conductive line 133. Following fuse programming where a high current is forced through the fuse structure to blow the fuse, current is forced between a positive current connection (I+) at conductive line 133 and a negative current connection (I−) at conductor 111. The voltage across the structure would be measured over a positive voltage connection (V+) along conductive line 133 and a negative voltage connection (V−) at conductor 111. If an open circuit is measured at both of the positive (V+) voltage connections and the negative (V−) voltage connection, then the failure occurred in a conductive via, for example conductive via 122 in
Forcing high current through the fuse structure during fuse programming will likely lead to damage in the surrounding dielectric layer. If conductive via 122 fails, then the resulting damage could be electrically detected by placing vias and lines next to the fuse structure, shown in
The fuse structure shown in
Next, dielectric layer 130 is deposited on layer 120, an opening or cavity 131 is formed in dielectric layer 130, liner 134 is deposited on surfaces of cavity 131, a Cu seed layer is deposited and cavity 131 is filled with a conductive material to form conductive via 132 and conductive line 133. Optionally, conductive line 133 is formed in such a way as to extend in all directions around conductive via 132.
Dielectric layers 120 and 130 can be deposited by a variety of methods. Chemical vapor deposition (CVD) is the preferred method for carbon-doped oxide dielectrics (SiCOH). Spin on processes are the preferred methods for polymer based dielectrics.
Cavity 121 may be formed using any suitable lithographic patterning and etching process. Conductive vias 122 and 132 and conductive lines 123 and 133 may be formed using a single or dual damascene process. Preferably, a dual damascene process is used.
A physical vapor deposition (PVD) process is used to deposit liner materials such as Ta and TaN. Other deposition processes, such as chemical vapor deposition (CVD) and atomic layer deposition (ALD), may be used to deposit liner materials as well.
To promote a failure in the lower via as opposed to the upper via or line, it is preferred to create poor liner coverage in conductive via 122 and good liner coverage in conductive via 132. Multiple embodiments for creating poor liner coverage are shown in
In order to undercut sidewalls 127 and 128 of conductive via 122, the dielectric layer is reactive ion etched through a hardmask for pattern transfer. This creates a dielectric-hardmask stack where the reactive ion etched conductive via 122 has a dense hardmask material on top. The dielectric layer is always a less-dense material than the hardmask, which means that it tends to be more deformable and more easily etchable by, for example, reactive ion etch and wet etches. Moreover, it is more easily deformed by, for example, heating, outgassing, and moisture desorption. The result is that the liner and seed deposition is likely to have a hardmask feature on top that has tighter dimensional tolerances for the patterned features than the less-dense dielectric layer that it serves to pattern. An undercut process can be performed using any low-k dielectric; however the effects of the undercut process are more pronounced using an ultra low-k dielectric. Consequently, an undercut is easy to create or engineer, simply on the basis of selection of a wet clean or reactive ion etch that is selective to the ultra low-k dielectric versus the hardmask, or to degas conditions that cause more shrinkage of the ultra low-k dielectric versus the hardmask. An ultra low-k dielectric material has a dielectric constant less than 2.7.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiment was chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated.
This application is a divisional of application Ser. No. 14/040,945, filed Sep. 30, 2013, currently pending, which is a divisional of application Ser. No. 13/074,407, filed Mar. 29, 2011, now U.S. Pat. No. 8,633,707. Each patent application identified above is incorporated here by reference in its entirety to provide continuity of disclosure.
| Number | Name | Date | Kind |
|---|---|---|---|
| 6100116 | Lee et al. | Aug 2000 | A |
| 6100118 | Shih et al. | Aug 2000 | A |
| 6157583 | Starnes et al. | Dec 2000 | A |
| 6218279 | Weber et al. | Apr 2001 | B1 |
| 6370074 | Jeffery et al. | Apr 2002 | B1 |
| 6444503 | Yu | Sep 2002 | B1 |
| 6459633 | Jeffery et al. | Oct 2002 | B1 |
| 6521971 | Tsai | Feb 2003 | B2 |
| 6555458 | Yu | Apr 2003 | B1 |
| 6611039 | Anthony | Aug 2003 | B2 |
| 6617234 | Wang et al. | Sep 2003 | B2 |
| 6753210 | Jeng et al. | Jun 2004 | B2 |
| 6756655 | Le et al. | Jun 2004 | B2 |
| 6831349 | Chuang | Dec 2004 | B2 |
| 6900533 | Burton | May 2005 | B2 |
| 7018935 | Park | Mar 2006 | B2 |
| 7205588 | Jeng et al. | Apr 2007 | B2 |
| 7339486 | Huang | Mar 2008 | B2 |
| 7528066 | Yang et al. | May 2009 | B2 |
| 7649240 | Kim et al. | Jan 2010 | B2 |
| 7679871 | Okada et al. | Mar 2010 | B2 |
| 7704805 | Cheng et al. | Apr 2010 | B1 |
| 7732314 | Danek et al. | Jun 2010 | B1 |
| 8633707 | Filippi et al. | Jan 2014 | B2 |
| 20020054524 | Jeffery et al. | May 2002 | A1 |
| 20020155672 | Wang et al. | Oct 2002 | A1 |
| 20030214043 | Saitoh et al. | Nov 2003 | A1 |
| 20040053487 | Jeng et al. | Mar 2004 | A1 |
| 20040119138 | Yang et al. | Jun 2004 | A1 |
| 20040198059 | Park | Oct 2004 | A1 |
| 20040219720 | Jeng et al. | Nov 2004 | A1 |
| 20040245601 | Koike | Dec 2004 | A1 |
| 20050285222 | Thei et al. | Dec 2005 | A1 |
| 20070063310 | Jeng | Mar 2007 | A1 |
| 20070170544 | Koike | Jul 2007 | A1 |
| 20070193983 | Wiley | Aug 2007 | A1 |
| 20070217109 | Huang | Sep 2007 | A1 |
| 20080023788 | Chung | Jan 2008 | A1 |
| 20080217735 | Chen et al. | Sep 2008 | A1 |
| 20080289695 | Holzer et al. | Nov 2008 | A1 |
| 20100090751 | Cheng et al. | Apr 2010 | A1 |
| 20120126363 | Wang et al. | May 2012 | A1 |
| Number | Date | Country |
|---|---|---|
| 103460380 | Dec 2013 | CN |
| 201013885 | Apr 2010 | TW |
| Entry |
|---|
| Office Action for Counterpart CN Application No. 201280016328.1, Mailing date Aug. 13, 2015, pp. 1-10. |
| PCT Application No. PCT/US2012/028847 International Filing Date: Mar. 13, 2012 Applicant: International Business Machines Corporation International Search Report and Written Opinion. |
| Bonilla et al., U.S. Appl. No. 14/040,945, filed Sep. 30, 2013, entitled “Stacked Via Structure for Metal Fuse Applications”. |
| Rizzolo et al., “IBM System z9 eFUSE applications and methodology”, IBM J. Res. & Dev. vol. 51, No. 1/2 Jan./Mar. 2007, pp. 65-75. |
| Takaoka et al., “A Novel Via-fuse Technology Featuring Highly Stable Blow Operation with Large On-off Ratio for 32nm Node and Beyond”, Authorized licensed use limited to: KnowledgeGate from IBM Market Insights. Downloaded on Jul. 14, 2010 at 16:10:38 UTC from IEEE Xplore. Restrictions apply, 2007 IEEE, pp. 43-46. |
| Number | Date | Country | |
|---|---|---|---|
| 20140167772 A1 | Jun 2014 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 14040945 | Sep 2013 | US |
| Child | 14188728 | US | |
| Parent | 13074407 | Mar 2011 | US |
| Child | 14040945 | US |
