Claims
- 1. A method of manufacturing a static induction transistor having:
- a source region formed by a first type of diffusion layer which is disposed in a surface region of a first type of high-resistance semiconductor,
- a gate region which surrounds said source region from at least two directions, wherein said gate region is formed by a second type of diffusion layer which is disposed in a surface region of said first type of high-resistance semiconductor, and wherein said gate region is diffused to a depth deeper than a depth diffused in said source region, and
- at least one of a first type and a second type of impurity layer disposed immediately beneath said source region for controlling a pinch-off voltage of said transistor, said method of manufacturing a static induction transistor, comprising the steps of:
- forming, after forming said gate diffusion region, a resist pattern by exposing parts of said gate region and a place where said source region will be formed; and
- forming said at least one of said first type and second type of impurity layer immediately beneath said source region by using said resist pattern as a mask, and implanting ions of at least one of an n-type impurity and a p-type impurity.
- 2. A method of manufacturing a static induction transistor having:
- a source region formed by a first type of diffusion layer which is formed in a surface region of a first type of high-resistance semiconductor,
- a gate region which surrounds said source region from at least two directions, wherein said gate region is formed by a second type of diffusion layer which is disposed in a surface region of said first type of high-resistance semiconductor, and wherein said gate region is diffused to a depth deeper than a depth diffused in said source region, and
- at least one of a first type and a second type of impurity layer disposed immediately beneath said source region for controlling a pinch-off voltage of said transistor, said method of manufacturing a static induction transistor, comprising the steps of:
- forming, after forming said gate diffusion region, a resist pattern for providing an aperture for said source region; and
- forming said at least one of said first type and second type of impurity layer immediately beneath said source region by using said resist pattern as a mask, and implanting ions of at least one of an n-type impurity and a p-type impurity.
- 3. A method of manufacturing a static induction transistor having:
- a first type of high-resistance semiconductor forming a channel region;
- a source region formed by a first type of diffusion layer which is disposed in a surface region of said semiconductor;
- a gate region which surrounds said source region from at least two directions, which is formed by a second type of diffusion layer which is diffused into said surface region of said first type of high resistance semiconductor at a depth deeper than the depth diffused in said source region; and
- a second type of impurity layer formed in said surface region of said first type of high-resistance semiconductor outside of said gate region for the purpose of capturing a photoelectric charge without any loss;
- said method of manufacturing a static induction transistor comprising:
- a step of providing resist in places wherein said gate and source regions will be formed and implanting ions of a said second type of impurity; and
- a step of selective oxidization for the purpose of forming said second type of impurity layer beneath a thick oxidized film.
- 4. A method of manufacturing a static induction transistor having:
- a first type of high-resistance semiconductor forming a channel region;
- a source region formed by a first type of diffusion layer which is disposed in a surface region of said first type of high-resistance semiconductor;
- a gate region which surrouds said source region from at least two directions, which is formed by a second type of diffusion layer which is diffused into said surface region of said first type of high-resistance semiconductor at a depth deeper than the depth diffused in said source region; and
- a second type of impurity layer formed in said surface region of said first type of high-resistance semiconductor outside of said gate region for the purpose of capturing a photoelectric charge without any loss, said method of manufacturing a static induction transistor being characterized in that:
- after a thick oxidized film is formed on an isolating region by selective oxidization and said gate region is formed, resist is provided over parts of said gate region and a place where said source will be formed, and a second type of impurity layer is formed by implanting ions of a second type of impurity.
- 5. A method of manufacturing a static induction transistor having a first type of high-resistance semiconductor which forms a channel region, a source region formed by a first type of diffusion layer which is disposed in a surface region of said first type of high-resistance semiconductor, a gate region which surrounds said source region from at least two directions, and which is formed by a second type of diffusion layer which is diffused in said surface region of said first type of high resistance semiconductor at a depth deeper than the depth diffused in said source region, and a first type of impurity layer formed in said surface region of said first type of high-resistance semiconductor outside of said gate region for the purpose of restricting dark output,
- said method of manufacturing said static induction transistor being characterized in that resists are provided on a place where said gate region and said source region will be formed, a first type of impurity is ion-implanted, and selective oxidization is conducted for the purpose of forming said first type of impurity layer beneath a thick oxidized film.
- 6. A method of manufacturing a static induction transistor having a first type of high-resistance semiconductor forming a channel region, a source region formed by a first type of diffusion layer disposed in a surface region of said first type of high-resistance semiconductor, a gate region which surrounds said source region from at least two directions, which is formed by a second type of diffusion layer which is disposed in said surface region of said first type of high-resistance semiconductor, and which is diffused at a depth deeper than the depth diffused in said source region, and a first type of impurity layer formed in said surface region of said first type of high-resistance semiconductor outside of said gate region for the purpose of restricting dark outputs,
- said method of manufacturing a static induction transistor being characterized in that after a thick oxidized film has been formed on an isolating region by selective oxidization and a gate region has been formed, a resit is provided covering a place where said source region will be formed and parts of said gate region so that said first type of impurity layer is formed by implainting ions of said first type of impurity.
- 7. A method of manufacturing a static induction transistor having a first type of high-resistance semiconductor forming a channel region, a source region formed by a first type of diffusion layer which is disposed in a surface region of said first type of high-resistance semiconductor, a gate region which surrounds said source region from at least two directions, which is formed by a second type of diffusion layer which is disposed in said surface region of said first type of high-resistance semiconductor, and which is diffused at a depth deeper than the depth diffused in said source region, a first type of impurity layer formed in said surface region of said first type of high-resistance semiconductor outside of said gate region, and a second type of impurity layer formed beneath said first type of impurity layer; said method of manufacturing a static induction transistor being characterized in that resist is formed on parts of said gate region and a place where said source will be formed, and implanting ions of said second type of impuriy and said first type of impurity are conducted so that said first type of impurity layer and said second type of impurity layer are formed by annealing.
- 8. A method of manufacturing a static induction transistor having a first type of high-resistance semiconductor, a source region formed by a first type of diffusion layer which is formed in a surface region of said first type of high-resistance semicondcutor, a gate region which surrounds said source region from at least two directions, and which is formed by a second type of diffusion layer which is diffused in said surface region of said first type of high-resistance semiconductor at a depth deeper than the depth diffused in said source region, a first or a second type of impurity layer formed in said surface region of said first type of high-resistance semiconductor between said source region and said gate region at the same depth as or shallower than said source region for the purpose of restricting dark output;
- said method of manufacturing a static induction transistor being characterized in that a resist is provided for the inside of said gate region other than said surface of said first type of high-resistance semiconductor, and said first or second type of impurity layer is formed by implanting ions.
Priority Claims (1)
| Number |
Date |
Country |
Kind |
| 62-103134 |
Apr 1987 |
JPX |
|
BACKGROUND OF THE INVENTION
This is a division of application Ser. No. 177,278 filed April 4, 1988.
This invention relates to a high S-N Ratio static induction transistor and a method of manufacturing the same, the static induction transistor being able to optionally control the pinch-off voltage thereof and capture photoelectric charge without involving any loss.
A static induction transistor (abbreviated as "SIT" hereinafter) works on a principle which is different from that of the conventional bipolar transistor, junction FET, and MOSFET. That is, SITs are provided with a potential barrier in a depleted channel region thereof between the source and drain which are disposed in a semiconductor, the potential barrier being able to be controlled by a gate voltage and a drain voltage. The height of the potential barrier is varied by the gate voltage or the drain voltage so that a current passing between the source and the drain is controlled.
In the SIT, the charge from the source is injected into the channel region after it has cleared the potential barrier, and it reaches the drain while being accelerated in the depleted electric field. Therefore, the charge runs through the channel at the saturation speed of the charge (in a case of an electron, it is 8.times.10.sup.6 cm/s). Since a high-resistance semiconductor substrate is used for the purpose of depleting the inside of the channel, in addition to a fact that the SIT has a small junction capacitance, SITs are, in principle, suitable for use in high-speed operations. Furthermore, SITs are characterized in free from charge diffusion, and in having a low noise level because of the high running speed of its charge.
By using a pin diode as a photoreceiving element, a photodiode exhibiting high photoelectric charge yield can be obtained, utilizing the pin diode's characteristics of a large volume of the depleted layer being widened through the high-resistance semiconductor substrate. Because an SIT is an element that uses a high resistance substrate, a so-called photosensor of an internal amplifying type, in which both photoelectric conversion capability and amplifying capability can be achieved in one element, can be obtained by combining the pin diode built into the SIT and the amplifying capability of the SIT.
SIT photosensors can be applied to any application, whether single, line or area applications. They also display the original characteristics of SITs such as high speed and low noise. Furthermore, since one SIT can constitute a unit cell of a photosensor, such photosensors are suitable for use in a miniaturized manner. Furthermore, because of the low noise level of SIT photosensors, a high S-N ratio can be expected, and high sensitivity can be obtained due to the photoelectric conversion achieved by the use of a pin diode. Furthermore, since a photoelectric charge storage region and channel region are separated from each other by a pn junction, the photoelectric charge can be maintained even if the output is read out, whereby non-destructive readout can be conducted. As a result of this, it is anticipated that SIT photosensors will be utilized for photoelectric analog memories.
An operation of SITs in a case of using it as a photosensor will now be described.
FIG. 1 is a cross-sectional view of an SIT photosensor in the form of a single cell.
A high-resistance epitaxial layer 2 is grown on an n.sup.+ substrate 1 acting as the drain of the SIT so that a shallow n.sup.+ source 3 is formed. The shallow n.sup.+ source 3 is surrounded by a p.sup.+ gate region 4. A gate electrode 5 made of polysilicone, a high fusing point metal, silicide or the like is disposed above the p.sup.+ gate region 4, a thin oxidized film 6 being disposed therebetween, whereby a MOS capacitance 7 is formed. In order to electrically isolate the cells, an element-isolating region 8 is formed by means of an n.sup.+ diffused layer or a trench isolation method. Reference numeral 13 represents a thermal oxidized film, and reference numerals 14 and 15 represent SiO.sub.2 films formed by way of a CVD.
Photoelectric conversion is carried out by the pin diode constituted by a p.sup.+ gate region 4, n.sup.- epitaxial layer 2, and an n.sup.+ substrate 1. The n.sup.+ substrate 1 generally has a positive voltage applied thereto so that the pin diode is reversely biased. As a result of this, a depletion layer 9 extending from the p.sup.+ gate region 4 is grown until it substantially reaches the overall width of the epitaxial layer 2, and it is then further widened in the lateral direction. When the photosensor is storing charge, a negative voltage is applied to the p.sup.+ gate region 4 through the MOS capacitance 7. An electron 10 of the electron hole pairs generated in the depletion layer 9 due to incidental light is escaped into the drain 1 or the source 3, and a hole 11 is stored in the p.sup.+ gate region 4 so that the gate potential is raised. When the gate potential is thus raised, the potential barrier formed in a channel 12 formed by the depleted epitaxial layer 2 which is formed between the source 3 and the drain 1 is lowered, whereby the electrons 10 begin moving from the source 3 toward the drain 1.
The source 3 is grounded before the storage time period, and the potential of the p.sup.+ gate region 4 is forwardly biased with respect to the source 3 through the MOS capacitance 7, as a result of which the photoelectric charge stored in the p.sup.+ gate region 4 is delivered to the source 3 (reset state).
A sequential operation consisting of a reset, storage and readout is illustrated by the time chart shown in FIG. 2A. FIG. 2B shows the structure of a circuit in which an operation of a single cell is illustrated. Reference numeral 17 represents an SIT forming a cell, reference numeral 18 represents a switching transistor, and symbol C.sub.G represents a gate oxidized film capacitance. Symbol .phi..sub.G represents a pulse signal applied to the gate electrode of the SIT 17, and symbol .phi..sub.s represents a pulse signal applied to the switching transistor 18. When it is in a reset mode, potential V.sub.G in the p.sup.+ gate region 4 becomes built-in potential .phi..sub.B, and is initialized as ##EQU1## at a timing T, where symbol C.sub.J represents gate junction capacitance. Symbol V.sub.RS represents a drive pulse applied to the SIT gate electrode in a reset mode. Symbol V.sub.RD represents a drive pulse applied to the SIT gate electrode when it is in a readout mode. Symbol V.sub.G represents the level corresponding to the rise of gate potential brought about by the photo-generated hole.
During the storage period, the source 3 is put in a floating state.
When the gate potential is raised due to the incidence of light, and the potential barrier is lowered, causing electrons to be moved from the source 3 to the drain 1, the source potential is raised. As a result of this, the height of the potential barrier is again raised with respect to the potential of the source 3, and the flow of electrons is stopped. Therefore, the source potential is changed in accordance with the gate potential. The source potential can be read out any number of times without damaging the photo-generated hole stored in the gate region 4 (non-destructive readout). When it is in the readout mode, the difference between the source potential V.sub.s and the gate potential V.sub.G becomes, as shown in FIG. 3, the pinch-off voltage V.sub.p of the static characteristics of an SIT (V.sub.s =V.sub.G -V.sub.p). The pinch-off voltage V.sub.p is defined as a voltage V.sub.GS between the gate and the source at which the source current I.sub.s begins flowing with the voltage V.sub.DS between the drain and the source remaining constant.
The pinch-off voltage V.sub.p serves an important role in setting the drive pulses V.sub.RD and V.sub.RS of the SIT photosensor. In the case of a linear sensor or an area sensor, the dispersion of the pinch-off voltage V.sub.p as it is corresponds to the dispersion of the output from the above sensors. The parameters for determining the pinch-off voltage V.sub.p are such as the density of the epitaxial layer, the depth X.sub.j of diffusion of the p.sup.+ gate region, the width Wg of the gate, and the depth of the source.
FIG. 4 is a vertical cross-sectional view illustrating the state after the diffusion of the gate region when the SIT is prepared. Symbol Wg represents the dimension of resist 22 provided on a thin thermally-oxidized film 21. The substantial width 2a (2a=Wg-2.times.0.8.times.x.sub.j) which acts to determine the pinch-off voltage V.sub.p is provided by masking the resist 22, implanting ions of boron into the region 23 which is to be a p.sup.+ -gate region, and obtaining a predetermined gate diffused depth x.sub.j after ion diffusion.
In FIG. 3, an SIT having V.sub.p >0 is called a normally-off type, while one having V.sub.p <0 is called a normally-on type. Symbol .PHI..sub.B represents a build-in voltage between the gate and the source. The reason that the source current I.sub.s rapidly increases when V.sub.GS >.PHI..sub.B is because the p.sup.+ gate region 4 and the source 3 are forwardly biased. Assuming that the depth x.sub.j of diffusion in the p.sup.+ gate region is constant, the narrower the width Wg of the gate, the closer the pinch-off voltage V.sub.p moves to .PHI..sub.B. That is, by changing the width Wg of the gate, the normally-on SIT or the normally-off SIT is gradually changed to a bipolar transistor. If the width Wg of the gate is decreased, the substantial distance between the p.sup.+ -gate region 4 and the source 3 also decreases. Therefore, the voltage resistance BV.sub.GS between the gate and the source is lowered. As a result of this, the pinch-off voltage V.sub.p and the voltage resistance BV.sub.GS between the gate and the source are, as shown in FIG. 5, changed with respect to the width Wg of the gate. Therefore, a limitation is involved in that the pinch-off voltage V.sub.p and the voltage resistance BV.sub.GS between the gate and the source cannot be changed individually. Furthermore, a problem arises in that the manufacturing process must be changed in a major way, such as changes in the mask dimension or the depth x.sub.j of diffusion in the p.sup.+ -gate if any means for changing the pinch-off voltage V.sub.p of the SIT is employed.
Next, the other problems concerning SIT photosensors will be described. SIT photosensors have a characteristic of good sensitivity for short waves. This characteistic is due to the fact that by widely forming a high-resistance epitaxial region through the cell which is formed by an SIT, holes generated in a depleted layer which extends laterally over the p.sup.+ gate region and those generated in the diffusion length of the holes can be effectively captured as a photoelectric charge signal. This state will now be described with reference to a plan pattern of a single cell of the SIT photosensor shown in FIG. 6. In this figure, reference numeral 31 represents an epitaxial region, and reference numeral 32 represents an isolating region. Reference numeral 33 represents a p.sup.+ gate region, and reference numeral 34 represents the end portion of the p.sup.+ gate region 33. Reference numeral 35 represents a source region, and reference numeral 36 represents a gate electrode for biasing the p.sup.+ gate region 33. Reference numeral 37 represents a source electrode, and reference numeral 38 represents a depletion layer extending from the p.sup.+ gate region 33 to the epitaxial region 31. The holes generated in this depletion layer 38 are instantaneously captured by the electric field of the depletion layer into the p.sup.+ gate region 33. However, a problem arises in that the holes generated in the epitaxial region 31 of the outerside of the depletion layer 38 partially vanish during movement from the place at which the holes are generated to the end of the depletion layer 38 because these holes reach the depletion layer 38 due to diffusion. Another problem arises in that a residual image is generated because there is a charge left over after readout due to the movement caused by the diffusion.
Furthermore, even though an SIT photosensor can have a wide depletion layer 38 formed therein because the high resistance epitaxial region 31 thereof acts to receive light, a large problem arises from the dark current that is generated in the depletion layer 38. With regard to the charge that is generated in a depletion layer, a rather large charge is generally generated in a depletion layer which extends along a surface, as compared with that generated in a depeletion layer which extends through a bulk. In the structure shown in FIG. 1 wherein a high resistance region covers the surface of the epitaxial region, since the extension of the depletion layer on the surface of the epitaxial region is large, a problem arises in that the amount of dark output becomes large, and the S-N ratio deteriorates in the reduced amount of light.
That is, the dark current generated in an SIT photosensor during a storage period becomes the total sum of charges generated in a depletion layer outward of the p.sup.+ gate region 4, in a depletion layer extending in the n.sup.- epitaxial layer 2 toward the drain 1, and in a depletion layer between the p.sup.+ gate region 4 and the source 3. As a result of this, this dark current is larger than that generated in the case of a simple pin diode. The thus-generated excessive dark output is assumed to be due in the main to the charge which is generated in the depletion layer between the p.sup.+ gate region 4 and the source 3. Since the distance between the p.sup.+ gate region 4 and the source 3 is relatively short, depletion can be readily realized only by a built-in voltage. Since the p.sup.+ gate region 4 and the source 3 are each high-density diffused layers (the surface density is substantially 10.sup.18 to 10.sup.20 cm.sup.-3), the width of the depletion layer between them does not substantially change even if the region between the p.sup.+ gate region 4 and the source 3 is reversely biased during the storage period. On the other hand, the widths of the depletion layer extending outwardly from the p.sup.+ gate region 4, and of that extending from the p.sup.+ gate region 4 toward the drain 1 increase as the reverse-bias voltage between the p.sup.+ gate region 4 and the drain 1 increases. As can be clearly seen from this, the strongest electric field is formed in the depletion layer between the p.sup.+ gate region 4 and the source 3 of the depletion layers formed around the p.sup.+ gate region 4 during the storage period. That is, the rate of generation of charge is highest in the above depletion layer.
FIG. 7 illustrates the change of the structure when the normally-off SIT changes to the normally-on SIT by changing the width Wg of the gate. As can be clearly seen from this figure, the width t of a depletion layer between the p.sup.+ gate region 41 and the n.sup.+ source 42 increases as the structure changes from the normally-off type to the normally-on type. In FIG. 7, reference numeral 43 represents an epitaxial layer, and reference numeral 44 represents a depletion layer.
FIG. 8 shows the result of measurement of the gate-source reverse characteristic with respect to the change of the width Wg of the gate. As the width Wg of the gate increases, the voltage resistance increases. On the other hand, leak current (gate-source current) also increases. This measurement shows that the important factor in preventing the generation of the dark output is to restrict the generation of charge in the depletion layer 44 between the p.sup.+ gate region 41 and the source 42.
As described above, the conventional SIT used as the photosensor shown in FIG. 1 has the following problems: in order to control the SIT pinch-off voltage, it is necessary to change the density of the epitaxial layer, the width of the gate, the depth of the gate, or the depth of the source. If the density of the epitaxial layer is changed, this change affects the threshold voltage V.sub.T of the p-channel MOSFET which is formed on the same substrate. Furthermore, any such change in the width of the gate, the depth of the gate, or the depth of the source affects the voltage resistance between the gate and the source. This leads to the problem that one parameter for individually changing the pinch-off voltage is not present.
Furthermore, since only the photoelectric charge which has reached the depletion layer by the way of diffusion changes into a photelectric charge signal, the photoelectric charge being generated on the outside of the depletion layer extending from the p.sup.+ gate region, a problem arises in that the photoelectric charge partially vanishes during diffusion. A still further problem arises from the fact that the photoelectric charge which does not reach the depletion layer appears as a residual image when the following readout is conducted.
Furthermore, as the pin diode acts to receive light, the region for capturing the photoelectric charge is arranged to be a wide region due to the fact that the depletion layer extends widely to the outside of the p.sup.+ gate region. However, a problem arises herein that great charges are generated in the depletion layer, especially where it extends to the surface, and this leads to deterioration of the S-N ratio.
A still further problem arises from the fact that since the region between the p.sup.+ gate and the source is depleted, and each diffusion layer of the gate and the source are disposed closely together, the electrical field in the depletion layer is strong. During storage, the region between the p.sup.+ gate and the source is reversely biased, causing the electric field to be increased. As a result of this, the charge which is generated in the depletion layer between the gate and the source increases, again causing the problem of deterioration of the S-N ratio.
An object of the present invention is therefore to overcome the above described problems experienced with a conventional SIT serving as a photosensor cell, and to provide an SIT in which the pinch-off voltage can be individually controlled without affecting the characteristics of the other SITs and MOSFETs which are respectively formed on the same substrate.
Another object of the present invention is to provide an SIT in which photoelectric charge which is generated in the epitaxial region can be captured as a photoelectric charge signal without any loss being involved, and in which generation of residual images can be prevented.
A still further object of the present invention is to provide an SIT in which the charge which is thermally generated in a depletion layer outwardly extending from the gate region and in a depletion layer between the gate and a source is lowered in order to improve the S-N ratio.
According to the present invention, in an SIT in which a first type of high-resistance semiconductor formed by an epitaxial layer has in a surface region thereof a source region formed by a first type of diffusion layer and a gate region which surrounds said source region from at least two directions and which is made of a second type of diffusion layer which is diffused at a depth deeper than that in said source region, the SIT is characterized in that a first type or a second type of impurity layer is formed immediately beneath said source region by implanting ions.
By forming an impurity layer by implainting ions of, for example, an n-type impurity in an n-channel SIT case, in the vicinity of a potential-saddle point which is formed immediately beneath the source region, the pinch-off voltage can be shifted to the normally-on type. On the other hand, by forming an impurity layer by implanting ions of a p-type impurity, the pinch-off voltage can be shifted to the normally-off type. That is, only by forming an impurity layer by implanting ions, an SIT having the optional pinch-off voltage can be easily obtained without any necessity of changing the other process-parameters. Furthermore, by increase in the dose of the p-type impurity for the purpose of moving the pinch-off voltage to the normally-off type, a bipolar transistor can be obtained, and control of the h.sub.FE of a bipolar transistor can be conducted.
According to the present invention, an SIT having in a surface region of a first type of high-resistance semiconductor which is formed by an epitaxial layer a source region formed by a first type of diffusion layer, a gate region which surrounds said source region from at least two directions and which is formed by a second type of diffusion layer which is diffused at a depth deeper than that in said source region, the SIT is characterized in that a second type of impurity layer is formed in a surface region of the first type of high-resisntance semiconductor outside of the gate region which is formed by the second type of diffusion layer.
That is, by forming on the surface of the epitaxial layer outside the gate region a low-density impurity layer of the same type as the gate region, electric field covering the surface area of the epitaxial layer can be formed, whereby photoelectric charge which is generated in the surface area can be immediately captured in the gate region without involving any loss, and generation of residual image can be prevented.
Furthermore, according to the present invention, an SIT having on the surface of a first type of high-resistance semiconductor which is formed by an epitaxial layer a source region formed by a first type of diffusion layer and a gate region which surrounds the source region from at least two direction and which is formed by a second type of diffusion layer which is diffused at a depth deeper than that in the source region, the SIT is characterized in that a first type of impurity layer is formed in the surface region of the first type of high-resistance semiconductor outside of the gate region which is formed by the second type of diffusion layer, or a first or second type of impurity layer is formed in the surface region of the first type of high-resistance semiconductor between the source region which is formed by the first type of diffusion layer and the gate region which is formed by the second type of diffusion layer, the first or second type of impurity layer being formed at the same depth as or shallower than the source region.
As described above, an impurity layer of the same type as that of the epitaxial layer is formed in the surface region of the epitaxial layer outside of the gate region, whereby the density at the surface of the epitaxial layer is increased. As a result of this, extension of the depletion layer extending outside the gate region can be restricted as small as possible, whereby generation of thermally excited charge in the depletion layer can be prevented, and dark current can be restricted. As a result of this, the S-N ratio can be improved.
Furthermore, by forming a p-type or an n-type impurity layer at the same depth as or shallower than the source in the surface region of the epitaxial layer between the gate and the source, extension of the depletion layer in the surface region between the gate and the source can be limited at the lowest level, whereby genertion of the thermally excited charge in the depletion layer can be restricted. As a result of this, dark current can be restricted, and the S-N ratio can be improved.
US Referenced Citations (6)
Foreign Referenced Citations (1)
| Number |
Date |
Country |
| 0219775 |
Nov 1985 |
JPX |
Divisions (1)
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Number |
Date |
Country |
| Parent |
177278 |
Apr 1988 |
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Patent Grant
4889826
