Claims
- 1. A static type semiconductor memory comprising:
- (1) a plurality of memory arrays each of which includes a plurality of memory cells, a plurality of complementary data line pairs, a first complementary data bus line pair, a first switch connected between said plurality of complementary data line pairs and said first complementary data bus line pair, and a first amplifier responding to complementary signals on said first complementary data line pairs being connected to a selected group of said plurality of memory cells;
- (2) a second complementary data bus line pair;
- (3) a second switch connected between complementary outputs of said first amplifier and said second complementary data bus line pair;
- (4) a second amplifier responding to complementary signals on said complementary data bus line pair; and
- (5) a third amplifier generating an output signal in response to complementary outputs of said second amplifier means;
- wherein an operation of said first amplifier is controlled by a first control signal;
- wherein an operation of said second amplifier is controlled by a second control signal;
- wherein an address signal for accessing a selective one from among said plurality of memory cells is supplied to said static type semiconductor memory, and
- wherein levels of said first and second control signals are set to such values that said first and second amplifiers operate in high amplification gain conditions in response to a change of level of said address signal, and thereafter levels of said first and second control signals are set to such values that said first and second amplifiers operate in a low power consumption conditions.
- 2. A static type semiconductor memory according to claim 1, further comprising:
- an equalizer minimizing a level difference of complementary inputs of at least one of said first, second and third amplifiers in response to a third control signal;
- wherein a level of said third control signal is of a value that a level difference minimizing operation of said equalizer is executed in response to the change of level of said address signal, and thereafter said level of said third control signal is of a value that said level difference minimizing operation of said equalizer means is in effective.
- 3. A static type semiconductor memory according to claim 2, wherein levels of said first and second control signals are set such that, when said first and second amplifiers operate in the low power consumption conditions, information read out through said first and second amplifiers operating in the high amplification gain conditions is held.
- 4. A static type semiconductor memory according to claim 3, wherein, after said level difference minimizing operation of said equalizers is ineffective the operating conditions of said first and second amplifiers are switched from said high amplification gain conditions to said low power consumption conditions.
Priority Claims (1)
Number |
Date |
Country |
Kind |
62-220227 |
Sep 1987 |
JPX |
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Parent Case Info
This application is a continuation of application Ser. No. 07/352,740, abandoned, filed 5/16/89 which is a continuation of Ser. No. 07/215,824 filed 7/6/88, now U.S. Pat. No. 4,891,792.
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4777625 |
Sakui et al. |
Oct 1988 |
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4780850 |
Miyamoto et al. |
Oct 1988 |
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4791616 |
Taguchi et al. |
Dec 1988 |
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Ogihara |
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Continuations (2)
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Number |
Date |
Country |
Parent |
352740 |
May 1989 |
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Parent |
215824 |
Jul 1988 |
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