This application claims the benefit of Korean Patent Application No. 10-2010-0125622 filed on Dec. 9, 2010, the entire contents of which is incorporated herein by reference for all purposes as if fully set forth herein.
1. Field of the Invention
Embodiments of the invention relate to a patterned retarder type stereoscopic image display and a method for driving the same.
2. Discussion of the Related Art
A stereoscopic image display is classified into a display using a stereoscopic technique and a display using an autostereoscopic technique. The stereoscopic technique, which uses a parallax image between left and right eyes of a user with a high stereoscopic effect, includes a glasses type method and a non-glasses type method, both of which have been put on the market. In the glasses type method, the parallax image between the left and right eyes is displayed on a direct-view display or a projector through a change in a polarization direction of the left and right parallax image or in a time-division manner, and thus a stereoscopic image is implemented using polarization glasses or shutter glasses. In the non-glasses type method, an optical axis of the parallax image between the left and right eyes is generally separated using an optical plate such as a parallax barrier and a lenticular lens, and thus the stereoscopic image is implemented.
Because the left eye polarization filter of the polarization glasses PG passes through only the left eye image, the luminance of the left eye image passing through the left eye polarization filter of the polarization glasses PG has to be uniform irrespective of the right eye image. However, as shown in
In one aspect, there is a stereoscopic image display including a display panel including data lines and gate lines crossing the data lines, a data modulation unit configured to modulate input image data so that pixel data of an nth line of the image data approaches a black gray level as pixel data of an (n−1)th line of the image data approaches a white gray level, where n is a natural number equal to or greater than 2, a data driver configured to convert the image data modulated by the data modulation unit into a data voltage and output the data voltage to the data lines, and a gate driver configured to sequentially output a gate pulse synchronized with the data voltage to the gate lines.
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention. In the drawings:
The invention will be described more fully hereinafter with reference to the accompanying drawings, in which example embodiments of the inventions are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Like reference numerals designate like elements throughout the specification. In the following description, if it is decided that the detailed description of known function or configuration related to the invention makes the subject matter of the invention unclear, the detailed description is omitted.
Names of elements used in the following description may be selected in consideration of facility of specification preparation. Thus, the names of the elements may be different from names of elements used in a real product.
As shown in
Data lines D and gate lines (or scan lines) G are formed on the TFT substrate to cross each other, and a plurality of liquid crystal cells are arranged in a plurality of cell regions defined by the data lines D and the gate lines G in a matrix form. TFTs formed at crossings between the data lines D and the gate lines G transfer a data voltage supplied through the data lines D to pixel electrodes of the liquid crystal cells in response to a gate pulse from the gate lines G. For the above-described operation, in each of the TFTs, a gate electrode is connected to the gate line G, a source electrode is connected to the data line D, and a drain electrode is connected to the pixel electrode of the liquid crystal cell and a storage capacitor. The storage capacitor holds the data voltage transferred to the pixel electrode for a predetermined time until a next data voltage is supplied. A common voltage is supplied to a common electrode opposite the pixel electrode. The display panel 10 may be implemented in any liquid crystal mode as well as the TN, VA, IPS, and FFS modes.
The color filter substrate includes black matrixes and color filters. The common electrodes are formed on the color filter substrate in a vertical electric field driving manner, such as a twisted nematic (TN) mode and a vertical alignment (VA) mode. The common electrodes are formed on the TFT substrate along with the pixel electrodes in a horizontal electric field driving manner, such as an in-plane switching (IPS) mode and a fringe field switching (FFS) mode.
An upper polarizing plate 11a is attached to the color filter substrate of the display panel 10, and a lower polarizing plate 11b is attached to the TFT array substrate of the display panel 10. As shown in
The display panel 10 displays a two-dimensional (2D) image on odd-numbered lines and even-numbered lines thereof in a 2D mode. The display panel 10 displays a left eye image (or a right eye image) on the odd-numbered lines and displays a right eye image (or a left eye image) on the even-numbered lines in a three-dimensional (3D) mode. Light of the image displayed on the display panel 10 enters a patterned retarder 30 positioned on the display panel 10 through an upper polarizing film.
First retarders 31 are formed on odd-numbered lines of the patterned retarder 30, and second retarders 32 are formed on even-numbered lines of the patterned retarder 30. The first retarders 31 retard a phase value of light from the display panel 10 by +λ/4, where λ is a wavelength of light. The second retarders 32 retard a phase value of the light from the display panel 10 by −λ/4. An optical axis r3 of the first retarder 31 is perpendicular to an optical axis r4 of the second retarder 32. The first retarders 31 may be configured so as to pass through only a first circular polarization (for example, a left circular polarization), and the second retarders 32 may be configured so as to pass through only a second circular polarization (for example, a right circular polarization).
The patterned retarder 30 may include a black stripe for widening an vertical viewing angle. Instead of the patterned retarder 30, pixels of the display panel 10 may be controlled using an active black stripe.
A left eye polarization filter of the polarization glasses 20 has the same optical axis as the first retarder 31 of the patterned retarder 30, and a right eye polarization filter of the polarization glasses 20 has the same optical axis as the second retarder 32 of the patterned retarder 30. For example, a left circular polarization filter may be selected as the left eye polarization filter of the polarization glasses 20, and a right circular polarization filter may be selected as the right eye polarization filter of the polarization glasses 20. A user has to wear the polarization glasses 20 when viewing a 3D image, and has to remove the polarization glasses 20 when viewing a 2D image.
The data driver 120 includes a plurality of source driver integrated circuits (ICs). The source driver ICs convert image data RGB received from the timing controller 130 into positive and negative gamma compensation voltages and generate positive and negative analog data voltages. The source driver ICs then supply the positive and negative analog data voltages to the data lines D of the display panel 10.
The gate driver 110 includes a plurality of gate driver ICs. Each of the gate driver ICs includes a shift register, a level shifter, an output buffer, and the like. A level shifter converts an output signal of the shift register into a swing width suitable for a TFT drive of the liquid crystal cell. The gate driver 110 sequentially supplies a gate pulse synchronized with the data voltage to the gate lines G of the display panel 10 under the control of the timing controller 130.
A hold type display element requiring a backlight unit may be selected as the display panel 10. The hold type display element may be generally implemented as a transmissive liquid crystal display panel modulating light from the backlight unit. The backlight unit includes a plurality of light sources, which are turned on based on a driving current supplied by a backlight unit driver, a light guide plate (or a diffusion plate), a plurality of optical sheets, and the like. The backlight unit may be implemented as one of an edge type backlight unit and a direct type backlight unit. The light sources of the backlight unit may be implemented as at least one of a hot cathode fluorescent lamp (HCFL), a cold cathode fluorescent lamp (CCFL), an external electrode fluorescent lamp (EEFL), and a light emitting diode (LED).
The backlight unit driver generates the driving current for turning on the light sources of the backlight unit. The backlight unit driver turns on or off the driving current supplied to the light sources under the control of the timing controller 130. The timing controller 130 outputs backlight control data, that adjusts a backlight luminance and a turn-on time of the light sources based on a global or local dimming signal DIM received from the host system 150, to the backlight unit driver in a serial peripheral interface (SPI) data format.
The timing controller 130 outputs a gate control signal for controlling the gate driver 110 to the gate driver 110 based on image data RGB′ modulated by the data modulation unit 140 and timing signals Vsync, Hsync, DE, and CLK. Further, the timing controller 130 outputs a data control signal for controlling the data driver 120 to the data driver 120 based on the modulated image data RGB′ and the timing signals Vsync, Hsync, DE, and CLK. The gate control signal includes a gate start pulse GSP, a gate shift clock GSC, a gate output enable GOE, and the like. The gate start pulse GSP controls a timing of a first gate pulse. The gate shift clock GSC shifts the gate start pulse GSP. The gate output enable signal GOE controls an output timing of the gate driver 110.
The data control signal includes a source start pulse SSP, a source sampling clock SSC, a polarity control signal POL, a source output enable SOE, and the like. The source start pulse SSP controls a data sampling start time of the data driver 120. The source sampling clock SSC controls a sampling operation of the data driver 120 based on a rising or falling edge thereof. If the image data RGB to be input to the data driver 120 is transferred based on a mini low voltage differential signaling (LVDS) interface standard, the source start pulse SSP and the source sampling clock SSC may be omitted. The polarity control signal POL inverts a polarity of the data voltage output by the data driver 120 every L horizontal periods, where L is a natural number. The source output enable signal SOE controls an output timing of the data driver 120.
The host system 150 supplies the image data RGB to the data modulation unit 140 through an interface such as an LVDS interface and a transition minimized differential signaling (TMDS) interface. Further, the host system 150 supplies the timing signals Vsync, Hsync, DE, and CLK and a mode signal MODE to the data modulation unit 140.
The data modulation unit 140 receives the image data RGB and the timing signals Vsync, Hsync, DE, and CLK from the host system 150. As pixel data of an (n−1)th line (or an (m+1)th line) of the image data RGB approaches a white gray level, where n is a natural number equal to or greater than 2 and m is a natural number, the data modulation unit 140 modulates pixel data of an nth line (or an mth line) of the image data RGB so that the pixel data of the nth line (or an mth line) approaches a black gray level, and outputs the modulated pixel data.
The timing signals Vsync, Hsync, DE, and CLK supplied by the host system 150 are converted in conformity with the timing of the image data RGB′ modulated by the data modulation unit 140. The modulated image data RGB′ and the timing signals Vsync, Hsync, DE, and CLK are input to the timing controller 130. The data modulation unit 140 is described in detail later with reference to
As shown in
The memory 141 stores the pixel data Pn−1 of the (n−1)th line of the image data RGB. The memory 141 outputs the pixel data Pn−1 of the (n−1)th line to the input address calculating unit 142 in synchronization with the pixel data Pn of the nth line input to the input address calculating unit 142. In the embodiment of the invention, the pixel data is 8-bit pixel data as an example, and the 8-bit pixel data is represented by a data value of 0-255. Further, in the embodiment of the invention, the data value ‘255’ corresponds to the white gray level and the data value ‘0’ corresponds to the black gray level.
The input address calculating unit 142 receives the pixel data Pn−1 of the (n−1)th line and the pixel data Pn of the nth line. The input address calculating unit 142 calculates an input address ADDn−1 of the (n−1)th line and an input address ADDn of the nth line, and outputs the calculated input addresses ADDn−1 and ADDn to the lookup table 143. The lookup table 143 outputs modulation parameters stored at crossings between the input addresses ADDn−1 and ADDn to the interpolation unit 144.
In the lookup table 143 shown in
As shown in
For example, when the pixel data Pn−1 of the (n−1)th line input to the input address calculating unit 142 is ‘179’ and the pixel data Pn of the nth line input to the input address calculating unit 142 is ‘83’, the input address calculating unit 142 calculates ‘176’ and ‘192’ as the two input addresses ADDn−1 of the (n−1)th line and calculates ‘80’ and ‘96’ as the two input addresses ADDn of the nth line. The lookup table 143 outputs four modulation parameters ‘71’, ‘69’, ‘87’, and ‘86’ stored at four crossings between the two input addresses ‘176’ and ‘192’ of the (n−1)th line and the two input addresses ‘80’ and ‘96’ of the nth line to the interpolation unit 144.
The interpolation unit 144 receives the modulation parameters from the lookup table 143 and receives the pixel data Pn−1 of the (n−1)th line and the pixel data Pn of the nth line from the input address calculating unit 142. The interpolation unit 144 outputs modulated pixel data Pn′ of the nth line from the pixel data Pn−1 of the (n−1)th line, the pixel data Pn of the nth line, and the modulation parameters using various known linear interpolation methods.
Also, the input addresses ADDn−1 of the (n−1)th line and the input addresses ADDn of the nth line in the lookup table 143 may include all of data values between 0 and 255.When the input addresses ADDn−1 of the (n−1)th line and the input addresses ADDn of the nth line in the lookup table 143 include all of data values between 0 and 255, the input address calculating unit 142 and the interpolation unit 144 may be omitted. In this instance, the lookup table 143 may directly receive the pixel data Pn−1 of the (n−1)th line and the pixel data Pn of the nth line as the input address and may output data stored at crossings between the input address ADDn−1 of the (n−1)th line and the input address ADDn of the nth line as the modulated pixel data Pn′ of the nth line.
Further, the data modulation unit 140 decides whether the input image data RGB is the 2D image data or the 3D image data. Only when the input image data RGB is the 3D image data, the data modulation unit 140 may be designed to modulate the image data RGB.
As shown in
The memory 141 stores the pixel data Pm of the mth line of the image data RGB. The memory 141 outputs the pixel data Pm of the mth line to the input address calculating unit 142 in synchronization with the pixel data Pm+1 of the (m+1)th line input to the input address calculating unit 142. In the embodiment of the invention, the pixel data is 8-bit pixel data as an example, and the 8-bit pixel data is represented by a data value of 0-255. Further, in the embodiment of the invention, the data value ‘255’ corresponds to the white gray level and the data value ‘0’ corresponds to the black gray level.
The input address calculating unit 142 receives the pixel data Pm of the mth line and the pixel data Pm+1 of the (m+1)th line. The input address calculating unit 142 calculates an input address ADDm of the mth line and an input address ADDm+1 of the (m+1)th line, and outputs the calculated input addresses ADDm and ADDm+1 to the lookup table 143. The lookup table 143 outputs modulation parameters stored at crossings between the input addresses ADDm and ADDm+1 to the interpolation unit 144.
In the lookup table 143 shown in
As shown in
For example, when the pixel data Pm+1 of the (m+1)th line input to the input address calculating unit 142 is ‘179’ and the pixel data Pm of the mth line input to the input address calculating unit 142 is ‘83’, the input address calculating unit 142 calculates ‘176’ and ‘192’ as the two input addresses ADDm+1 of the (m+1)th line and calculates ‘80’ and ‘96’ as the two input addresses ADDm of the mth line. The lookup table 143 outputs four modulation parameters ‘71’, ‘69’, ‘87’, and ‘86’ stored at four crossings between the two input addresses ‘176’ and ‘192’ of the (m+1)th line and the two input addresses ‘80’ and ‘96’ of the mth line to the interpolation unit 144.
The interpolation unit 144 receives the modulation parameters from the lookup table 143 and receives the pixel data Pm of the mth line and the pixel data Pm+1 of the (m+1)th line from the input address calculating unit 142. The interpolation unit 144 output modulated pixel data Pm′ of the mth line from the pixel data Pm of the mth line, the pixel data Pm+1 of the (m+1)th line, and the modulation parameters using various known linear interpolation methods.
Also, the input addresses ADDm+1 of the (m+1)th line and the input addresses ADDm of the mth line in the lookup table 143 may include all of data values between 0 and 255. When the input addresses ADDm+1 of the (m+1)th line and the input addresses ADDm of the mth line in the lookup table 143 include all of data values between 0 and 255, the input address calculating unit 142 and the interpolation unit 144 may be omitted. In this instance, the lookup table 143 may directly receive the pixel data Pm+1 of the (m+1)th line and the pixel data Pm of the mth line as the input address and may output data stored at crossings between the input address ADDm+1 of the (m+1)th line and the input address ADDm of the mth line as the modulated pixel data Pm′ of the mth line.
Further, the data modulation unit 140 decides whether the input image data RGB is the 2D image data or the 3D image data. Only when the input image data RGB is the 3D image data, the data modulation unit 140 may be designed to modulate the image data RGB.
In the patterned retarder type stereoscopic image display according to the embodiment of the invention, because the left eye polarization filter of the polarization glasses 20 passes through only the left eye image, the luminance of the left eye image passing through the left eye polarization filter of the polarization glasses 20 is almost uniform irrespective of the right eye image. However, in the related art shown in
In other words, in the related art patterned retarder type stereoscopic image display shown in
In other words, in the patterned retarder type stereoscopic image display according to the embodiment of the invention, as shown in
As shown in
The input address calculating unit 142 calculates the input address ADDn−1 of the (n−1)th line from the pixel data Pn−1 of the (n−1)th line and calculates the input address ADDn of the nth line from the pixel data Pn of the nth line input in step S102. A method for calculating the input address ADDn−1 of the (n−1)th line and the input address ADDn of the nth line was described above with reference to
The lookup table 143 receives the input address ADDn−1 of the (n−1)th line and the input address ADDn of the nth line from the input address calculating unit 142 in step S103. Further, in step S103, the lookup table 143 outputs the modulation parameters stored at crossings between the input address ADDn−1 of the (n−1)th line and the input address ADDn of the nth line to the interpolation unit 144.
The interpolation unit 144 outputs the modulated pixel data Pn′ of the nth line from the pixel data Pn−1 of the (n−1)th line and the pixel data Pn of the nth line output by the input address calculating unit 142, and the modulation parameters output by the lookup table 143 in step S104. The interpolation unit 144 may output the modulated pixel data Pn′ of the nth line using various known linear interpolation methods.
As described above, in the stereoscopic image display according to the embodiment of the invention, as the pixel data of the (n−1)th line (or the (m+1)th line) of the image data approaches the white gray level, the pixel data of the nth line (or the mth line) is modulated so that the pixel data of the nth line approaches the black gray level. Hence, the luminance of the left eye image passing through the left eye polarization filter of the polarization glasses is little affected by the luminance of the right eye image. Further, the luminance of the right eye image passing through the right eye polarization filter of the polarization glasses is little affected by the luminance of the left eye image in the same manner as the left eye image. As a result, the 3D crosstalk may be reduced, and the user may view the stereoscopic image more stereoscopically.
Although embodiments have been described with reference to a number of illustrative embodiments thereof, it should be understood that numerous other modifications and embodiments can be devised by those skilled in the art that will fall within the scope of the principles of this disclosure. More particularly, various variations and modifications are possible in the component parts and/or arrangements of the subject combination arrangement within the scope of the disclosure, the drawings and the appended claims. In addition to variations and modifications in the component parts and/or arrangements, alternative uses will also be apparent to those skilled in the art.
Number | Date | Country | Kind |
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10-2010-0125622 | Dec 2010 | KR | national |