Patent Application
20130120416
This disclosure relates to electromechanical systems.
Electromechanical systems (EMS) include devices having electrical and mechanical elements, actuators, transducers, sensors, optical components (including mirrors) and electronics. Electromechanical systems can be manufactured at a variety of scales including, but not limited to, microscales and nanoscales. For example, microelectromechanical systems (MEMS) devices can include structures having sizes ranging from about a micron to hundreds of microns or more. Nanoelectromechanical systems (NEMS) devices can include structures having sizes smaller than a micron including, for example, sizes smaller than several hundred nanometers. Electromechanical elements may be created using deposition, etching, lithography and/or other micromachining processes that etch away parts of substrates and/or deposited material layers, or that add layers to form electrical and electromechanical devices.
One type of EMS device is called an interferometric modulator (IMOD). As used herein, the term interferometric modulator or interferometric light modulator refers to a device that selectively absorbs and/or reflects light using the principles of optical interference. In some implementations, an IMOD may include a pair of conductive plates, one or both of which may be transparent and/or reflective, wholly or in part, and capable of relative motion upon application of an appropriate electrical signal. In an implementation, one plate may include a stationary layer deposited on a substrate and the other plate may include a reflective membrane separated from the stationary layer by an air gap. The position of one plate in relation to another can change the optical interference of light incident on the IMOD. IMOD devices have a wide range of applications, and are anticipated to be used in improving existing products and creating new products, especially those with display capabilities.
In an EMS device, the reflective membrane can be moved between an actuated position and a relaxed position by application of a voltage between an electrode coupled to the reflective membrane and a stationary electrode. However, charge leakage from the movable reflective membrane can impact the performance of the EMS device. For example, the refresh rate of the device can be affected by charge leakage. Accordingly, there is a need for reducing the impact of charge leakage and for improving the operational performance of EMS devices.
The systems, methods and devices of the disclosure each have several innovative aspects, no single one of which is solely responsible for the desirable attributes disclosed herein.
One innovative aspect of the subject matter described in this disclosure can be implemented in an electromechanical systems (EMS) device including a substrate, an optical stack disposed over the substrate, a movable layer and a storage capacitor. The optical stack includes a stationary electrode and at least one dielectric layer disposed over the stationary electrode. The movable layer is positioned over the optical stack to define a cavity between the movable layer and the optical stack, and the movable layer is movable through the cavity between an actuated position and a relaxed position. The storage capacitor includes a first plate, a second plate and a dielectric structure disposed between the first and second plates. The first plate includes a portion of the movable layer positioned over an optically non-active region of the device, and the dielectric structure of the storage capacitor includes a portion of the at least one dielectric layer of the optical stack.
In some implementations, the portion of the movable layer that forms the first plate of the capacitor contacts the at least one dielectric layer of the optical stack over the optically non-active region of the device.
In some implementations, the stationary electrode extends beneath the patterned portion of the support structure to define the second plate of the capacitor.
Another innovative aspect of the subject matter described in this disclosure can be implemented in a method of forming an EMS device having an actuated position and a relaxed position. The method includes forming an optical stack over a substrate, the optical stack including a stationary electrode and at least one dielectric layer disposed over the stationary electrode. The method further includes forming a movable layer over the optical stack and forming a storage capacitor including a first plate, a second plate and a dielectric structure disposed between the first and second plates. A portion of the movable layer over an optically non-active region of the device is arranged to form the first plate of the capacitor, and the at least one dielectric structure of the optical stack is arranged to form the dielectric layer of the capacitor.
In some implementations, the method further includes attaching the portion of the movable layer that forms the first plate of the capacitor to the at least one dielectric layer of the optical stack over the optically non-active region of the device.
In some implementations, the movable layer includes a reflective layer, a dielectric layer and a cap layer, the dielectric layer disposed between the reflective layer and the cap layer, and the portion of the movable layer that forms the first plate includes the reflective layer.
Another innovative aspect of the subject matter described in this disclosure can be implemented in an EMS device including a substrate, an optical stack disposed over the substrate, a movable layer and a means for storing charge including a first plate, a second plate and a dielectric structure disposed between the first and second plates. The optical stack includes a stationary electrode and at least one dielectric layer disposed over the stationary electrode. The movable layer is movable through the cavity between an actuated position and a relaxed position. The storing charge means is disposed in an optically non-active region of the device, and the storing charge means includes a portion of the movable layer and a portion of the at least one dielectric layer.
In some implementations, the charge storing means has a capacitance in the range of 10 fF to about 1,000 fF.
Details of one or more implementations of the subject matter described in this specification are set forth in the accompanying drawings and the description below. Although the examples provided in this disclosure are primarily described in terms of electromechanical systems (EMS) and microelectromechanical systems (MEMS)-based displays, the concepts provided herein may apply to other types of displays, such as liquid crystal displays, organic light-emitting diode (“OLED”) displays and field emission displays. Other features, aspects and advantages will become apparent from the description, the drawings and the claims. Note that the relative dimensions of the following figures may not be drawn to scale.
Like reference numbers and designations in the various drawings indicate like elements, which may have certain structural or characteristic differences according to certain implementations.
The following description is directed to certain implementations for the purposes of describing the innovative aspects of this disclosure. However, a person having ordinary skill in the art will readily recognize that the teachings herein can be applied in a multitude of different ways. The described implementations may be implemented in any device or system that can be configured to display an image, whether in motion (e.g., video) or stationary (e.g., still image), and whether textual, graphical or pictorial. More particularly, it is contemplated that the described implementations may be included in or associated with a variety of electronic devices such as, but not limited to: mobile telephones, multimedia Internet enabled cellular telephones, mobile television receivers, wireless devices, smartphones, Bluetooth® devices, personal data assistants (PDAs), wireless electronic mail receivers, hand-held or portable computers, netbooks, notebooks, smartbooks, tablets, printers, copiers, scanners, facsimile devices, GPS receivers/navigators, cameras, MP3 players, camcorders, game consoles, wrist watches, clocks, calculators, television monitors, flat panel displays, electronic reading devices (i.e., e-readers), computer monitors, auto displays (including odometer and speedometer displays, etc.), cockpit controls and/or displays, camera view displays (such as the display of a rear view camera in a vehicle), electronic photographs, electronic billboards or signs, projectors, architectural structures, microwaves, refrigerators, stereo systems, cassette recorders or players, DVD players, CD players, VCRs, radios, portable memory chips, washers, dryers, washer/dryers, parking meters, packaging (such as in electromechanical systems (EMS), microelectromechanical systems (MEMS) and non-MEMS applications), aesthetic structures (e.g., display of images on a piece of jewelry) and a variety of EMS devices. The teachings herein also can be used in non-display applications such as, but not limited to, electronic switching devices, radio frequency filters, sensors, accelerometers, gyroscopes, motion-sensing devices, magnetometers, inertial components for consumer electronics, parts of consumer electronics products, varactors, liquid crystal devices, electrophoretic devices, drive schemes, manufacturing processes and electronic test equipment. Thus, the teachings are not intended to be limited to the implementations depicted solely in the Figures, but instead have wide applicability as will be readily apparent to one having ordinary skill in the art. For example, the teachings herein are applicable not only to interferometric MEMS display elements, but also to other EMS display elements such as those used in active-matrix liquid crystal display (AMLCD) and active-matrix organic light-emitting diode (AMOLED) display applications.
In certain implementations, active-matrix EMS devices including an integrated storage capacitor are provided. As used herein, the term “active-matrix” can refer to an EMS device in which each pixel of the device is individually controlled using an active switch, such as a thin film transistor (TFT). The EMS device can include an optical stack disposed over a substrate and a movable reflective membrane (i.e., mechanical layer) positioned over the optical stack to define a gap. The optical stack can include a stationary electrode and one or more dielectric layers. The mechanical layer is movable within the gap in response to a voltage applied between the mechanical layer and the stationary electrode. For example, a movable electrode can be formed from a portion of the mechanical layer and/or coupled to the mechanical layer, and a voltage difference between the movable electrode and the stationary electrode can be used to generate an electrostatic force that can move the mechanical layer. To improve electrical and/or optical performance, the EMS device can include an integrated storage capacitor and an active switch formed over an optically non-active region of the device. For example, including an integrated storage capacitor can increase a capacitance associated with a pixel, thereby reducing pixel leakage, reducing drive voltage and/or improving an image refresh of the display. The storage capacitor can include a first plate, a second plate and a dielectric structure disposed between the first and second plates. In some implementations, the first plate of the storage capacitor includes a portion of the mechanical layer and the dielectric structure includes at least one dielectric layer of the optical stack, thereby helping to integrate the design of the storage capacitor by forming the storage capacitor at least in part using layers used in forming pixels of the display. In some implementations, a support post used to support the mechanical layer is patterned so that a portion of the mechanical layer contacts the dielectric structure to form the first plate of the storage capacitor. The second plate of the storage capacitor can include any suitable electrical conductor, including, for example, the stationary electrode of the optical stack or a metal layer used to form a source and/or drain of a thin-film transistor.
Particular implementations of the subject matter described in this disclosure can be implemented to realize one or more of the following potential advantages. For example, some implementations reduce the drive voltage of a display and/or reduce the impacts of pixel leakage current relative to certain other configurations of displays, such as other active-matrix displays omitting a storage capacitor. Furthermore, some implementations improve an image refresh rate of a display. Moreover, some implementations improve integration of components of a display, thereby allowing the display to be fabricated using a smaller die area. Additionally, some implementations can be used to increase a capacitance associated with pixels of a display. Furthermore, some implementations can be used to reduce fabrication complexity by using layers used in forming pixels to form a storage capacitor. Additionally, some implementations can be used to reduce the power consumption of an array and/or otherwise improve the performance of the array.
An example of a suitable EMS or MEMS device, to which the described implementations may apply, is a reflective display device. Reflective display devices can incorporate interferometric modulators (IMODs) to selectively absorb and/or reflect light incident thereon using principles of optical interference. IMODs can include an absorber, a reflector that is movable with respect to the absorber, and an optical resonant cavity defined between the absorber and the reflector. The reflector can be moved to two or more different positions, which can change the size of the optical resonant cavity and thereby affect the reflectance of the IMOD. The reflectance spectrums of IMODs can create fairly broad spectral bands which can be shifted across the visible wavelengths to generate different colors. The position of the spectral band can be adjusted by changing the thickness of the optical resonant cavity, i.e., by changing the position of the reflector.
The IMOD display device can include a row/column array of IMODs. Each IMOD can include a pair of reflective layers, i.e., a movable reflective layer and a fixed partially reflective layer, positioned at a variable and controllable distance from each other to form an air gap (also referred to as an optical gap or cavity). The movable reflective layer may be moved between at least two positions. In a first position, i.e., a relaxed position, the movable reflective layer can be positioned at a relatively large distance from the fixed partially reflective layer. In a second position, i.e., an actuated position, the movable reflective layer can be positioned more closely to the partially reflective layer. Incident light that reflects from the two layers can interfere constructively or destructively depending on the position of the movable reflective layer, producing either an overall reflective or non-reflective state for each pixel. In some implementations, the IMOD may be in a reflective state when unactuated, reflecting light within the visible spectrum, and may be in a dark state when actuated, reflecting light outside of the visible range (e.g., infrared light). In some other implementations, however, an IMOD may be in a dark state when unactuated, and in a reflective state when actuated. In some implementations, the introduction of an applied voltage can drive the pixels to change states. In some other implementations, an applied charge can drive the pixels to change states.
The depicted portion of the pixel array in
In
The optical stack 16 can include a single layer or several layers. The layer(s) can include one or more of an electrode layer, a partially reflective and partially transmissive layer and a transparent dielectric layer. In some implementations, the optical stack 16 is electrically conductive, partially transparent and partially reflective, and may be fabricated, for example, by depositing one or more of the above layers onto a transparent substrate 20. The electrode layer can be formed from a variety of materials, such as various metals, for example indium tin oxide (ITO). The partially reflective layer can be formed from a variety of materials that are partially reflective, such as various metals, e.g., chromium (Cr), semiconductors and dielectrics. The partially reflective layer can be formed of one or more layers of materials, and each of the layers can be formed of a single material or a combination of materials. In some implementations, the optical stack 16 can include a single semi-transparent thickness of metal or semiconductor which serves as both an optical absorber and conductor, while different, more conductive layers or portions (e.g., of the optical stack 16 or of other structures of the IMOD) can serve to bus signals between IMOD pixels. The optical stack 16 also can include one or more insulating or dielectric layers covering one or more conductive layers or a conductive/absorptive layer.
In some implementations, the layer(s) of the optical stack 16 can be patterned into parallel strips, and may form row electrodes in a display device as described further below. As will be understood by one having skill in the art, the term “patterned” is used herein to refer to masking as well as etching processes. In some implementations, a highly conductive and reflective material, such as aluminum (Al), may be used for the movable reflective layer 14, and these strips may form column electrodes in a display device. The movable reflective layer 14 may be formed as a series of parallel strips of a deposited metal layer or layers (orthogonal to the row electrodes of the optical stack 16) to form columns deposited on top of posts 18 and an intervening sacrificial material deposited between the posts 18. When the sacrificial material is etched away, a defined gap 19, or optical cavity, can be formed between the movable reflective layer 14 and the optical stack 16. In some implementations, the spacing between posts 18 may be on the order of 1-1,000 μm, while the gap 19 may be approximately 1-1,000 μm, while the gap 19 may be on the order of 1,000-10,000 Angstroms (Å).
In some implementations, each pixel of the IMOD, whether in the actuated or relaxed state, is essentially a capacitor formed by the fixed and moving reflective layers. When no voltage is applied, the movable reflective layer 14 remains in a mechanically relaxed state, as illustrated by the pixel 12 on the left in
The processor 21 can be configured to communicate with an array driver 22. The array driver 22 can include a row driver circuit 24 and a column driver circuit 26 that provide signals to, e.g., a display array or panel 30. The cross section of the IMOD display device illustrated in
In some implementations, a frame of an image may be created by applying data signals in the form of “segment” voltages along the set of column electrodes, in accordance with the desired change (if any) to the state of the pixels in a given row. Each row of the array can be addressed in turn, such that the frame is written one row at a time. To write the desired data to the pixels in a first row, segment voltages corresponding to the desired state of the pixels in the first row can be applied on the column electrodes, and a first row pulse in the form of a specific “common” voltage or signal can be applied to the first row electrode. The set of segment voltages can then be changed to correspond to the desired change (if any) to the state of the pixels in the second row, and a second common voltage can be applied to the second row electrode. In some implementations, the pixels in the first row are unaffected by the change in the segment voltages applied along the column electrodes, and remain in the state they were set to during the first common voltage row pulse. This process may be repeated for the entire series of rows, or alternatively, columns, in a sequential fashion to produce the image frame. The frames can be refreshed and/or updated with new image data by continually repeating this process at some desired number of frames per second.
The combination of segment and common signals applied across each pixel (that is, the potential difference across each pixel) determines the resulting state of each pixel.
As illustrated in
When a hold voltage is applied on a common line, such as a high hold voltage VCHOLD
When an addressing, or actuation, voltage is applied on a common line, such as a high addressing voltage VCADD
In some implementations, hold voltages, address voltages and segment voltages may be used which produce the same polarity potential difference across the modulators. In some other implementations, signals can be used which alternate the polarity of the potential difference of the modulators. Alternation of the polarity across the modulators (that is, alternation of the polarity of write procedures) may reduce or inhibit charge accumulation which could occur after repeated write operations of a single polarity.
During the first line time 60a, a release voltage 70 is applied on common line 1; the voltage applied on common line 2 begins at a high hold voltage 72 and moves to a release voltage 70; and a low hold voltage 76 is applied along common line 3. Thus, the modulators (common 1, segment 1), (1,2) and (1,3) along common line 1 remain in a relaxed, or unactuated, state for the duration of the first line time 60a, the modulators (2,1), (2,2) and (2,3) along common line 2 will move to a relaxed state, and the modulators (3,1), (3,2) and (3,3) along common line 3 will remain in their previous state. With reference to
During the second line time 60b, the voltage on common line 1 moves to a high hold voltage 72, and all modulators along common line 1 remain in a relaxed state regardless of the segment voltage applied because no addressing, or actuation, voltage was applied on the common line 1. The modulators along common line 2 remain in a relaxed state due to the application of the release voltage 70, and the modulators (3,1), (3,2) and (3,3) along common line 3 will relax when the voltage along common line 3 moves to a release voltage 70.
During the third line time 60c, common line 1 is addressed by applying a high address voltage 74 on common line 1. Because a low segment voltage 64 is applied along segment lines 1 and 2 during the application of this address voltage, the pixel voltage across modulators (1,1) and (1,2) is greater than the high end of the positive stability window (i.e., the voltage differential exceeded a predefined threshold) of the modulators, and the modulators (1,1) and (1,2) are actuated. Conversely, because a high segment voltage 62 is applied along segment line 3, the pixel voltage across modulator (1,3) is less than that of modulators (1,1) and (1,2), and remains within the positive stability window of the modulator; modulator (1,3) thus remains relaxed. Also during line time 60c, the voltage along common line 2 decreases to a low hold voltage 76, and the voltage along common line 3 remains at a release voltage 70, leaving the modulators along common lines 2 and 3 in a relaxed position.
During the fourth line time 60d, the voltage on common line 1 returns to a high hold voltage 72, leaving the modulators along common line 1 in their respective addressed states. The voltage on common line 2 is decreased to a low address voltage 78. Because a high segment voltage 62 is applied along segment line 2, the pixel voltage across modulator (2,2) is below the lower end of the negative stability window of the modulator, causing the modulator (2,2) to actuate. Conversely, because a low segment voltage 64 is applied along segment lines 1 and 3, the modulators (2,1) and (2,3) remain in a relaxed position. The voltage on common line 3 increases to a high hold voltage 72, leaving the modulators along common line 3 in a relaxed state.
Finally, during the fifth line time 60e, the voltage on common line 1 remains at high hold voltage 72, and the voltage on common line 2 remains at a low hold voltage 76, leaving the modulators along common lines 1 and 2 in their respective addressed states. The voltage on common line 3 increases to a high address voltage 74 to address the modulators along common line 3. As a low segment voltage 64 is applied on segment lines 2 and 3, the modulators (3,2) and (3,3) actuate, while the high segment voltage 62 applied along segment line 1 causes modulator (3,1) to remain in a relaxed position. Thus, at the end of the fifth line time 60e, the 3×3 pixel array is in the state shown in
In the timing diagram of
The details of the structure of IMODs that operate in accordance with the principles set forth above may vary widely. For example,
As illustrated in
In implementations such as those shown in
The process 80 continues at block 84 with the formation of a sacrificial layer 25 over the optical stack 16. The sacrificial layer 25 is later removed (e.g., at block 90) to form the cavity 19 and thus the sacrificial layer 25 is not shown in the resulting IMODs 12 illustrated in
The process 80 continues at block 86 with the formation of a support structure e.g., a post 18 as illustrated in
The process 80 continues at block 88 with the formation of a movable reflective layer or membrane such as the movable reflective layer 14 illustrated in
The process 80 continues at block 90 with the formation of a cavity, e.g., cavity 19 as illustrated in
In some implementations, an IMOD device including a mechanical layer and an integrated storage capacitor is provided. The IMOD device can be included in an active-matrix pixel array, and the storage capacitor can be used to improve the performance of the active-matrix pixel array. For example, the integrated storage capacitor can be used to increase a capacitance associated with the IMOD device, thereby improving an image refresh rate of the array, reducing a drive voltage of the array, reducing the power consumption of the array, and/or otherwise improving the performance of the array. The storage capacitor includes a first plate, a second plate, and a dielectric structure disposed between the first and second plates. In some implementations, the first plate of the storage capacitor is formed at least in part from a portion of a mechanical layer disposed over an optically non-active region of the IMOD device. The IMOD device can include an optical stack having a stationary electrode and one or more dielectric layers, and the dielectric structure of the storage capacitor can include at least one dielectric layer of the optical stack. The second plate of the storage capacitor can include any suitable electrical conductor, including, for example, the stationary electrode of the optical stack or a metal layer used to form a source and/or drain of a thin-film transistor.
In the example illustrated in
In this implementation, the first TFT 108a includes a source electrically coupled to the first data line 102a, a gate electrically coupled to the first scan line 104a and a drain electrically coupled to a first plate of the first storage capacitor 110a and to a first electrode of the first IMOD 112a. The second TFT 108b includes a source electrically coupled to the second data line 102b, a gate electrically coupled to the first scan line 104a and a drain electrically coupled to a first plate of the second storage capacitor 110b and to a first electrode of the second IMOD 112b. The third TFT 108c includes a source electrically coupled to the first data line 102a, a gate electrically coupled to the second scan line 104b and a drain electrically coupled to a first plate of the third storage capacitor 110c and to a first electrode of the third IMOD 112c. The fourth TFT 108d includes a source electrically coupled to the second data line 102b, a gate electrically coupled to the second scan line 104b and a drain electrically coupled to a first plate of the fourth storage capacitor 110d and to a first electrode of the fourth IMOD 112d. In the illustrated configuration, the first to fourth storage capacitors 110a, 110b, 110c and 110d each include a second plate electrically connected to a common voltage reference VCOM, which can be, for example, a ground voltage. However, other implementations are possible, such as configurations in which the second ends of the first and second capacitors 110a and 110b are electrically connected to a first common voltage reference and the second ends of the third and fourth capacitors 110c and 110d are electrically connected to a second common voltage reference. In the illustrated configuration, the first to fourth IMODs 112a, 112b, 112c and 112d each further include a second electrode electrically connected to the common voltage reference VCOM. However, other implementations are possible, such as configurations in which the second electrodes of the first and second IMODs 112a and 112b are electrically connected to a first common voltage reference and the second electrodes of the third and fourth IMODs 112c and 112d are electrically connected to a second common voltage reference, or configurations in which the second electrodes of the IMODs 112a, 112b, 112c and 112d are electrically connected to a first common voltage reference and the second plates of the capacitors 110a, 110b, 110c and 110d are electrically connected to a second common voltage reference. In some implementations, the first electrode of each of the first to fourth IMODs 112a, 112b, 112c and 112d is a movable electrode and the second electrode of each of the first to fourth IMODs 112a, 112b, 112c and 112d is a stationary electrode.
In some implementations, the storage capacitors 110a, 110b, 110c and 110d have a capacitance selected to be in the range of about 10 fF to about 1,000 fF, for example, about 60 ff. The capacitance of the storage capacitors 110a, 110b, 110c and 110d also can be selected relative to the capacitance of the IMODs 112a, 112b, 112c and 112d. For example, in some implementations, each storage capacitor has a capacitance that is about 1 times to about 3 times the capacitance of an associated IMOD. A person having ordinary skill in the art will readily understand that capacitance values can depend on many factors, such as air gap, pixel size, drive voltage requirement, power consumption, etc.
The first and second data lines 102a and 102b and the first and second scan lines 104a and 104b can be used to write image data to the IMOD array 100. For example, a signal provided on the first scan line 104a can be used to address a first row of the IMOD array 100 associated with the first and second pixels 106a and 106b. A signal provided on the second scan line 104b can be used to address a second row of the IMOD array 100 associated with the third and fourth pixels 106c and 106d. Additionally, the voltage provided to the first and second data lines 102a and 102b can be controlled so as to set the state of the IMODs in the selected row. For example, when addressing a given row, pixels in the addressed row that are to be actuated can be exposed to a voltage difference between the data line and the common voltage reference VCOM suitable for actuation, and pixels that are to be relaxed (or unactuated) can be exposed to a voltage difference between the data line and the common voltage reference VCOM suitable to cause the mechanical layer of the IMOD to be moved to a relaxed state. In some implementations, the actuation voltage is in the range of about 10 V to about 16 V, for example, about 12 V, and the relaxation voltage is in the range of about 0 V to about 8 V, for example, about 0 V or 1 V.
The inclusion of the first to fourth storage capacitors 110a, 110b, 110c and 110d can increase the amount of charge stored for a given amount of voltage across each IMOD. For example, the amount of charge stored on each of the IMODs 112a, 112b, 112c and 112d can be equal to about VIMOD*(CIMOD+CS), where VIMOD is the voltage difference between the first and second electrodes of the IMOD, CIMOD is the capacitance of the IMOD, and CS is the capacitance of the storage capacitor. Including the storage capacitors can increase pixel charge storage and can reduce the impacts of pixel leakage current. For example, charge leakage, such as leakage associated with channel leakage of a thin-film transistor (TFT), can cause the voltage of a pixel to change over time and can lead to a pixel changing state if it is not refreshed at a sufficiently fast rate or if the pixel does not have a sufficient amount of stored charge.
Accordingly, the first to fourth storage capacitors 110a, 110b, 110c and 110d can help prevent pixel leakage from changing the voltage across the electrodes of the first to fourth IMODs 112a, 112b, 112c and 112d over time, thereby improving image refresh rate and reducing drive voltage and power consumption of the pixel array 100. In some implementations, the integrated storage capacitors 110a, 110b, 110c and 110d are formed from one or more layers of the IMODs 112a, 112b, 112c and 112d. Using layers of the IMODs 112a, 112b, 112c and 112d to form the storage capacitors in all or part can help integrate the design of the pixel array 100, thereby reducing the area (or footprint) of the array. Although the pixel array 100 illustrates one configuration suitable for using the storage capacitors 110a, 110b, 110c and 110d, integrated storage capacitors can be used in any suitable pixel array, including, for example, other implementations of active or analog IMOD arrays.
In
Although
In some implementations, the first dielectric layer 116b is selected to have a thickness in the range of about 10 nm to about 70 nm, for example, about 30 nm, and the second dielectric layer 116c is selected to have a thickness in the range of about 4 nm to about 20 nm, for example, about 15 nm. However, a person having ordinary skill in the art will readily understand that the thicknesses of the first and second dielectric layers 116b and 116c can depend on many factors, including, for example, on a desired capacitance of an integrated storage capacitor and/or on manufacturing constraints. As will be described later below, the first and/or second dielectric layers 116b and 116c can be included in a dielectric structure of an integrated storage capacitor. Since the capacitance of the integrated storage capacitor can be inversely proportional to a separation between the plates of the storage capacitor, selecting the first and/or second dielectric layers 116b and 116c to be relatively thin can increase the capacitance of the integrated storage capacitor.
When forming an integrated storage capacitor, a portion of the support layer used to form the support structures 18 can be patterned over an optically non-active region of the IMOD. For example, as shown in
Reference will now be made to
The mirror layer 121 can be any suitable reflective material, including, for example, a metal, such as an aluminum alloy. In some implementations, the mirror layer 121 includes aluminum-copper (AlCu) having copper by weight in the range of about 0.3% to 1.0%, for example, about 0.5%. The thickness of the mirror layer 121 can be any suitable thickness, such as a thickness in the range of about 200-500 Å, for example, about 300 Å.
The dielectric layer 122 can be a dielectric layer of, for example, SiON, and the dielectric layer 122 can have any suitable thickness, such as a thickness in the range of about 500-8,000 Å. However, the thickness of the dielectric layer 122 can be selected depending on a variety of factors, including, for example, the desired stiffness of the dielectric layer 122, which can aid in achieving the same pixel actuation voltage for different sized air-gaps for color display applications.
As illustrated in
The sacrificial layer 25 can be removed using a variety of methods, such as by exposing the sacrificial layer 25 to an etchant. For example, an etchable sacrificial material 25 such as Mo, tungsten (W), tantalum (Ta) or polycrystalline or amorphous Si may be removed by dry chemical etching, for example, by exposing the sacrificial layer to a fluorine-based gaseous or vaporous etchant, such as vapors derived from XeF2. As skilled artisans will recognize, the sacrificial layer can be exposed for a period of time that is effective to remove the material, typically selectively relative to the structures surrounding the gap. Other selective etching methods, for example, wet etching and/or plasma etching, also can be used.
The IMOD of
The illustrated storage capacitor 140 is disposed in an optically non-active region of the IMOD. For example, in the illustrated configuration, the storage capacitor 140 has been formed over the black mask 23 in the storage capacitor aperture 120 of
The illustrated EMS device includes a storage capacitor 140, a TFT 148, and an IMOD 149. Integrating the storage capacitor 140, the TFT 148, and the IMOD 149 together can reduce the area of a pixel array, such as the pixel array 100 of
The EMS device of
As shown in
The optical stack 16 has been formed over the planarization layer 136. The illustrated optical stack 16 includes the stationary electrode 116a, the first dielectric layer 116b and the second dielectric layer 116c. As shown in
The integrated storage capacitor 140 includes a first plate 141, a second plate 142 and a dielectric structure 143. In the illustrated configuration, the first plate 141 includes a portion of the reflective layer 121, the second plate 142 includes a portion of the stationary electrode 116a, and the dielectric structure 143 includes a portion of the first and second dielectric layers 116b and 116c of the optical stack 16.
The IMOD 151 includes a first side, a second side, a third side and a fourth side, and the first to fourth capacitor segments 152a, 152b, 152c and 152d have been formed adjacent the first to fourth sides of the IMOD 151, respectively. The TFT 154 is formed adjacent the fourth capacitor segment 152d on a side of the fourth capacitor segment 152d opposite the IMOD 151. The first to fourth storage capacitors segments 152a, 152b, 152c and 152d can be electrically coupled together to form a storage capacitor. In some implementations, the total area of all of the storage capacitor segments 152a, 152b, 152c and 152d is selected to be in the range of about 8 square μm to about 100 square μm, for example, about 20 square μm. However, a person having ordinary skill in the art will readily understand that the total area of the storage capacitor segments 152a, 152b, 152c and 152d can depend on many factors, including, for example, on a desired capacitance of an integrated storage capacitor.
As shown in
In block 202, an optical stack is formed over a substrate. The optical stack includes a stationary electrode and at least one dielectric layer disposed over the stationary electrode.
The process 200 continues at a block 204, in which a mechanical layer is formed over the optical stack. In some implementations, the mechanical layer includes a reflective layer, a dielectric layer and a cap layer.
In block 206, a storage capacitor including a first plate, a second plate and a dielectric structure is formed over an optically non-active region of the EMS device. The first plate includes a portion of the mechanical layer and the dielectric structure includes a portion of the dielectric layer of the optical stack. In some implementations, the dielectric layer of the mechanical layer is patterned over the storage capacitor such that the first plate of the storage capacitor includes both a portion of the reflective layer and a portion of the cap layer of the mechanical layer. Many additional steps may be employed before, in the middle of, or after the illustrated sequence, but such steps are omitted here for clarity of the description.
The display device 40 includes a housing 41, a display 30, an antenna 43, a speaker 45, an input device 48 and a microphone 46. The housing 41 can be formed from any of a variety of manufacturing processes, including injection molding and vacuum forming. In addition, the housing 41 may be made from any of a variety of materials, including, but not limited to: plastic, metal, glass, rubber and ceramic, or a combination thereof. The housing 41 can include removable portions (not shown) that may be interchanged with other removable portions of different color, or containing different logos, pictures, or symbols.
The display 30 may be any of a variety of displays, including a bi-stable or analog display, as described herein. The display 30 also can be configured to include a flat-panel display, such as plasma, EL, OLED, STN LCD, or TFT LCD, or a non-flat-panel display, such as a CRT or other tube device. In addition, the display 30 can include an IMOD display, as described herein.
The components of the display device 40 are schematically illustrated in
The network interface 27 includes the antenna 43 and the transceiver 47 so that the display device 40 can communicate with one or more devices over a network. The network interface 27 also may have some processing capabilities to relieve, for example, data processing requirements of the processor 21. The antenna 43 can transmit and receive signals. In some implementations, the antenna 43 transmits and receives RF signals according to the IEEE 16.11 standard, including IEEE 16.11(a), (b), or (g), or the IEEE 802.11 standard, including IEEE 802.11a, b, g, n, and further implementations thereof. In some other implementations, the antenna 43 transmits and receives RF signals according to the BLUETOOTH standard. In the case of a cellular telephone, the antenna 43 is designed to receive code division multiple access (CDMA), frequency division multiple access (FDMA), time division multiple access (TDMA), Global System for Mobile communications (GSM), GSM/General Packet Radio Service (GPRS), Enhanced Data GSM Environment (EDGE), Terrestrial Trunked Radio (TETRA), Wideband-CDMA (W-CDMA), Evolution Data Optimized (EV-DO), NEV-DO, EV-DO Rev A, EV-DO Rev B, High Speed Packet Access (HSPA), High Speed Downlink Packet Access (HSDPA), High Speed Uplink Packet Access (HSUPA), Evolved High Speed Packet Access (HSPA+), Long Term Evolution (LTE), AMPS, or other known signals that are used to communicate within a wireless network, such as a system utilizing 3G or 4G technology. The transceiver 47 can pre-process the signals received from the antenna 43 so that they may be received by and further manipulated by the processor 21. The transceiver 47 also can process signals received from the processor 21 so that they may be transmitted from the display device 40 via the antenna 43.
In some implementations, the transceiver 47 can be replaced by a receiver. In addition, in some implementations, the network interface 27 can be replaced by an image source, which can store or generate image data to be sent to the processor 21. The processor 21 can control the overall operation of the display device 40. The processor 21 receives data, such as compressed image data from the network interface 27 or an image source, and processes the data into raw image data or into a format that is readily processed into raw image data. The processor 21 can send the processed data to the driver controller 29 or to the frame buffer 28 for storage. Raw data typically refers to the information that identifies the image characteristics at each location within an image. For example, such image characteristics can include color, saturation and gray-scale level.
The processor 21 can include a microcontroller, CPU, or logic unit to control operation of the display device 40. The conditioning hardware 52 may include amplifiers and filters for transmitting signals to the speaker 45, and for receiving signals from the microphone 46. The conditioning hardware 52 may be discrete components within the display device 40, or may be incorporated within the processor 21 or other components.
The driver controller 29 can take the raw image data generated by the processor 21 either directly from the processor 21 or from the frame buffer 28 and can re-format the raw image data appropriately for high speed transmission to the array driver 22. In some implementations, the driver controller 29 can re-format the raw image data into a data flow having a raster-like format, such that it has a time order suitable for scanning across the display array 30. Then the driver controller 29 sends the formatted information to the array driver 22. Although a driver controller 29, such as an LCD controller, is often associated with the system processor 21 as a stand-alone Integrated Circuit (IC), such controllers may be implemented in many ways. For example, controllers may be embedded in the processor 21 as hardware, embedded in the processor 21 as software, or fully integrated in hardware with the array driver 22.
The array driver 22 can receive the formatted information from the driver controller 29 and can re-format the video data into a parallel set of waveforms that are applied many times per second to the hundreds, and sometimes thousands (or more), of leads coming from the display's x-y matrix of pixels.
In some implementations, the driver controller 29, the array driver 22, and the display array 30 are appropriate for any of the types of displays described herein. For example, the driver controller 29 can be a conventional display controller or a bi-stable display controller (such as an IMOD controller). Additionally, the array driver 22 can be a conventional driver or a bi-stable display driver (such as an IMOD display driver). Moreover, the display array 30 can be a conventional display array or a bi-stable display array (such as a display including an array of IMODs). In some implementations, the driver controller 29 can be integrated with the array driver 22. Such an implementation can be useful in highly integrated systems, for example, mobile phones, portable-electronic devices, watches or small-area displays.
In some implementations, the input device 48 can be configured to allow, for example, a user to control the operation of the display device 40. The input device 48 can include a keypad, such as a QWERTY keyboard or a telephone keypad, a button, a switch, a rocker, a touch-sensitive screen, a touch-sensitive screen integrated with the display array 30, or a pressure- or heat-sensitive membrane. The microphone 46 can be configured as an input device for the display device 40. In some implementations, voice commands through the microphone 46 can be used for controlling operations of the display device 40.
The power supply 50 can include a variety of energy storage devices. For example, the power supply 50 can be a rechargeable battery, such as a nickel-cadmium battery or a lithium-ion battery. In implementations using a rechargeable battery, the rechargeable battery may be chargeable using power coming from, for example, a wall socket or a photovoltaic device or array. Alternatively, the rechargeable battery can be wirelessly chargeable. The power supply 50 also can be a renewable energy source, a capacitor, or a solar cell, including a plastic solar cell or solar-cell paint. The power supply 50 also can be configured to receive power from a wall outlet.
In some implementations, control programmability resides in the driver controller 29 which can be located in several places in the electronic display system. In some other implementations, control programmability resides in the array driver 22. The above-described optimization may be implemented in any number of hardware and/or software components and in various configurations.
The various illustrative logics, logical blocks, modules, circuits and algorithm steps described in connection with the implementations disclosed herein may be implemented as electronic hardware, computer software, or combinations of both. The interchangeability of hardware and software has been described generally, in terms of functionality, and illustrated in the various illustrative components, blocks, modules, circuits and steps described above. Whether such functionality is implemented in hardware or software depends upon the particular application and design constraints imposed on the overall system.
The hardware and data processing apparatus used to implement the various illustrative logics, logical blocks, modules and circuits described in connection with the aspects disclosed herein may be implemented or performed with a general purpose single- or multi-chip processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, or, any conventional processor, controller, microcontroller, or state machine. A processor also may be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration. In some implementations, particular steps and methods may be performed by circuitry that is specific to a given function.
In one or more aspects, the functions described may be implemented in hardware, digital electronic circuitry, computer software, firmware, including the structures disclosed in this specification and their structural equivalents thereof, or in any combination thereof. Implementations of the subject matter described in this specification also can be implemented as one or more computer programs, i.e., one or more modules of computer program instructions, encoded on a computer storage media for execution by, or to control the operation of, data processing apparatus.
Various modifications to the implementations described in this disclosure may be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other implementations without departing from the spirit or scope of this disclosure. Thus, the claims are not intended to be limited to the implementations shown herein, but are to be accorded the widest scope consistent with this disclosure, the principles and the novel features disclosed herein. The word “exemplary” is used exclusively herein to mean “serving as an example, instance, or illustration.” Any implementation described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other implementations. Additionally, a person having ordinary skill in the art will readily appreciate, the terms “upper” and “lower” are sometimes used for ease of describing the figures, and indicate relative positions corresponding to the orientation of the figure on a properly oriented page, and may not reflect the proper orientation of the IMOD as implemented.
Certain features that are described in this specification in the context of separate implementations also can be implemented in combination in a single implementation. Conversely, various features that are described in the context of a single implementation also can be implemented in multiple implementations separately or in any suitable subcombination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination.
Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. Further, the drawings may schematically depict one more example processes in the form of a flow diagram. However, other operations that are not depicted can be incorporated in the example processes that are schematically illustrated. For example, one or more additional operations can be performed before, after, simultaneously, or between any of the illustrated operations. In certain circumstances, multitasking and parallel processing may be advantageous. Moreover, the separation of various system components in the implementations described above should not be understood as requiring such separation in all implementations, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products. Additionally, other implementations are within the scope of the following claims. In some cases, the actions recited in the claims can be performed in a different order and still achieve desirable results.
The disclosure claims priority to U.S. Provisional Patent Application No. 61/558,657 filed Nov. 11, 2011 entitled “STORAGE CAPACITOR FOR ELECTROMECHANICAL SYSTEMS AND METHODS OF FORMING THE SAME,” which is assigned to the assignee hereof. The disclosure of the prior application is considered part of, and is incorporated by reference in, this disclosure.
| Number | Date | Country | |
|---|---|---|---|
| 61558657 | Nov 2011 | US |
