Claims
- 1. A storage electrode of a DRAM cell comprising:
- a lower electrode plate formed on an insulating layer to contact a diffusion region of a transistor provided on a substrate;
- an upper electrode plate formed over said lower electrode plate and being separated therefrom by a distance; and
- a plurality of irregularly shaped electrode bars irregularly spaced-apart from one another and having vertical sidewalls, said electrode bars being formed of a conductive material provided between said lower and upper electrode plates and being electrically connected with said upper and lower electrode plates.
- 2. A storage electrode of a DRAM cell as claimed in claim 1, wherein said upper electrode plate and said bars are formed of a material including polysilicon.
- 3. A storage electrode of a DRAM cell comprising:
- a lower electrode plate formed on a first insulating layer to contact a diffusion region of a transistor provided on a substrate;
- an upper electrode plate formed over said lower electrode plate and being separated therefrom by a distance; and
- a plurality of irregularly shaped electrode bars irregularly spaced-apart from one another and having vertical sidewalls, said electrode bars being formed of a conductive material provided between said lower and upper electrode plates by selectively etching a second insulating layer formed between said upper and lower electrode plates, and said electrode bars being electrically connected with said upper and lower electrode plates.
Priority Claims (1)
Number |
Date |
Country |
Kind |
92-19351 |
Oct 1992 |
KRX |
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Parent Case Info
This is a divisional of U.S. patent application Ser. No. 08/138,204, filed Oct. 20, 1993, now U.S. Pat. No. 5,405,799.
US Referenced Citations (1)
Number |
Name |
Date |
Kind |
5172201 |
Suizu |
Dec 1992 |
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Divisions (1)
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Number |
Date |
Country |
Parent |
138204 |
Oct 1993 |
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