STRESS INCORPORATION IN SEMICONDUCTOR DEVICES

Abstract

Examples of the present technology include processing methods to incorporate stress in a channel region of a semiconductor transistor. The methods may include depositing a stressed material on an adjacent layer, where the adjacent layer is disposed between the stressed material and semiconductor material having an incorporated dopant. The adjacent layer may be characterized by an increased stress level after the deposition of the stressed material. The method may further include heating the stressed material and the adjacent layer, and removing the stressed material from the adjacent layer. The adjacent layer retains at least a portion of the increased stress after the removal of the stressed material. Examples of the present technology also include semiconductor structures having a conductive layer with first stress, and an intermediate layer with second stress in contact with the conductive layer. The second tensile stress may be at least ten times the first tensile stress.

Description

Claims

1. A semiconductor structure comprising: a conductive layer characterized by a first tensile stress;an intermediate layer in contact with the conductive layer, wherein the intermediate layer is characterized by a second tensile stress at least ten times the first tensile stress; anda semiconductor material having an incorporated dopant, wherein the intermediate layer is disposed between the conductive layer and the semiconductor material having the incorporated dopant.

2. The semiconductor structure of claim 1, wherein the first tensile stress in the conductive layer is less than 1 MPa.

3. The semiconductor structure of claim 1, wherein the second tensile stress in the intermediate layer is greater than 1 MPa.

4. The semiconductor structure of claim 1, wherein the first tensile stress in the conductive layer is less than 0.1 MPa.

5. The semiconductor structure of claim 1, wherein the second tensile stress in the intermediate layer is greater than 50 MPa.

6. The semiconductor structure of claim 1, wherein the conductive layer comprises tungsten, cobalt, copper, or aluminum.

7. The semiconductor structure of claim 1, wherein the intermediate layer comprises silicon oxide or silicon nitride.

8. The semiconductor structure of claim 1, wherein the semiconductor material having an incorporated dopant comprises a source region, a drain region, or a channel region of a semiconductor transistor.

9. The semiconductor structure of claim 1, wherein the semiconductor structure comprises an n-channel or a p-channel MOSFET, a FinFET, a gate-all-around FET, or a nanosheet FET.

10. A semiconductor structure comprising: a substrate comprising doped source and drain regions;a conductive layer characterized by a first tensile stress; andan intermediate layer in contact with each of the conductive layer and the substrate, wherein the intermediate layer is characterized by a second tensile stress at least fifteen times the first tensile stress.

11. The semiconductor structure of claim 10, wherein the first tensile stress in the conductive layer is less than 1 MPa.

12. The semiconductor structure of claim 10, wherein the second tensile stress in the intermediate layer is greater than 1 MPa.

13. The semiconductor structure of claim 10, wherein the first tensile stress in the conductive layer is less than 0.1 MPa.

14. The semiconductor structure of claim 10, wherein the second tensile stress in the intermediate layer is greater than 50 MPa.

15. The semiconductor structure of claim 10, wherein the conductive layer comprises tungsten, cobalt, copper, or aluminum.

16. The semiconductor structure of claim 10, wherein the intermediate layer comprises silicon oxide or silicon nitride.

17. The semiconductor structure of claim 10, wherein the semiconductor structure comprises an n-channel or a p-channel MOSFET, a FinFET, a gate-all-around FET, or a nanosheet FET.