means for exerting mechanical stress on the crystal lattice of the channel region

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H01L29/7842

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HELECTRICITY H01Electric elements H01LSEMICONDUCTOR DEVICES ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier

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H01L29/7842means for exerting mechanical stress on the crystal lattice of the channel region

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Patents Grantslast 30 patents

Information Patent Grant
High electron mobility transistors (HEMTS) including a yttrium (Y)...
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Information Patent Grant
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- Issue date Dec 3, 2024
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Information Patent Grant
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- Satoshi Akutsu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Contact over active gate structures for advanced integrated circuit...
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- Intel Corporation
- Andrew W. Yeoh
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Information Patent Grant
Semiconductor structure cutting process and structures formed thereby
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- Issue date Oct 29, 2024
- Taiwan Semiconductor Manufacturing Co., Ltd
- Ryan Chia-Jen Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fully strained channel
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- Shahaji B. More
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Information Patent Grant
RF devices with nanotube particles for enhanced performance and met...
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Information Patent Grant
Gate cut and fin trim isolation for advanced integrated circuit str...
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Information Patent Grant
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Information Patent Grant
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Information Patent Grant
Heterogeneous metal line compositions for advanced integrated circu...
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Information Patent Grant
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Information Patent Grant
Semiconductor structure cutting process and structures formed thereby
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- Issue date Feb 6, 2024
- Taiwan Semiconductor Manufacturing Co., Ltd
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Fin patterning for advanced integrated circuit structure fabrication
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- Issue date Jan 23, 2024
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Wrap-around contact on FinFET
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- Taiwan Semiconductor Manufacturing Co., Ltd
- Sung-Li Wang
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Information Patent Grant
Process for manufacturing a strained semiconductor device and corre...
- Patent number 11,837,558
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- Santo Alessandro Smerzi
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Core-shell nanostructures for semiconductor devices
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Gate cut and fin trim isolation for advanced integrated circuit str...
- Patent number 11,799,015
- Issue date Oct 24, 2023
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- Tahir Ghani
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- Junya Yaita
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- Patent number 11,777,031
- Issue date Oct 3, 2023
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- Chun-Yen Peng
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Information Patent Grant
Structure and method for providing line end extensions for fin-type...
- Patent number 11,721,761
- Issue date Aug 8, 2023
- Mosaid Technologies Incorporated
- Shao-Ming Yu
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Patents Applicationslast 30 patents

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INTERFACE PROFILE CONTROL IN EPITAXIAL STRUCTURES FOR SEMICONDUCTOR...
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GATE CUT AND FIN TRIM ISOLATION FOR ADVANCED INTEGRATED CIRCUIT STR...
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RF DEVICES WITH NANOTUBE PARTICLES FOR ENHANCED PERFORMANCE AND MET...
- Publication number 20240234241
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DUAL METAL GATE STRUCTURES FOR ADVANCED INTEGRATED CIRCUIT STRUCTUR...
- Publication number 20240186403
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- Jeffrey S. LEIB
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Information Patent Application
METHOD FOR MANUFACTURING SOURCE/DRAIN EPITAXIAL LAYER OF FDSOI MOSFET
- Publication number 20240170344
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- Shanghai Huali Integrated Circuit Corporation
- Jiaqi HONG
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Semiconductor Structure Cutting Process and Structures Formed Thereby
- Publication number 20240113112
- Publication date Apr 4, 2024
- Taiwan Semiconductor Manufacturing Co., Ltd.
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SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
- Publication number 20240047567
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- INNOSCIENCE (SUZHOU) TECHNOLOGY CO., LTD.
- Ronghui HAO
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Core-Shell Nanostructures For Semiconductor Devices
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- Taiwan Semiconductor Manufacturing Co., Ltd.
- Cheng-Yi PENG
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VERTICAL FIELD EFFECT TRANSISTOR WITH STRAINED CHANNEL
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- International Business Machines Corporation
- SHOGO MOCHIZUKI
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SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD FOR THE SEMICONDUC...
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DISLOCATION ENHANCED TRANSISTOR DEVICE AND METHOD
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- Toshihiko Miyashita
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- Ashish Pal
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STRUCTURE AND METHOD FOR PROVIDING LINE END EXTENSIONS FOR FIN-TYPE...
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HIGH ELECTRON MOBILITY TRANSISTORS (HEMTS) INCLUDING A YTTRIUM (Y)...
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- Edward Beam
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ENHANCED CHANNEL STRAIN TO REDUCE CONTACT RESISTANCE IN NMOS FET DE...
- Publication number 20230187447
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- Taiwan Semiconductor Manufacturing Company, Ltd.
- Yu-Chang LIN
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CMOS FINFET DEVICE HAVING STRAINED SIGE FINS AND A STRAINED SI CLAD...
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- Daedalus Prime LLC
- Stephen M. Cea
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SEMICONDUCTOR DEVICE
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- Publication date Mar 23, 2023
- Kabushiki Kaisha Toshiba
- Satoshi AKUTSU
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BIPOLAR JUNCTION TRANSISTORS INCLUDING A STRESS LINER
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- GLOBALFOUNDRIES U.S. Inc.
- Man Gu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME
- Publication number 20220384431
- Publication date Dec 1, 2022
- Fujian Jinhua Integrated Circuit Co., Ltd.
- Yi-Wang Jhan
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SEMICONDUCTOR DEVICE INCLUDING A SUPERLATTICE PROVIDING METAL WORK...
- Publication number 20220376047
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- ATOMERA INCORPORATED
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INTERFACE PROFILE CONTROL IN EPITAXIAL STRUCTURES FOR SEMICONDUCTOR...
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- Taiwan Semiconductor Manufacturing Co., Ltd.
- Winnie Victoria Wei Ning CHEN
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Information Patent Application
ISOLATION WALL STRESSOR STRUCTURES TO IMPROVE CHANNEL STRESS AND TH...
- Publication number 20220352029
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- Intel Corporation
- Aaron D. Lilak
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Information Patent Application
Super-Flexible Transparent Semiconductor Film and Preparation Metho...
- Publication number 20220310384
- Publication date Sep 29, 2022
- Suzhou Institute of Nano-Tech and Nano-Bionics (Sinano), Chinese Academy of S...
- Yukun Zhao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE
- Publication number 20220262952
- Publication date Aug 18, 2022
- Kabushiki Kaisha Toshiba
- Masataka INO
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STRUCTURE AND METHOD FOR PROVIDING LINE END EXTENSIONS FOR FIN-TYPE...
- Publication number 20220223727
- Publication date Jul 14, 2022
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Shao-Ming Yu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD FOR THE SEMICONDUC...
- Publication number 20220181495
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- Taiwan Semiconductor Manufacturing company Ltd.
- CHUN-YEN PENG
- H01 - BASIC ELECTRIC ELEMENTS

means for exerting mechanical stress on the crystal lattice of the channel region

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

High electron mobility transistors (HEMTS) including a yttrium (Y)...

Multilayer structure and semiconductor device

Semiconductor device

Contact over active gate structures for advanced integrated circuit...

Semiconductor structure cutting process and structures formed thereby

Fully strained channel

RF devices with nanotube particles for enhanced performance and met...

Semiconductor structure and manufacturing method therefor

Semiconductor device and method of forming the same

Interface profile control in epitaxial structures for semiconductor...

Gate cut and fin trim isolation for advanced integrated circuit str...

Isolation wall stressor structures to improve channel stress and th...

Enhanced channel strain to reduce contact resistance in NMOS FET de...

Display device including stressors

RF devices with nanotube particles for enhanced performance and met...

Dual metal gate structure having portions of metal gate layers in c...

Heterogeneous metal line compositions for advanced integrated circu...

Trench contact structures for advanced integrated circuit structure...

Semiconductor structure cutting process and structures formed thereby

Fin patterning for advanced integrated circuit structure fabrication

Method for fabricating semiconductor device

Semiconductor device

Super-flexible transparent semiconductor film and preparation metho...

Wrap-around contact on FinFET

Process for manufacturing a strained semiconductor device and corre...

Core-shell nanostructures for semiconductor devices

Gate cut and fin trim isolation for advanced integrated circuit str...

Semiconductor device

Semiconductor structure and manufacturing method for the semiconduc...

Structure and method for providing line end extensions for fin-type...

Patents Applicationslast 30 patents

SEMICONDUCTOR DEVICES FOR USE IN HIGH-PRESSURE ENVIRONMENTS

FULLY STRAINED CHANNEL

MOBILITY ENHANCEMENT BY SOURCE AND DRAIN STRESS LAYER OR IMPLANTATI...

Semiconductor Structure Cutting Process and Structures Formed Thereby

INTERFACE PROFILE CONTROL IN EPITAXIAL STRUCTURES FOR SEMICONDUCTOR...

GATE CUT AND FIN TRIM ISOLATION FOR ADVANCED INTEGRATED CIRCUIT STR...

RF DEVICES WITH NANOTUBE PARTICLES FOR ENHANCED PERFORMANCE AND MET...

DUAL METAL GATE STRUCTURES FOR ADVANCED INTEGRATED CIRCUIT STRUCTUR...

METHOD FOR MANUFACTURING SOURCE/DRAIN EPITAXIAL LAYER OF FDSOI MOSFET

Semiconductor Structure Cutting Process and Structures Formed Thereby

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Core-Shell Nanostructures For Semiconductor Devices

VERTICAL FIELD EFFECT TRANSISTOR WITH STRAINED CHANNEL

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD FOR THE SEMICONDUC...

DISLOCATION ENHANCED TRANSISTOR DEVICE AND METHOD

STRESS INCORPORATION IN SEMICONDUCTOR DEVICES

STRUCTURE AND METHOD FOR PROVIDING LINE END EXTENSIONS FOR FIN-TYPE...

HIGH ELECTRON MOBILITY TRANSISTORS (HEMTS) INCLUDING A YTTRIUM (Y)...

ENHANCED CHANNEL STRAIN TO REDUCE CONTACT RESISTANCE IN NMOS FET DE...

CMOS FINFET DEVICE HAVING STRAINED SIGE FINS AND A STRAINED SI CLAD...

SEMICONDUCTOR DEVICE

BIPOLAR JUNCTION TRANSISTORS INCLUDING A STRESS LINER

SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME

SEMICONDUCTOR DEVICE INCLUDING A SUPERLATTICE PROVIDING METAL WORK...

INTERFACE PROFILE CONTROL IN EPITAXIAL STRUCTURES FOR SEMICONDUCTOR...

ISOLATION WALL STRESSOR STRUCTURES TO IMPROVE CHANNEL STRESS AND TH...

Super-Flexible Transparent Semiconductor Film and Preparation Metho...

SEMICONDUCTOR DEVICE

STRUCTURE AND METHOD FOR PROVIDING LINE END EXTENSIONS FOR FIN-TYPE...

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD FOR THE SEMICONDUC...