Claims
- 1. A synchronous digital apparatus employing internal clock multiplication that stretches setup and hold times for input signals, comprising:(a) a prelatch having a data input coupled to an external data input, a clock input coupled to an external clock input, and an output; (b) an internal clock generator having an input coupled to the external clock input and having an output where the internal clock generator produces an output signal which has a frequency greater than the external clock; and (c) a latch having a data input coupled to the output from the prelatch, a clock input coupled to the internal clock generator, and an output.
- 2. The synchronous digital apparatus as recited in claim 1 further comprising a first input buffer interposed between the external data input and the prelatch data input, and a second input buffer interposed between the external clock input and the internal clock generator input.
- 3. The synchronous digital apparatus as recited in claim 1 further comprising combinational logic interposed between the output of the prelatch and the data input of the latch.
- 4. The synchronous digital apparatus as recited in claim 1 wherein the external clock input is gated with a data direction signal to prohibit the prelatch from latching data when the external data input is outbound from the latch output.
- 5. A system for stretching setup and hold times for input signals in a synchronous apparatus employing internal clock multiplication, comprising:(a) prelatch means, coupled to receive external data and an external clock, for prelatching the external data synchronous with the external clock; (b) internal clock generator means, coupled to receive the external clock, for generating an internal clock having a frequency greater than the external clock; and (c) latch means, coupled to the prelatch means and to the internal clock generator means, for latching signals output from-the prelatch means synchronous with the internal clock.
- 6. The system as recited in claim 5 further comprising a first input buffer means interposed between the external data input means and the prelatch data input means, and a second input buffer means interposed between the external clock input means and the internal clock generator input means for buffering the external data and the external clock.
- 7. The system as recited in claim 5 further comprising combinational logic means, interposed between the prelatch means and the latch means, for combining predetermined signals with signals output from the prelatch means.
- 8. The system as recited in claim 5 further comprising data direction gate means, coupled to the external clock, for prohibiting the prelatch means from latching data when data is outbound from the latch means.
- 9. A method of stretching setup and hold times for input signals in a synchronous digital apparatus employing internal clock multiplication, comprising the steps of:(a) prelatching an external data input synchronous with an external clock to create a prelatch output; (b) responsive to the external clock, generating an internal clock having a frequency greater than the external clock; and (c) latching the prelatch output synchronous with the internal clock.
- 10. The method as recited in claim 9 further comprising the step of buffering the external data input and the external clock.
- 11. The method as recited in claim 9 further comprising the step of combining predetermined signals with the prelatch output before latching in step (c).
- 12. The method as recited in claim 9 further comprising the step (d) of inhibiting step (a) responsive to data being outbound from the synchronous digital apparatus.
Parent Case Info
The present application is a file wrapper continuation of application Ser. No. 08/418,316, filed Apr. 7, 1995, now abandoned.
US Referenced Citations (14)
Continuations (1)
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Number |
Date |
Country |
Parent |
08/418316 |
Apr 1995 |
US |
Child |
09/314857 |
|
US |