VIA-Cyrix, Inc.

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Fremont, CA, US

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Patents Grantslast 30 patents

Information Patent Grant
Microprocessor and method of processing instructions for responding...
- Patent number 7,594,103
- Issue date Sep 22, 2009
- VIA-Cyrix, Inc.
- Paul J. Patchen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low-power decode circuitry and method for a processor having multip...
- Patent number 7,194,601
- Issue date Mar 20, 2007
- VIA-Cyrix, Inc.
- Charles F. Shelor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for cache power reduction
- Patent number 7,177,981
- Issue date Feb 13, 2007
- VIA-Cyrix, Inc.
- Timothy D. Davis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Tag array access reduction in a cache memory
- Patent number 7,143,243
- Issue date Nov 28, 2006
- VIA-Cyrix, Inc.
- William V. Miller
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for performing mathematical functions using po...
- Patent number RE39385
- Issue date Nov 7, 2006
- Via-Cyrix, Inc.
- Thomas B. Brightman
- 708 - Electrical computers: arithmetic processing and calculating
Information Patent Grant
Status register update logic optimization
- Patent number 7,130,988
- Issue date Oct 31, 2006
- VIA-Cyrix, Inc.
- Charles F. Shelor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for accessing registers in a processor
- Patent number 7,024,544
- Issue date Apr 4, 2006
- VIA-Cyrix, Inc.
- Charles F. Shelor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for managing a processor pipeline in response...
- Patent number 7,013,383
- Issue date Mar 14, 2006
- VIA-Cyrix, Inc.
- Charles F. Shelor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor and method for pre-fetching out-of-order instructions
- Patent number 6,983,359
- Issue date Jan 3, 2006
- VIA-Cyrix, Inc.
- William V. Miller
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hierarchical clock gating circuit and method
- Patent number 6,844,767
- Issue date Jan 18, 2005
- VIA-Cyrix, Inc.
- Charles F. Shelor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple asynchronous switching system
- Patent number 6,842,052
- Issue date Jan 11, 2005
- VIA-Cyrix, Inc.
- William V. Miller
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor architecture for virtualizing selective external bus tran...
- Patent number 6,442,635
- Issue date Aug 27, 2002
- VIA-Cyrix, Inc.
- Thomas B. Brightman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple-operand instruction in a two operand pipeline and processo...
- Patent number 6,412,063
- Issue date Jun 25, 2002
- VIA-Cyrix, Inc.
- Nicholas G. Samra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method of expediting bit scan instructions
- Patent number 6,381,622
- Issue date Apr 30, 2002
- VIA-Cyrix, Inc.
- Milton Lie
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Built-in self-test circuit and method for validating an associative...
- Patent number 6,351,789
- Issue date Feb 26, 2002
- VIA-Cyrix, Inc.
- Daniel W. Green
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Translation look-aside buffer for storing region configuration bits...
- Patent number 6,351,797
- Issue date Feb 26, 2002
- VIA-Cyrix, Inc.
- Douglas R. Beard
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Real mode translation look-aside buffer and method of operation
- Patent number 6,301,647
- Issue date Oct 9, 2001
- VIA-Cyrix, Inc.
- Daniel W. Green
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for writing back multiple results over a single-r...
- Patent number 6,275,926
- Issue date Aug 14, 2001
- VIA-Cyrix, Inc.
- Nicholas G. Samra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock multiplier using nonoverlapping clock pulses for waveform gen...
- Patent number 6,239,627
- Issue date May 29, 2001
- VIA-Cyrix, Inc.
- Andrew T. Brown
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
System and method of retiring misaligned write operands from a writ...
- Patent number 6,219,773
- Issue date Apr 17, 2001
- VIA-Cyrix, Inc.
- Raul A. Garibay
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor having selectable exception handling modes
- Patent number 6,209,083
- Issue date Mar 27, 2001
- VIA-Cyrix, Inc.
- Ajay Naini
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Debug system allowing programmable selection of alternate debug mec...
- Patent number 6,205,560
- Issue date Mar 20, 2001
- VIA-Cyrix, Inc.
- Mark W. Hervin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Stretching setup and hold times in synchronous designs
- Patent number 6,169,772
- Issue date Jan 2, 2001
- VIA-Cyrix, Inc.
- Antone L. Fourcroy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor with multiple execution pipelines using pipe stage state...
- Patent number 6,138,230
- Issue date Oct 24, 2000
- VIA-Cyrix, Inc.
- Mark W. Hervin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reloadable floating point unit
- Patent number 6,115,730
- Issue date Sep 5, 2000
- VIA-Cyrix, Inc.
- Atul Dhablania
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pipelined processor with microcontrol of register translation hardware
- Patent number 6,073,231
- Issue date Jun 6, 2000
- VIA-Cyrix, Inc.
- Mark Bluhm
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Translation look-aside buffer slice circuit and method of operation
- Patent number 6,065,091
- Issue date May 16, 2000
- VIA-Cyrix, Inc.
- Daniel W. Green
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fast RAM for use in an address translation circuit and method of op...
- Patent number 6,032,241
- Issue date Feb 29, 2000
- VIA-Cyrix, Inc.
- Daniel W. Green
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Speculative bus cycle acknowledge for 1/2X core/bus clocking
- Patent number 6,009,533
- Issue date Dec 28, 1999
- VIA-Cyrix, Inc.
- Kenneth M. Zick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
PLL using pulse width detection for frequency and phase error corre...
- Patent number 6,005,425
- Issue date Dec 21, 1999
- VIA-Cyrix Inc.
- James Cho
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
Apparatus and method for accessing registers in a processor
- Publication number 20060136699
- Publication date Jun 22, 2006
- VIA-Cyrix, Inc.
- Charles F. Shelor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and system for terminating unnecessary processing of a condi...
- Publication number 20040255103
- Publication date Dec 16, 2004
- VIA-Cyrix, Inc.
- Richard L. Duncan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Tag array access reduction in a cache memory
- Publication number 20040243764
- Publication date Dec 2, 2004
- VIA-Cyrix, Inc.
- William V. Miller
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and system for predicting the execution of conditional instr...
- Publication number 20040230781
- Publication date Nov 18, 2004
- VIA-Cyrix, Inc.
- Charles F. Shelor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and system for cache power reduction
- Publication number 20040225839
- Publication date Nov 11, 2004
- VIA-Cyrix, Inc.
- Timothy D. Davis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Status register update logic optimization
- Publication number 20040098564
- Publication date May 20, 2004
- VIA-Cyrix, Inc.
- Charles F. Shelor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multiple asynchronous switching system
- Publication number 20030227300
- Publication date Dec 11, 2003
- VIA-Cyrix, Inc.
- William V. Miller
- G06 - COMPUTING CALCULATING COUNTING

VIA-Cyrix, Inc.

Organization

Patents Grantslast 30 patents

Microprocessor and method of processing instructions for responding...

Low-power decode circuitry and method for a processor having multip...

Method and system for cache power reduction

Tag array access reduction in a cache memory

Method and apparatus for performing mathematical functions using po...

Status register update logic optimization

Apparatus and method for accessing registers in a processor

Apparatus and method for managing a processor pipeline in response...

Processor and method for pre-fetching out-of-order instructions

Hierarchical clock gating circuit and method

Multiple asynchronous switching system

Processor architecture for virtualizing selective external bus tran...

Multiple-operand instruction in a two operand pipeline and processo...

System and method of expediting bit scan instructions

Built-in self-test circuit and method for validating an associative...

Translation look-aside buffer for storing region configuration bits...

Real mode translation look-aside buffer and method of operation

System and method for writing back multiple results over a single-r...

Clock multiplier using nonoverlapping clock pulses for waveform gen...

System and method of retiring misaligned write operands from a writ...

Processor having selectable exception handling modes

Debug system allowing programmable selection of alternate debug mec...

Stretching setup and hold times in synchronous designs

Processor with multiple execution pipelines using pipe stage state...

Reloadable floating point unit

Pipelined processor with microcontrol of register translation hardware

Translation look-aside buffer slice circuit and method of operation

Fast RAM for use in an address translation circuit and method of op...

Speculative bus cycle acknowledge for 1/2X core/bus clocking

PLL using pulse width detection for frequency and phase error corre...

Patents Applicationslast 30 patents

Apparatus and method for accessing registers in a processor

Method and system for terminating unnecessary processing of a condi...

Tag array access reduction in a cache memory

Method and system for predicting the execution of conditional instr...

Method and system for cache power reduction

Status register update logic optimization

Multiple asynchronous switching system

Trademarklast 30 trademarks