Patent Grant
12015042
Embodiments described herein are generally related to an optoelectronic device, and more specifically, an image sensor that has an epitaxially grown charge layer on surfaces of pixels to enhance signal-to-noise ratio in the image sensor.
Complementary metal-oxide-semiconductor (CMOS) image sensors (CIS) are widely used in various applications such as digital cameras and mobile phones. A CIS uses an array of pixels, such as photodiodes, photogate detectors, or phototransistors, for collecting light projected towards a semiconductor substrate and converting collected photo-energy into electrical signals that can be used in a suitable application. One type of CIS, backside-illuminated (BSI) CIS, typically has a silicon substrate that includes an array of pixels formed inside for sensing and recording an intensity of light entering the substrate from the backside, and some circuitry and input/outputs adjacent the array of pixels for providing an operation environment for the pixels and for supporting external communication with the pixels. During device processing such as etching, polishing, or any other material removing process, a surface of the backside of the substrate (and thus surfaces of the pixels) is damaged and left with dangling bonds and/or defect centers. Charge carriers generated from such dangling bonds and/or defect centers contribute to the formation of noise in the electrical signals in the array of pixels.
Conventional methods for suppressing the generation of noise include passivating the surface of the backside of the substrate, by adding a charge layer (i.e., a layer including charge carriers) near the surface of the backside of the substrate. Charge carriers in the charge layer recombine with charge carriers generated from the dangling bonds and/or defect centers. A charge layer may be formed by implanting a desired type of charges (i.e., positive charges or negative charges that are opposite of the charge carriers generated from the dangling bonds and/or defect centers) into the substrate. Alternatively, a charge layer may be formed by adding a dielectric material on the surface of the backside of the substrate having the opposite type of the desired type of charges, such that the desired type of charges is induced in the substrate near the backside. A buffer oxide layer may be inserted between the surface of the backside of the substrate and the dielectric material for charge separation between the charge carriers in the dielectric layer and the induced charge carriers in the substrate near the surface.
However, recent demand for deeper pixels with high aspect ratio trench isolation (i.e., pixels separated from each other by high aspect ratio trenches) and higher signal-to-noise ratio brings challenges to the conventional methods. A charge layer formed by the conventional methods may not provide enough charge carriers to passivate the surface of the substrate with reasonable fabrication cost and design requirements. Furthermore, a charge layer formed by implantation may also not have a good coverage on sidewalls of trenches of high aspect ratio. A charge layer formed by a thick dielectric layer for better passivation of the induced charge carriers may also have a high absorption coefficient, leading to reduced signal from the array of pixels.
Therefore, there is a need in the art for an improved method for passivating a damaged surface of the backside of a BSI CIS device as well as any damaged surface from etch and/or polishing and more generally an improved structure of a BSI CIS device. The method can also be implemented on frontside-illuminated (FSI) CIS to provide similar benefits as for BSI CIS.
In one embodiment, a method of fabricating a semiconductor device includes forming an interconnect structure over a front side of a sensor substrate, thinning the sensor substrate from a back side of the sensor substrate, etching trenches into the sensor substrate, pre-cleaning an exposed surface of the sensor substrate, epitaxially growing a charge layer directly on the pre-cleaned exposed surface of the sensor substrate, and forming isolation structures within the etched trenches.
In another embodiment, a method of fabricating a semiconductor device includes epitaxially growing a epitaxially grown layer directly on a surface of a handle substrate, epitaxially growing a semiconductor layer directly on the charge layer, implanting a dopant into the semiconductor layer, etching trenches into the semiconductor layer, forming isolation structures within the etched trenches, forming an interconnect structure over the semiconductor layer, and removing the handle substrate from the epitaxially grown layer.
In yet another embodiment, an image sensor includes a sensor substrate having a front side and a back side, a plurality of pixels formed within the sensor substrate on the back side, a plurality of isolation structures formed within the sensor substrate, wherein the plurality of pixels are isolated from each other by one of the plurality of isolation structures, an interconnect structure over the front side of the sensor substrate, and a charge layer epitaxially grown directly on surfaces of the plurality of pixels on the back side of the sensor substrate.
Implementations of the present disclosure, briefly summarized above and discussed in greater detail below, can be understood by reference to the illustrative implementations of the disclosure depicted in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical implementations of this disclosure and are therefore not to be considered limiting of its scope, for the disclosure may admit to other equally effective implementations.
To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. The figures are not drawn to scale and may be simplified for clarity. It is contemplated that elements and features of one implementation may be beneficially incorporated in other implementations without further recitation.
Embodiments described herein are generally related to an optoelectronic device, and more specifically, an image sensor that has an epitaxially grown charge layer on surface of pixels to enhance signal to noise ratio in the image sensor.
Image sensors described herein include an epitaxially grown charge layer on a sensor substrate in which pixels are formed. Epitaxially grown charge layers conformally cover damaged surfaces of pixels where undesired carriers (noise) are generated from dangling bonds and/or defect centers caused by device fabrication processes. Epitaxially grown charge layers passivate the charge carriers at the surfaces of pixels, and thus are prevented from causing noise in the electrical signals converted from photo-energy in the pixels.
The image sensor device 100 includes a sensor substrate 102 having a front side 104 and a back side 106. The sensor substrate 102 may be a photodiode. In some embodiments, the sensor substrate 102 includes a pinned layer photodiode, a photogate, a reset transistors, a source follower transistor, or a transfer transistor. The sensor substrate 102 is operable to sense incident light 110 that is projected toward the back side 106 of the sensor substrate 102. The sensor substrate 102 absorbs photo-energy of the projected incident light 110 and creates electron-hole pairs near the back side 106 of the sensor substrate 102, inducing mobile charge carriers. The charge carriers are diffused and detected as an electrical signal near the front side 104 of the sensor substrate 102.
The sensor substrate 102 may be a substrate with a p-type dopant such as boron or n-type dopant such as phosphorous or arsenic doped by a suitable implantation process, such as a diffusion process. The substrate may be a bulk silicon, any other suitable semiconducting materials such as crystalline germanium, compound semiconductors such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, Ill-Nitrides or combinations thereof. Alternatively, the substrate may be a silicon-on-insulator (SOI) substrate that includes a semiconductor layer such as silicon or germanium formed on an insulator layer, formed using wafer bonding and/or other suitable methods. The insulator layer may be a buried oxide (BOX) layer formed in a semiconductor substrate. The substrate may have any suitable crystallographic orientation (e.g., a (100), (110), (111), or (001) crystallographic orientation). The thickness of the substrate may range between about 100 microns (μm) and 1000 μm.
In the sensor substrate 102, an array or grid of pixels 108 are formed. The pixels 108 may be varied from one another to have different depths, thicknesses, widths, and so forth. Although only two pixels 108 are illustrated in
The image sensor device 100 further includes a charge layer 116 epitaxially grown conformally directly on surfaces of the pixels 108 on the back side 106 of the sensor substrate 102, including inner walls of the trenches 114. The pixels 108 may include defect centers and a high concentration of dangling bonds near the surfaces of the pixels 108 on the back side 106 of the sensor substrate 102 due to device processing such as etching to form the trenches 114 and thinning of the sensor substrate 102 from the back side 106. Charge carriers generated from the defect centers and the dangling bonds that would cause the generation of noise in the electrical signals converted from photo-energy in the array of pixels 108 are passivated (i.e., recombined) with charge carriers formed in the charge layer 116. Thus, the noise in the electrical signals is reduced. The charge layer 116 may include boron-doped silicon (Si:B), boron-doped silicon germanium (SiGe:B), boron-doped germanium (Ge:B), or a combination thereof. In some embodiments, the charge layer 116 is formed of carbon-doped silicon (Si:C), which blocks metal diffusion from the front side 104 of the sensor substrate 102, in addition to providing the charge carriers. The charge layer 116 formed of silicon germanium (SiGe), germanium (Ge), or carbon-doped silicon (Si:C) on the sensor substrate 102 formed of doped silicon induces tension at the interface with the sensor substrate 102 due to a lattice mismatch, and thus the indirect bandgap of silicon is modified toward a direct bandgap, which enhances generation of electron-hole pairs and therefore the electrical signal. Thickness of the charge layer 116 may be between about 5 nm and 50 nm. Since such epitaxial charge layer can also serve as extension of pixel area, which could increase the thickness beyond 50 nm depending on integration. A density of formed charge carriers in the charge layer 116 may be between 1×1018/cm3 and 5×1021/cm3.
The image sensor device 100 may further have an interconnect structure 118 formed over the front side 104 of the sensor substrate 102. The interconnect structure 118 may include a plurality of patterned dielectric layers and conductive layers that provide interconnections (e.g., wiring) between the various doped features, circuitry, and input/output of the image sensor device 100. The interconnect structure 118 may further include an interlayer dielectric (ILD), a multilayer interconnect (MLI) structure, including, for example, contacts, vias, and metal lines. The MLI structure may include aluminum interconnects formed of aluminum/silicon/copper alloy, titanium, titanium nitride, tungsten, polysilicon, metal silicide, or combinations thereof. Alternatively, the MLI structure may include copper multilayers interconnect formed of copper alloy, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, polysilicon, metal silicide, or combinations thereof.
The image sensor device 200 includes a sensor substrate 102 having a front side 104 and a back side 106.
In the sensor substrate 102, an array or grid of pixels 108 are formed. The sensor substrate 102 may further include isolation structures 212, which provide electrical and optical isolation between the pixels 108. The isolation structures 212 may be shallow trench isolation (STI) structures that are formed of a dielectric material such as silicon oxide or silicon nitride filled in trenches 214, deep trench isolation (DTI) structures that are formed of a dielectric or polymetallic materials filled in the trenches 214, or a capacitor with airgaps in the trenches 214. The trenches 214 are formed by etching the sensor substrate 102. In some embodiments, the isolation structures 212 include doped isolation features, such as heavily doped n-type or p-type regions. Although only three isolation structures 212 are illustrated in
The image sensor device 200 includes an epitaxially grown layer 216 (referred to as an “Epi layer” hereinafter) directly on top surfaces of the pixels 108 on the back side 106 of the sensor substrate 102. The Epi layer 216 may be formed of boron-doped silicon (Si:B), boron-doped silicon germanium (SiGe:B), or boron-doped germanium (Ge:B), carbon-doped silicon (Si:C). The image sensor device 200 further includes a charge layer 218 over the Epi layer 216 and inner walls of the trenches 214. In some embodiments, the charge layer 218 includes boron-doped silicon (Si:B), boron-doped silicon germanium (SiGe:B), boron-doped germanium (Ge:B), or carbon-doped silicon (Si:C) that is epitaxially grown on the exposed surface of the sensor substrate 102 on the back side 106. In some embodiments, the charge layer 218 is formed by adding a dielectric material on the exposed surface of the sensor substrate 102 on the back side 106 having the opposite type of the desired type of charges, such that the desired type of charges is induced in the substrate near the back side 106.
In block 302 of the method 300, a sensor substrate 102 is provided or fabricated, as shown in
In block 304 of the method 300, an interconnect structure 118 is formed over the front side 104 of the sensor substrate 102, as shown in
In block 306 of the method 300, the sensor substrate 102 is flipped over and thinned from the back side 106, as shown in
In block 308 of the method 300, trenches 114 are etched into the sensor substrate 102 from the back side 106. Pixels 108 are each defined between two adjacent trenches 114 and an array or grid of pixels 108 are formed. The pixels 108 may be varied from one another to have different depths, thicknesses, widths, and so forth. Although only two pixels 108 and three trenches 114 are illustrated in
In block 310 of the method 300, an exposed surface of the sensor substrate 102 on the back side 106 is pre-cleaned to remove organic materials, native oxides such as carbon oxide and other impurities, to enhance performance of the image sensor device 100. A cleaning solution may include a mixture of H2O2—H2SO4 and/or wet oxidization, dry oxidation and an aqueous HF (hydrofluoric acid). The cleaned surface of the sensor substrate 102 may be dried by a drier to remove any residual liquids or particles. In some embodiments, the pre-cleaning process is performed at a low temperature, about 450° C. or less.
In block 312 of the method 300, a charge layer 116 is epitaxially grown on the exposed surface of the sensor substrate 102 on the back side 106, including inner walls of the trenches 114 (that is, exposed surfaces of the pixels 108), as shown in
In block 314 of the method 300, isolation structures 112 are formed as shown in
It should be noted that the particular example embodiments described above are just some possible example methods of fabricating semiconductor devices having integrated circuits according to the present disclosure and do not limit the possible configurations, specifications, or the like of liquid ejecting devices according to the present disclosure. For example, the methods can be applied to fabricate other semiconductor devices such as solar cells. Further, the order of the blocks of the method 300 can be replaced and some of the blocks of the method 300 can be repeated or omitted. The trenches 114 can be etched from the front side 104 of the sensor substrate 102.
In block 502 of the method 500, a layer 216 is epitaxially grown on a handle substrate 602, as shown in
In block 504 of the method 500, a semiconductor layer 604 is epitaxially grown over the Epi layer 216, as shown in
In block 506 of the method 500, a p-type dopant such as boron and n-type dopant such as phosphorous or arsenic is doped into the semiconductor layer 604 by a suitable implantation process 606, such as a diffusion or an epitaxial process to form a sensor substrate 102, as shown in
In block 508 of the method 500, an interconnect structure 118 is formed over the front side 104 of the sensor substrate 102 as in block 304.
In block 510 of the method 500, the sensor substrate 102 is flipped over and the handle substrate 602 is removed from the Epi layer 216, as shown in
In block 512 of the method 500, trenches 214 are etched into the sensor substrate 102 from the back side 106. Pixels 108 are each defined between two adjacent trenches 214 and an array or grid of pixels 108 are formed. The pixels 108 may be varied from one another to have different depths, thicknesses, widths, and so forth. Although only two pixels 108 and three trenches 214 are illustrated in
In block 514 of the method 500, a charge layer 218 is formed over the exposed surface of the sensor substrate 102 on the back side 106, including inner walls of the trenches 214, as shown in
In block 516 of the method 500, isolation structures 212 are formed as shown in
It should be noted that the particular example embodiments described above are just some possible example methods of fabricating semiconductor devices having integrated circuits according to the present disclosure and do not limit the possible configurations, specifications, or the like of liquid ejecting devices according to the present disclosure. For example, the methods can be applied to fabricate other semiconductor devices such as solar cells. Further, the order of the blocks of the method 500 can be replaced and some of the blocks of the method 500 can be repeated or omitted. The trenches 214 can be etched from the front side 104 of the sensor substrate 102.
In the example embodiments described above, the image sensors and the methods for fabricating the same are provided to reduce noise in the electrical signals converted from photo-energy in array of pixels. An epitaxially grown charge layer in the image sensors provide a large concentration of charge carriers to passivate excess charge carriers generated at surfaces of pixels in the image sensors. An epitaxially grown charge layer may provide additional functions such as an etch stop layer in a fabrication process or a getter that blocks metal diffusion within the image sensors and/or the stress to engineer the material bandgap/work function near sensor surfaces and/or the separation between signal and noise.
While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms. Furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.
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