Field
The field relates to structures with integrated waveguides, and in particular, to interconnects and circuit structures with integrated metallic waveguides.
Description of the Related Art
In some electronic systems, multiple integrated device dies may be mounted to a carrier and may communicate with one another in a variety of ways. For example, in some systems, two integrated device dies can communicate with one another by way of conductive traces or interconnects provided in an intervening package substrate such as a printed circuit board (PCB) or in a silicon interposer. In other systems, a silicon bridge or other interconnect structure can serve to electrically connect two dies within a package or system. However, existing die-to-die interconnects may experience high losses due to conductor loss, crosstalk or other factors. Accordingly, there remains a continuing need for improved die-to-die communications.
Various embodiments disclosed herein relate to interconnects and structures with integrated waveguides, e.g., integrated conductive or metallic waveguides. As explained above, existing techniques for providing die-to-die (or chip-to-chip) communications within a package or system may not provide adequate performance at high frequencies. For example, some die-to-die interconnects may experience high current densities which can lead to high losses due to conductor loss, crosstalk and other factors. Moreover, in some systems, it may be difficult to provide millimeter wave or sub-terahertz communications over a range of tens of gigahertz to hundreds of gigahertz (e.g., in a range of 10 GHz to 950 GHz, in a range of 20 GHz to 900 GHz) using coplanar or microstrip waveguides since such devices may be lossy at millimeter-sized wavelengths. The embodiments disclosed herein beneficially enable the use of lower loss metallic waveguides for die-to-die communications, including communications at wavelengths in a range of 0.1 mm to 10 mm.
A metallic or conductive waveguide can comprise an effectively closed metallic or conductive channel as viewed from a side cross-section taken perpendicular to a propagation direction of the waveguide, and can include a low loss dielectric material within the effectively closed channel. In various embodiments, the metallic or conductive waveguide can comprise a metal, including metallic compounds. In some embodiments, the metallic waveguide can be defined by bonding two elements (e.g., two semiconductor elements) along an interface, with the waveguide defined at least in part by the interface. In some embodiments, the two elements can be directly bonded to one another without an intervening adhesive. In other embodiments, the metallic waveguide can be at least partially (e.g., completely) embedded in an element and can include one or a plurality of ports that can receive a radiating element for coupling electromagnetic waves to the waveguide. The disclosed embodiments can therefore provide die-to-die communications with low loss and with little or no crosstalk, which can enable high frequency die-to-die communications. Moreover, in embodiments that utilize direct bonding, the resulting structure can be constructed at lower costs than other techniques, since the waveguides can be constructed using the bonding layers defined for directly bonding two elements to one another. The integrated waveguides disclosed herein can also advantageously reduce the number of radio frequency (RF) components provided in the package, since the waveguides described herein can be directly integrated into the dies and/or other elements.
In the illustrated embodiment, one or more of the device dies 2a-2c are directly bonded to the carrier 3 without an intervening adhesive. The direct bond between the dies 2a-2c and the carrier 3 can include a direct bond between corresponding conductive features of the dies 2a-2c (e.g., a processor die) and the carrier 3 (e.g., an integrated device die, an interposer, etc.) without an intervening adhesive, without being limited thereto. In some embodiments, the conductive features may be surrounded by non-conductive field regions. To accomplish the direct bonding, in some embodiments, respective bonding surfaces of the conductive features and the non-conductive field regions can be prepared for bonding. Preparation can include provision of a nonconductive layer, such as silicon oxide or silicon nitride, with exposed conductive features, such as metal bond pads or contacts. The bonding surfaces of at least the non-conductive field regions, or both the conductive and non-conductive regions, can be polished to a very high degree of smoothness (e.g., less than 20 nm surface roughness, or more particularly, less than 5 nm surface roughness). In some embodiments, the surfaces to be bonded may be terminated with a suitable species and activated prior to bonding. For example, in some embodiments, the non-conductive surfaces (e.g., field regions) of the bonding layer to be bonded, such as silicon oxide material, may be very slightly etched for activation and exposed to a nitrogen-containing solution and terminated with a nitrogen-containing species. As one example, the surfaces to be bonded (e.g., field regions) may be exposed to an ammonia dip after a very slight etch, and/or a nitrogen-containing plasma (with or without a separate etch). In a direct bond interconnect (DBI) process, nonconductive features of the dies and the carrier can directly bond to one another, even at room temperature and without the application of external pressure, while the conductive features of the dies and the carrier layer can also directly bond to one another, without any intervening adhesive layers. Bonding by DBI forms stronger bonds than Van der Waals bonding, including significant covalent bonding between the surfaces of interest. Subsequent annealing can further strengthen bonds, particularly between conductive features of the bonding interfaces.
In some embodiments, the respective conductive features can be flush with the exterior surfaces (e.g., the field regions) of the dies and the carrier. In other embodiments, the conductive features may extend above the exterior surfaces. In still other embodiments, the conductive features of one or both of the dies and the carrier are recessed relative to the exterior surfaces (e.g., nonconductive field regions) of the dies and the carrier. For example, the conductive features can be recessed relative to the field regions by less than 20 nm, e.g., less than 10 nm.
Once the respective surfaces are prepared, the nonconductive field regions (such as silicon oxide) of the dies 2a-2c can be brought into contact with corresponding nonconductive regions of the carrier 3. The interaction of the activated surfaces can cause the nonconductive regions of the dies 2a-2c to directly bond with the corresponding nonconductive regions of the carrier 3 without an intervening adhesive, without application of external pressure, without application of voltage, and at room temperature. In various embodiments, the bonding forces of the nonconductive regions can include covalent bonds that are greater than Van der Waals bonds and exert significant forces between the conductive features. Prior to any heat treatment, the bonding energy of the dielectric-dielectric surface can be in a range from 150-300 mJ/m2, which can increase to 1500-4000 mJ/m2 after a period of heat treatment. Regardless of whether the conductive features are flush with the nonconductive regions, recessed or protrude, direct bonding of the nonconductive regions can facilitate direct metal-to-metal bonding between the conductive features. In various embodiments, the dies 2a-2c and the carrier 3 may be heated after bonding at least the nonconductive regions. As noted above, such heat treatment can strengthen the bonds between the nonconductive regions, between the conductive features, and/or between opposing conductive and non-conductive regions. In embodiments where one or both of the conductive features are recessed, there may be an initial gap between the conductive features of the dies 2a-2c and the carrier 3, and heating after initially bonding the nonconductive regions can expand the conductive elements to close the gap. Regardless of whether there was an initial gap, heating can generate or increase pressure between the conductive elements of the opposing parts, aid bonding of the conductive features and form a direct electrical and mechanical connection.
Additional details of the direct bonding processes used in conjunction with each of the disclosed embodiments may be found throughout U.S. Pat. Nos. 7,126,212; 8,153,505; 7,622,324; 7,602,070; 8,163,373; 8,389,378; and 8,735,219, and throughout U.S. Patent Application Nos. 14/835,379; (issued as U.S. Pat. No. 9,953,941); 62/278,354; 62/303,930; and 15/137,930, (published as US 2016/0314346), the contents of each of which are hereby incorporated by reference herein in their entirety and for all purposes.
Direct bonding of the dies 2a-2c to the carrier 3 can result in a bond interface 6 between the elements 2 and the carrier 3. The waveguide 10 can be defined along the interface 6 between the carrier 3 and the elements 2 (the dies 2a-2c). For example, as explained herein, the waveguide 10 can comprise a first waveguide portion 10a that is defined by features at the respective lower surfaces 12 of the elements 2 and at an upper surface 5 of the carrier 3. As explained below in connection with
The walls 11a-11d can be electrically grounded so as to provide a bounded pathway along which electromagnetic waves can propagate. As shown in
The first waveguide portion 10a can be formed in any suitable manner, such as by damascene processes. In the arrangement illustrated in
The resulting bonded structure 1 can be bonded along the interface 6, and the waveguide 10 can be defined at least in part along the bond interface 6. For example, the first and second metallic features 14a, 14b and the associated dielectric features 7a, 7b can cooperate along the interface 6 to form the first waveguide portion 10a of the waveguide 10. In particular, the first and second metallic features 14a, 14b can bond to one another such that the walls 11c, 11d can be formed from respective side portions of the features 14a, 14b (e.g., the portions of the metal that line the sidewalls of the trenches in the elements). The walls 11a, 11b can be defined by the portions of the metal that line the bottoms of the trenches in the respective elements. As shown in the side sectional view of
Turning to
In some arrangements, it may be undesirable to provide continuous linear segments, such as the metallic features 14a, 14b shown in
Accordingly,
For example, the gaps 15 can be sized so as to be less than 20% (e.g., less than 15%, or less than 10%) of the wavelength of the waves W to be coupled to the waveguide 10. In some embodiments, the gaps 15 can be sized so as to be in a range of 0.5% to 15%, in a range of 1% to 10%, or in a range of 2% to 5% of the wavelength of the waves W to be coupled to the waveguide 10. Relatively small pitches for the metallic features 14a, 14b and associated gaps 15 therein can be defined using lithographic techniques. In various embodiments, for example, the pitch of the gaps 15 and metallic features 14a, 14b can be 30 microns or less for wavelengths greater than 300 microns. In various embodiments, the pitch of the gaps 15 and metallic features 14a, 14b can be less than 20 microns or less than 10 microns. In various embodiments, the pitch of the gaps 15 and metallic features 14a, 14b can be in a range of 1 micron to 40 microns, in a range of 1 micron to 30 microns, in a range of 5 microns to 30 microns, in a range of 5 microns to 20 microns, or in a range of 5 microns to 10 microns. The ability to create small pitch discontinuities or gaps in the metallic features 14a, 14b in a semiconductor element (such as a die or interposer) can beneficially reduce dishing while enabling little or no degradation in electrical performance. For waveguides 10 that are completely embedded in the semiconductor element, the pitch can be further reduced, e.g., to below 1 micron as defined by photolithographic limits.
As shown in
Upon bonding of the dies 2a, 2b to the carrier 3, the radiating elements 13a, 13b can electromagnetically couple to the waveguide 10 by way of the ports 17b, 17d. In the illustrated embodiment, the radiating elements 13a, 13b can comprise probes of a conductive segment that are inserted into openings in the metallic channel 11 defined by the ports 17b, 17d. In other embodiments, as explained above, the radiating elements 13a, 13b can comprise other suitable structures, such as conductive loops or apertures. Accordingly, in the embodiment shown in
Thus, as shown in
In one embodiment, a structure is disclosed. The structure can include a first element and a carrier bonded to the first element along an interface. The structure can include a waveguide defined at least in part along the interface between the first element and the carrier. The waveguide can comprise an effectively closed metallic channel and a dielectric material within the effectively closed metallic channel as viewed from a side cross-section of the structure.
In another embodiment, a structure is disclosed. The structure can include a semiconductor element having a waveguide at least partially embedded therein. The waveguide can comprise an effectively closed metallic channel and a dielectric material within the effectively closed metallic channel as viewed from a side cross-section of the structure. The structure can include a first port extending through the effectively closed metallic channel to an exterior surface of the semiconductor element. The first port can be configured to couple to a radiating element to transmit electromagnetic radiation to, or to receive electromagnetic radiation from, the waveguide.
In another embodiment, a method of forming a structure is disclosed. The method can include providing a first element and a carrier. The first element can comprise first metallic features and first dielectric features exposed on an exterior surface of the first element. The carrier can comprise second metallic features and second dielectric features exposed on an exterior surface of the carrier. The method can include bonding the first element to the carrier along an interface to bond the first metallic features and the second metallic features and to bond the first dielectric features and the second dielectric features. The bonded first element and carrier can define a waveguide at least in part along the interface between the first element and the carrier. The waveguide can comprise an effectively closed metallic channel and a dielectric material within the effectively closed metallic channel as viewed from a side cross-section of the structure.
For purposes of summarizing the disclosed embodiments and the advantages achieved over the prior art, certain objects and advantages have been described herein. Of course, it is to be understood that not necessarily all such objects or advantages may be achieved in accordance with any particular embodiment. Thus, for example, those skilled in the art will recognize that the disclosed implementations may be embodied or carried out in a manner that achieves or optimizes one advantage or group of advantages as taught or suggested herein without necessarily achieving other objects or advantages as may be taught or suggested herein.
All of these embodiments are intended to be within the scope of this disclosure. These and other embodiments will become readily apparent to those skilled in the art from the following detailed description of the embodiments having reference to the attached figures, the claims not being limited to any particular embodiment(s) disclosed. Although this certain embodiments and examples have been disclosed herein, it will be understood by those skilled in the art that the disclosed implementations extend beyond the specifically disclosed embodiments to other alternative embodiments and/or uses and obvious modifications and equivalents thereof. In addition, while several variations have been shown and described in detail, other modifications will be readily apparent to those of skill in the art based upon this disclosure. It is also contemplated that various combinations or sub-combinations of the specific features and aspects of the embodiments may be made and still fall within the scope. It should be understood that various features and aspects of the disclosed embodiments can be combined with, or substituted for, one another in order to form varying modes of the disclosed implementations. Thus, it is intended that the scope of the subject matter herein disclosed should not be limited by the particular disclosed embodiments described above, but should be determined only by a fair reading of the claims that follow.
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Number | Date | Country | |
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20180191047 A1 | Jul 2018 | US |