1. Technical Field
The present invention relates to integrated circuits intended for operating at very high frequency and more specifically to such circuits, some portions of which are sensitive to noise signals.
2. Description of the Related Art
For example, in the field of telecommunications and of portable phones, it is desired to integrate on a same chip logic signal processing circuits and analog amplifying circuits, intended for operating at very high frequencies, greater than 1 GHz, ranging for example from 2 to 10 GHz. In particular, a low-noise analog amplifier directly connected to the antenna output is generally provided. It is important to avoid that the noise resulting from the switchings of the digital signals affects the amplifier inputs since this noise would then be injected back into the circuit with a very high gain.
To test the sensitivity to noise of an integrated circuit and of various protection circuits, a test structure such as that shown in
As illustrated by the partial cross-section view of
Such a protective structure is efficient at frequencies smaller than 1 GHz. However, as illustrated in
Various theoretical explanations could be found for this phenomenon, which in any case is certainly due to the fact that the impedance of the connection of isolating wall 15 to ground becomes high. Thus, in prior art, various means for reducing the value of this impedance have been tried. One of these means is to use a so-called “flip-chip” semiconductor chip assembly mode in which the connection points on the chip are metallized and coated with conductive balls. Each conductive ball is then directly put in contact with a metallized region of a printed circuit board to which this chip is to be connected. Connections with a much smaller impedance than in the case where the chips are assembled in a package and connected to the package tabs by wires are thus obtained. However, this has not enabled completely solving the problem posed and has only partially improved the features of known protection structures.
Thus, an object of the present invention is to provide a novel structure of protection against noise of an area of an integrated circuit formed on a massive substrate.
To achieve this object, the present invention provides a structure of protection of a first area of a semiconductor wafer including a substrate of a first conductivity type against high-frequency noise likely to be injected from components formed in the upper portion of a second area of the wafer, including a very heavily-doped wall of the first conductivity type having substantially the depth of said upper portion. The wall is divided into three heavily-doped strips of the first conductivity type separated and surrounded by medium-doped intermediary strips of the first conductivity type, the distance between the end heavily-doped strips being of the order of magnitude of the substrate thickness.
According to an embodiment of the present invention, the first conductivity type is type P.
According to an embodiment of the present invention, each of the three heavily-doped P-type strips is divided into successive segments.
According to an embodiment of the present invention, each segment is connected to a ground plane via a flip-chip assembly.
The foregoing objects, features and advantages of the present invention will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings, in which:
As usual in the representation of semiconductor components, the various cross-section views and top views of components are not drawn to scale in the various drawings. In these drawings, same references designate identical or similar elements.
As shown in
Assuming in
With a triple wall according to the present invention, all other things being equal, a −54-dB damping is obtained between squares C1-1 and C14-14 for a 2-GHz frequency, while, as shown in
To further improve the operation of the system according to the present invention, instead of using continuous strips 21, these strips may be divided into successive segments, each segment being coated with a metallization independently connected to a ground plane. Preferably, the segments will be arranged in quincunx, that is, the intervals between two segments of the median strips will be placed substantially in front of the middle of segments of the end strips. This segmentation is illustrated as an example by areas 25 shown between two dotted lines in
As an example, for a P substrate having a 350-μm thickness, three P+ strips having a 10-μm width spaced apart by 175 μm may be used, these strips being segmented into segments having a length on the order of 175 μm, each segment being provided with a contact pad, the distance between pads being on the order of 200 μm.
Number | Date | Country | Kind |
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01 01524 | Feb 2001 | FR | national |
Filing Document | Filing Date | Country | Kind | 371c Date |
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PCT/FR02/00423 | 2/4/2002 | WO | 00 | 8/5/2003 |
Publishing Document | Publishing Date | Country | Kind |
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WO02/063692 | 8/15/2002 | WO | A |
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