Claims
- 1. A data processing system comprising:a central processing unit executing program instructions to manipulate data; at least one level one cache connected to said central processing unit temporarily storing at least one of program instructions for execution by said central processing unit and data for manipulation by said central processing unit; a level two unified cache connected to said level one instruction cache and said level one data cache for supply of instructions to said level one instruction cache and data to said level one data cache; a directly addressable memory; a direct memory access unit connected to said directly addressable memory and adapted for connection to an external memory; and a superscalar memory transfer controller connected to said level one instruction cache, said level one data cache, said level two unified cache, said directly addressable memory and said direct memory access unit, said superscalar memory transfer controller operable in memory cycles and capable of scheduling plural non-interfering memory movements to and from said level two unified cache and said directly addressable memory each memory cycle in accordance with a predetermined priority of operation.
- 2. The data processing system of claim 1, wherein:said at least one level one cache includes a level one instruction cache temporarily storing program instructions for execution by said central processing unit.
- 3. The data processing system of claim 1, wherein:said at least one level one cache includes a level one data cache temporarily storing data for manipulation by said central processing unit.
- 4. The data processing system of claim 1, wherein:said level two unified cache includes a cache tag memory having plural read ports and a single write port; and said superscalar memory transfer controller is capable of scheduling plural cache tag memory read accesses and one cache tag memory write access in a single memory cycle.
- 5. The data processing system of claim 1, wherein:said level two unified cache includes a cache access state machine for each of said at least one level one caches, a cache access state machine for said direct memory access unit, a cache access state machine for level two unified cache read miss service, a cache access state machine for level two unified cache write miss service and a cache access state machine for victim eviction service; and said superscalar memory transfer controller is capable of scheduling plural of said cache access state machines in a single memory cycle.
- 6. The data processing system of claim 1, wherein:said level two unified cache consists of plural memory banks; and said superscalar memory transfer controller is capable of scheduling plural memory accesses to non-interfering memory banks of said level two unified cache in a single memory cycle.
- 7. In data processing system including a central processing unit executing program instructions to manipulate data, at least one level one cache connected to said central processing unit temporarily storing at least one of program instructions for execution by said central processing unit and data for manipulation by said central processing unit, a level two unified cache connected to said level one instruction cache and said level one data cache for supply of instructions to said level one instruction cache and data to said level one data cache, a directly addressable memory and a direct memory access unit connected to said directly addressable memory and adapted for connection to an external memory, the method comprising the steps of:operating in memory cycles; and scheduling plural non-interfering memory movements to and from said level two unified cache and said directly addressable memory in accordance with a predetermined priority of operation in a single memory cycle.
- 8. The method of claim 7, wherein said level two unified cache includes a cache tag memory has plural read ports and a single write port, the method further comprising the step of:scheduling plural cache tag memory read accesses and one cache tag memory write access in single memory cycle.
- 9. The method of claim 7, further comprising the step of:scheduling a plurality of a cache access state machine for each of said at least one level one caches, a cache access state machine for said direct memory access unit, a cache tag access state machine for level two unified cache read miss service, a cache tag access state machine for level two unified cache write miss service and a cache tag access state machine for victim eviction service in a single memory cycle.
- 10. The method of claim 7, wherein said level two unified cache consists of plural memory banks, the method further comprising the step of:scheduling plural memory accesses to non-interfering memory banks of said level two unified cache in a single memory cycle.
Parent Case Info
This application claims priority under 35 USC §119(e)(1) of Provisional Application No. 60/144,550, filed Jul. 15, 1999 now abandoned and Provisional Application No. 60/166,536, filed Nov. 18, 1999 now abandoned.
US Referenced Citations (4)
Number |
Name |
Date |
Kind |
5107416 |
Jippo et al. |
Apr 1992 |
A |
6260081 |
Magro et al. |
Jul 2001 |
B1 |
6345320 |
Kawamata et al. |
Feb 2002 |
B1 |
6351781 |
Gracias et al. |
Feb 2002 |
B1 |
Provisional Applications (2)
|
Number |
Date |
Country |
|
60/144550 |
Jul 1999 |
US |
|
60/166536 |
Nov 1999 |
US |