The present disclosure relates to electronics modules with protective finishes suitable for use with both flip chip and wire bond components.
Electronics modules and printed circuit boards (PCBs) are often used to support and connect several electrical components. Generally, an electronics module and/or PCB includes a non-conductive body for support, and a plurality of conductive features for connecting the various electrical components. The conductive features may be any type of conductive structure and may include contact pads, conductive traces, vias, and/or the like. Electrical components such as resistors, capacitors, inductors, bond wires, and integrated circuits (ICs) are mounted to one or more exposed portions of the conductive features by a soldering process. For example, the conductive features may include one or more contact pads connected to one another by one or more conductive traces. An electrical component (such as a resistor, a capacitor, an inductor, an IC, etc.) may be mounted on the one or more conductive pads by the soldering process. Accordingly, one or more circuits may be formed on the electronics module and/or PCB.
The conductive features discussed above are often created by a copper etching process, wherein a thin copper sheet is laminated onto the non-conductive body and etched to form a connection pattern. The conductive properties and performance characteristics of the conductive features may degrade over time due to oxidation and exposure to the elements. Accordingly, a protective finish is generally deposited onto the one or more conductive features in order to preserve the conductive properties thereof.
While there are many protective finishes commercially available today, most if not all of these protective finishes are suitable for only a single type of electronics packaging system. For example, conventional protective finishes are generally suitable for either wire bond components or flip chip components, but not both. This is due to the different bonding types utilized for wire bond and flip chip components. Specifically, while the electrical connection points for a wire bond component do not need to support any structure, those for a flip chip component do. Accordingly, surface finishes for flip chip components require mechanical stability and reliability against forces such as shear. For purposes of illustration, an exemplary wire bond component 10 and electronics module 12 are shown in
In some situations, it may be necessary to utilize both wire bond and flip chip components on a single electronics module. As discussed above, the protective finishes used for wire bond and flip chip components are typically not compatible with one another. Accordingly,
The first mask 32 is then removed (step 106 and
Accordingly, there is a need for an electronics module that is easy to manufacture, robust, and capable of supporting both wire bond and flip chip components.
The present disclosure relates to electronics modules with protective finishes suitable for use with both flip chip and wire bond components. In one embodiment, an electronics module includes a non-conductive body, a first set of conductive features exposed on a surface of the non-conductive body, and a second set of conductive features exposed on the surface of the non-conductive body. The first set of conductive features is configured to connect to a wire bond component. The second set of conductive features is configured to connect to a flip chip component. A protective finish is provided over each one of the first set of conductive features and the second set of conductive features. The protective finish includes a layer of nickel less than 1 μm thick, a layer of palladium over the layer of nickel, and a layer of gold over the layer of palladium. By using the protective finish including a layer of nickel less than 1 μm thick, a layer of palladium over the layer of nickel, and a layer of gold over the layer of palladium, both flip chip and wire bond components may be connected to the electronics module while utilizing the single protective finish, thereby saving both time and cost in the production of the electronics module.
In one embodiment, a method for manufacturing an electronics module includes the steps of providing a non-conductive body including a first set of conductive features suitable for connecting a wire bond component to the electronics module and a second set of conductive features suitable for connecting a flip chip component to the non-conductive body and providing the same protective finish over the first set of conductive features and the second set of conductive features. The protective finish includes a layer of nickel less than 1 μm thick, a layer of palladium over the layer of nickel, and a layer of gold over the layer of palladium. By using the protective finish including a layer of nickel less than 1 μm thick, a layer of palladium over the layer of nickel, and a layer of gold over the layer of palladium, a wire bond component may be coupled to the first set of conductive features and a flip chip component may be coupled to the second set of conductive features while utilizing only one protective finish. Accordingly, both time and cost in the production of the electronics module can be saved.
Those skilled in the art will appreciate the scope of the present disclosure and realize additional aspects thereof after reading the following detailed description of the preferred embodiments in association with the accompanying drawing figures.
The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure.
The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the disclosure and illustrate the best mode of practicing the disclosure. Upon reading the following description in light of the accompanying drawings, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.
It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.
Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and/or “including” when used herein specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
A protective finish 52 is located over each one of the first set of conductive features 48 and the second set of conductive features 50. Notably, the protective finish 52 provided over the first set of conductive features 48 and the second set of conductive features 50 is the same protective finish. Accordingly, the manufacturing process of the electronics module 44 may be significantly streamlined, as discussed in detail below. In one embodiment, the protective finish 50 includes a layer of nickel, a layer of palladium over the layer of nickel, and a layer of gold over the layer of palladium. Known in the industry as an ENEPIG protective finish, conventional ENEPIG formulations often include a relatively thick (i.e., >3 μm) layer of nickel. The inventors discovered that conventional ENEPIG protective finishes are generally unsuitable for flip chip components due to the thick layer of nickel that is conventionally included therein. Specifically, using a thick layer of nickel results in unreliable and structurally unsound solder joints when connecting a flip chip component to a conductive feature with an ENEPIG protective finish. Accordingly, the protective layer 52 shown in
The non-conductive body 46 may be any suitable material. In one embodiment, the non-conductive body 46 is a laminate material such as that typically used to support printed circuit boards (PCBs). Specifically, the non-conductive body 46 may be formed of any material that acts as an electrical insulator such as a multifunctional epoxy, an epoxy blend, a bismaleimide-triazine (BT) resin, a ceramic, or the like.
To electrically connect the wire bond component 54 to the first set of conductive features 48, a localized attachment process is used, wherein the various wire bonds 60 are attached to a conductive pad (not shown) on the wire bond component 54 and also to one of the first set of conductive features 48. First, heat, pressure, and/or ultrasonic energy may be applied directly to each one of the first set of conductive features 48 over which the wire bond 60 has been placed. Accordingly, each one of the wire bonds 60 is effectively welded to a corresponding one of the first set of conductive features 48.
To electrically connect the flip chip component 56 to the second set of conductive features 50, a solder reflow process is used, wherein the solder balls 62 of the flip chip component 56 are aligned with the second set of conductive features 50 and heat is applied in order to reflow the solder balls and form an electrical connection between the solder balls 62 and a corresponding one of the second set of conductive features 50. In the course of the reflow process, a portion of the protective finish 52 is dissolved surrounding each one of the solder balls 62. Notably, the thin layer of nickel is dissolved in order to allow each one of the solder balls 62, which may be tin, to directly contact a corresponding one of the second set of conductive features 50. Since the second set of conductive features 50 is generally copper, a copper-on-tin solder joint is formed in which the tin substantially dissolves into the copper, thereby resulting in improved reliability and electrical characteristics when compared to the use of conventional protective finishes.
The protective finish 52 is then provided over the first set of conductive features 48, and the second set of conductive features 50 (step 204 and
The flip chip component 56 is then coupled to the second set of conductive features 50 (step 210 and
Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.
This application claims the benefit of provisional patent application Ser. No. 61/926,498, filed Jan. 13, 2014, the disclosure of which is hereby incorporated herein by reference in its entirety.
Number | Date | Country | |
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61926498 | Jan 2014 | US |