Patent Application
20240112076
This disclosure relates generally to the implementation of machine learning networks on hardware and more particularly to the synchronization of compute elements executing statically scheduled instructions.
Machine learning is one of the most powerful recent trends in technology. In machine learning, a model is developed to perform a certain task. The model, which will be referred to as a machine learning network, is trained and deployed in order to carry out that task. For example, a model may be developed to recognize the presence of objects within images captured by a set of cameras. Once the model is deployed, images captured by the cameras are input to the machine learning network, which then outputs whether or to what confidence level objects are present within the images.
Machine learning networks typically require the handling of a large volume of data and the execution of a large number of computations. As a result, they are commonly implemented in compute facilities with access to significant resources, such as in the cloud or on server clusters. There can be many advantages if the machine learning network was instead embedded on edge devices, such as combined in a camera system. However, many types of edge devices, such as cameras, have resource limitations. They may be limited in memory, processing capability, power consumption, etc. As a result, on-chip compute elements may be simplified to conserve resources, but this may give rise to a need to synchronize the operation of these elements.
Embodiments of the disclosure have other advantages and features which will be more readily apparent from the following detailed description and the appended claims, when taken in conjunction with the example embodiments in the accompanying drawings, in which:
The figures and the following description relate to preferred embodiments by way of illustration only. It should be noted that from the following discussion, alternative embodiments of the structures and methods disclosed herein will be readily recognized as viable alternatives that may be employed without departing from the principles of what is claimed.
Machine learning networks (MLNs) are commonly implemented in compute facilities with access to significant resources, such as in the cloud or on server clusters. However, the sources of input to machine learning networks may be located remotely from these large compute facilities. For example, cameras and other types of sensors may be edge devices. Example applications for edge devices include automotive and other forms of transportation including autonomous transportation, agricultural, industrial, robotics, drones, surveillance and security, smart environments including smart cities, medical and personalized health. Example tasks include computer vision, image analysis, image understanding, speech recognition, audio analysis, audio understanding, natural language processing, classification and pattern recognition tasks. For edge devices, it may be desirable to perform certain tasks in real-time. In addition to memory and other programmable processors, an edge device may also include sensors, such as cameras including both still image and video cameras, microphones, temperature sensors, pressure sensors and other types of sensors. The sensors may capture samples that are used as inputs to a computing pipeline within the edge device. Thus, it would be beneficial if MLNs could be implemented in edge devices.
A Machine Learning Accelerator (MLA) is described herein that may be built into an edge device. The MLA executes a machine learning network. As will be described in more detail below, one method of optimizing execution of an MLN is to use a compiler that, prior to run-time, generates a computer program with statically scheduled instructions for executing the MLN. For example, the compiler may determine which instructions are executed by which compute elements in the MLA at what time. Static scheduling enables the compute elements in the MLA to execute the instructions with no run-time conditions, branching or dependencies. This may result in lower power consumption, simpler MLA design, and lower cost.
However, because on-chip memory is limited, the statically scheduled instructions and corresponding data may be stored in off-chip memory and then transferred to on-chip storage elements for consumption by the on-chip processing elements. On-chip memory such as SRAM has a known access time, so data transfers from/to SRAM storage elements to/from processing elements may be statically scheduled. However, SRAM typically has limited space.
Off-chip memory such as DRAM has much more space available, but it has variable access time, so the compiler may not be able to predict when the instructions or corresponding data fetched from the off-chip memory will be ready for execution and cannot statically schedule data and instruction transfers from DRAM. This issue may be compounded if instructions are to be executed by multiple processing elements according to a common static schedule because the compiler assumes that the processing elements are synchronized in their operation. One processing element cannot start execution of its statically scheduled instructions later than another processing element, just because its instructions or data arrived later.
In one approach, a mechanism is used to detect whether sufficient instructions and data have been transferred from off-chip memory to the on-chip storage elements and processing elements in order to fulfill the static schedule. If sufficient instructions or data are not available, then execution of the statically scheduled instructions is suspended until the transfers from off-chip memory catches up sufficiently.
The system in
In
Note that the static schedule determined by the compiler may or may not be included as part of the instructions and computer program. In some embodiments, the computer program may expressly include the schedule, specifying that instruction A is executed at cycle X, instruction B is executed at cycle X+4, instruction C is executed at cycle X+12, etc. In alternate embodiments, the computer program may specify only that instruction A is executed, followed by instruction B, and then instruction C, but without any scheduling information. Even though the static schedule is not expressly specified, these instructions will still execute according to the static schedule determined by the compiler because the compiler knows how long it takes to execute each instruction. As a result of the static scheduling, the MLA and instruction set for the MLA may be simplified, with the complexity offloaded to the compiler. A simpler MLA can result in lower cost, lower power consumption and higher performance, all of which are desirable for implementation in edge devices.
In more detail, the MLN 200 may be described by an architecture and parameters. A depiction of an MLN is shown to the right of box 200 in
y=F(Σwixi+b) (1)
where xi are the inputs received from other nodes i, wi are weights, b is a bias and F( ) is a nonlinear operator. The MLN architecture includes the number of nodes and layers and their interconnectivity, and the operators applied at nodes. The operators may be described in a parameterized form. The MLN parameters include the weights, biases, and parameters for the operators.
MLNs may vary in size, depending on the desired task. Small MLNs may have 5-10 or fewer layers, medium size MLNs may have 30-50 layers, and large MLNs may have 200 or more layers. Examples of inputs include text, images and video. Some of the layers may be fully interconnected where every node in one layer provides input to every node in the next layer. Others may be more locally interconnected, for example to implement convolutions. Each weighted interconnect represents a scalar multiplication. The total number of scalar multiplications required to implement an MLN may be on the order of millions, billions, tens of billions or even more. These may be carried out by matrix multiplications.
The MLA 270 includes a plurality of Tiles 280 and an on-chip memory system with storage elements (not shown in
The compiler 220 receives a description of the MLN 200 and generates a computer program 250 that implements the MLN using the MLA 270. The computer program 250 receives an input sample for the MLN and executes the operations of the MLN to produce the output for the MLN. The computer program 250 includes instructions to be executed by the Tiles for implementing computations in the MLN and may also include instructions to be executed by other elements, such as the storage elements of the on-chip memory or a controller outside the Tiles. For additional examples and description of the MLA and related components, see U.S. application Ser. No. 16/840,216, “Machine Learning Network Implemented by Statically Scheduled Instructions, with Compiler,” which is incorporated by reference herein in its entirety.
The program of statically scheduled instructions may include a series of computations required to implement a portion of the MLN, where the time required for each computation and associated data transfers is known. As a result, the compiler may statically schedule these instructions. The resulting computer program produced by the compiler then implements an allocation of compute instructions to Tiles and a schedule for executing the instructions as determined by the compiler, although these may not be expressly contained with the computer program.
Non-deterministic instructions are also used. For example, non-deterministic instructions may include data fetch and instruction fetch from off-chip memory where the time required to execute the operation varies too much to allow reliable synchronization with other operations. Other examples include computations that occur off-chip, and conditions, branching and other programmatic constructs that depend on values not known until run-time.
The example instructions shown in
For Tile 1, instruction 255a transfers data into Tile 1 from either another Tile or from ones of the SEs, and instruction 255b then performs a computation that consumes that data. Instruction 255b is dependent on instruction 255a. Here, the T1 C pipeline is not required to continuously poll the T1 D pipeline at run-time for when the data is available, and run-time message passing between the pipelines is not required to indicate that the data is available. Rather, because the duration (i.e., time required to execute) of instruction 255a is known, the compiler knows when the data will be available (for convenience, marked as cycle c1 in the figure) and can construct a static schedule in which instruction 255b starts execution then. The duration of instruction 255b is also known, so the compiler knows that compute instruction 255d may start after instruction 255b. In this case, the compiler determines a static schedule in which instruction 255d starts at cycle c3. Compute instruction 255d depends on data brought into the Tile by instruction 255c. The duration of instruction 255c is known, so the compiler knows that in the static schedule, instruction 255c must start at cycle c2 or earlier. This pattern is repeated for pairs of data transfer instructions and compute instructions 255e-f, 255g-h, 255i-j.
For Tile 2, compute instruction 2551 depends on data from data transfer instruction 255k. However, instruction 255k does not start immediately at cycle c0. Rather, it has a delayed start at cycle c4. This may be because the data transfer path required by instruction 255k is occupied by some other data transfer instruction and is not available until cycle c4. The start time of instruction 255k in the static schedule is not determined by run-time arbitration or contention mechanisms for the shared data transfer path. Rather, the compiler knows that the data transfer path is occupied since the compiler knows the start times and durations of all the data transfer instructions, so the compiler simply creates a static schedule in which instruction 255k does not start until cycle c4 when the compiler knows the data transfer path will be available. Similarly, data transfer instruction 255m has a delayed start time. Perhaps the T2 D pipeline is being used to transfer out the results of computation 2551 and does not become available until cycle c5.
For Tile 3, computation 255n starts immediately at cycle c0. Perhaps the required data was loaded into Tile 3 during some prior phase. Data transfer instructions 255o and 255p load data for compute instruction 255q. They are separated in time, perhaps because different pieces of data were not available or the data transfer paths were not available until those times. As a final example, data transfer instruction 255r loads data for compute instruction 255s. In the static schedule, the compiler places instruction 255r well in advance of when the data is required, but this may be because that is when the data transfer path is available or perhaps the data was transferred out of the sourcing Tile in order to make room in that Tile.
Execution of the instructions according to the static schedule at run-time may be implemented in different ways. In one approach, the computer program includes an express schedule for the execution of the instructions. Continuing the example of
In order to statically schedule the instructions, the compiler typically will know the duration of each instruction (i.e., how long each instruction takes to execute), the capabilities of each Tile (which Tiles can execute which instructions), the topology of data transfer paths to and from Tiles (including between Tiles, and between Tiles and on-chip memory), and the computations required and their dependencies (i.e., the MLN description). With this information, the compiler can schedule unconditional start times for the Tile instructions. Here, unconditional refers to run-time conditions. The execution order of statically scheduled instructions will not change as a result of run-time conditions, branching or dependence on input values. As a result, compute instructions may be scheduled for start times when all of the required data for the computation is known to be available and the compute pipeline is also known to be available. The need for run-time determination of whether data has arrived and whether the compute pipeline is available may be avoided. Analogously, data transfer instructions may be scheduled for start times when the data transfer path is known to be available. The need for circuitry to handle arbitrations, or to check for or resolve contentions and collisions on shared data transfer paths at run-time may be avoided. The need for routing tables and other circuitry to determine routing at run-time may also be avoided.
The static schedule of
The PE 380 also includes a sync detector 394, which ensures that the instruction queue 382 stores sufficient instructions to meet the static schedule. In one approach, before execution switches from sub-queue 383A to sub-queue 383B, the sync detector determines whether sub-queue B stores sufficient instructions to meet the static schedule. If not, the sync detector 394 sends a sync request to the sync controller 396 and the sync controller 396 then suspends operation of the computing mesh until enough instructions are stored in sub-queue B.
There may be some latency between the time when the sync detector 394 determines there are not sufficient instructions and the time when operation of the computing mesh is suspended. Assume that this latency takes N cycles. Then the sync detector 394 makes its determination at least N cycles in advance. In one approach, the sync detector 394 may continuously query whether the instruction queue has sufficient instructions for the next N cycles. This is accurate, but may introduce more overhead than is desirable.
An alternate approach makes use of the sub-queues. The test for “sufficient number of instructions” is whether sub-queue B is filled with instructions. This test is performed at least N cycles before the execution of instructions from sub-queue A completes. Different instructions may take different number of cycles to complete. In a simple approach, it is assumed that each instruction must take at least one cycle, so the sync detector 394 queries whether sub-queue B is filled at least N instructions before the instructions from sub-queue A complete execution. For example, if the sub-queues each hold 32 instructions and N=10, then the sync detector 394 makes the query after the first 22 instructions in sub-queue A have executed because the remaining 10 instructions will require at least 10 cycles to complete.
In a more accurate approach, the actual execution time for each instruction is used. For example, if the last two instructions in sub-queue A are scheduled to take 4 and 6 cycles to execute, then the sync detector 394 makes the query after the first 30 instructions in sub-queue A have executed because the remaining 2 instructions will require at least 10 cycles to complete. Other estimates of the execution time of instructions may be used, ranging from the conservative estimate of 1 cycle per instruction to the accurate estimate based on actual execution time.
If the sync detector 394 determines there are insufficient instructions in the queue, it instructs the sync controller 396 to suspend operation of the computing mesh. Transfers from off-chip memory into the instruction queue continue. Once the requisite number of instructions is in the queue (e.g., once sub-queue B is filled), the sync detector 394 signals the sync controller 396 to resume operation of the computing mesh.
At the end of the program, the sub-queue may contain all of the instructions that are available but it may not be full because the end of the program has been reached. In that case, the sync detector 394 does not generate a sync request. Once the end of the program has been reached and the last instruction is loaded into the instruction queue, the sync detector 394 need not continue to test for a sufficient number of instructions.
At the start of the program, it is important that the compute elements start together in order to maintain synchronization. In one approach, the sync detector 394 signals to the sync controller 396 when the instruction queue 382 is filled (or when one sub-queue 383A is filled). When the sync controller 396 receives these signals from all of the compute elements, then it starts execution of the statically scheduled program.
The SE 490 also includes a sync detector 494. In one approach, the sync detector 494 includes a register that stores the states of the bank 493, where the states are (X) data transfer with off-chip memory (off-mesh mode), and (Y) data transfer within the computing mesh (intra-mesh mode). Assume that bank 493 is in state X because data is transferring between bank 493 and off-chip memory. These data transfers may be reads or writes. When all the data transfers are completed, the state is changed from X to Y, indicating that bank 493 is ready for intra-mesh data transfers (i.e., statically scheduled data transfers). When the intra-mesh data transfers are completed, the state is changed from Y back to X, indicating that the sub-bank is now ready for data transfers with the off-chip memory.
Intra-mesh data transfers from PEs (or other SEs) to SE 490 occur as follows. A packet from PE to SE 490 is transmitted with a gap between header and payload. When the header reaches SE 490, the SE determines whether it is in state Y (intra-mesh mode). If so, then the data transfer continues and the payload is also received. However, if the SE 490 is in state X (off-mesh mode), then the sync detector 494 instructs the sync controller 496 to suspend operation of the computing mesh. The payload from the PE is frozen in the computing mesh while the SE 490 continues its off-mesh operations with off-chip DRAM. Once these off-mesh transfers are completed, the state is changed to Y (intra-mesh mode) and the payload transfer to the SE 490 is completed.
Intra-mesh data transfers from SE 490 to PEs (or other SEs) occur as follows. The PE sends a data request to the SE 490. If the SE 490 is in state Y (intra-mesh mode), then it can transfer the data packet to the PE. If the SE 490 is in state X (off-mesh mode), then the sync detector 494 instructs the sync controller 496 to suspend operation of the computing mesh. The data packet is not transferred from SE 490 to the PE until the off-mesh transfers are completed and the SE 490 returns to state Y.
If there is a latency of N cycles before suspending operation of the computing mesh, then the sync detector 494 should make its determination at least N cycles in advance. For example, the time gap between the packet header and packet payload is at least N cycles, and the time gap between the data request and the data packet is also at least N cycles.
In
In
The resulting optimized description 635 of the MLN may be expressed as a graph, in which the nodes of the graph represent nodes in the MLN and the edges of the graph represent the weighted interconnects. The compiler 620 receives the optimized graph 635 and produces the resulting computer program 650. The compiler 620 may perform operations including static scheduling 622, PPA (power performance area) optimizations 624, graph optimizations 626 and/or partitioning 628.
In order to statically schedule 622 the deterministic instructions, the compiler typically will know the duration of each instruction (i.e., how long each instruction takes to execute), the capabilities of each element (which processing elements and storage elements can execute which instructions), the topology of data transfer paths to and from Tiles (including between Tiles, and between Tiles and on-chip memory), and the computations required and their dependencies (i.e., the MLN description). With this information, the compiler can schedule unconditional start times for the deterministic instructions. Here, unconditional refers to run-time conditions. The execution order of statically scheduled instructions will not change as a result of run-time conditions, branching or dependence on input values. As a result, compute instructions may be scheduled for start times when all of the required data for the computation is known to be available and the compute pipeline is also known to be available. The need for run-time determination of whether data has arrived and whether the compute pipeline is available may be avoided. Analogously, data transfer instructions may be scheduled for start times when the data transfer path is known to be available. The need for circuitry to handle arbitrations, or to check for or resolve contentions and collisions on shared data transfer paths at run-time may be avoided. The need for routing tables and other circuitry to determine routing at run-time may also be avoided.
PPA optimization 624 includes different optimizations of the computer program 650. For example, the allocation of MLN computations to Tiles may be optimized to reduce power consumption, to increase performance (such as reducing latency or increasing throughput) and/or to reduce area (e.g., number of Tiles used). The compiler 620 may also optimize 624 the computer program 650, subject to constraints on power, performance, area and/or any of the quantities described above. Graph optimization 626 includes analysis of the graph representing the MLN to prune, merge or quantize links, parameters, values, and layers to achieve better performance. Partitioning 628 concerns mapping the computations in the MLN to an implementation on the MLA. This includes determining which computations are allocated to which Tiles and how data flows through the mesh of Tiles during computation. If there are multiple mosaics, it also includes determining which computations are allocated to which mosaics.
The resulting computer program 650 may be loaded into memory for execution on a machine learning accelerator 670. For example, one possible application is object detection. In this case, the inputs are images captured by a video camera. The MLN 600 has been trained to identify certain objects in the video images. The computer program 650 implementing the MLN is loaded onto memory that is accessible by the MLA 670, which is implemented as a chip inside the camera. This way, images captured by the video camera may be immediately analyzed by the computer program 650 running on the MLA 670.
In addition to the MLA 670, the computer program 650 or parts of it may be run on a software simulator 646 and/or hardware emulator 648 (including FPGAs configured as MLAs). These may be used for product development, debugging and/or prototyping. For some purposes, a full simulation or emulation is not necessary. For example, to check that there are no collisions or conflicts between statically scheduled instructions, only the flow of data may be simulated or emulated. It is not necessary to compute actual values.
The embodiments described above may be used to execute a single MLN. However, the MLA is enabled to execute multiple MLNs.
As discussed above, the MLA includes various components that are on the same die. The MLA may be integrated into a larger integrated circuit product (e.g., as part of an edge device).
The connections to the external world include camera inputs 840 for the computer vision processors, ports for debug 842 and configuration 844, a connection 846 to external memory (e.g., DRAM), chip-to-chip connections 848, and network connections 850 (e.g., Ethernet and PCIe).
The SoC of
In addition to memory and other programmable processors, an edge device may also include sensors, such as cameras (both still image and video cameras), microphones, temperature sensors, pressure sensors and other types of sensors. The sensors may capture samples that are used as inputs to a computing pipeline within the edge device. For example, image samples may be input to the computer vision processors 812, which perform initial operations such as edge detection and enhancement, contrast enhancement, motion detection, and optical flow. Raw and/or processed images may be then input to the MLA 870 for analysis by the machine learning network. The MLA may also receive other inputs, such as metadata from other sources and data from other sensors. The application processors 810 may also perform various functions in the overall pipeline and may also serve as a master controller that coordinates operation of the MLA and the other programmable processors in the pipeline.
Edge devices may be portable with less power available for computations compared to, for example, cloud-based server farms. It may also be desirable for the computing pipeline within the edge device to perform tasks without utilizing cloud-based or other remote compute resources. In some implementations, the MLA implements computations in the machine learning network at a speed of at least 50 TOPs (50 trillion operations per second) at a power consumption of not more than 5 watts. The speed may be increased by increasing the number of Tiles in the mesh or the number of Tile meshes on the die.
Although the detailed description contains many specifics, these should not be construed as limiting the scope of the invention but merely as illustrating different examples. It should be appreciated that the scope of the disclosure includes other embodiments not discussed in detail above. Various other modifications, changes and variations which will be apparent to those skilled in the art may be made in the arrangement, operation and details of the method and apparatus disclosed herein without departing from the spirit and scope as defined in the appended claims. Therefore, the scope of the invention should be determined by the appended claims and their legal equivalents.
