SYNCHRONIZATION OF READ AND VERIFY OPERATIONS THAT MAY BE CARRIED OUT AT THE SAME TIME OVER DISTINCT PARTITIONS OF A FLASH MEMORY

Abstract

A method prevents errors in execution of simultaneous read and verify operations on data being modified in two different partitions of a nonvolatile memory device. The errors are due to disturbances caused by turning on or by turning off a bank of sense amplifiers of a partition while a critical discrimination phase is being carried out by the bank of sense amplifiers of the other partition. The method includes establishing an increase in duration of one of the two operations for exceeding a minimum duration of a critical discrimination phase for the banks of sense amplifiers, and conditionally delaying conditioning of generation of a turn on or turn off signal of the bank of sense amplifiers for the partition in which the operation of an increase in duration is in progress by a predetermined time. The predetermined time is based on a command of termination, or a beginning of the critical discrimination phase by the bank of sense amplifiers of the other partition wherein the other operation is in progress.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1, 2 and 3, as discussed above, respectively depict the supply distribution network to the banks of sense amplifiers of two distinct partitions of a memory device, the timing diagram that highlights the discussed cause of possible errors, and the scheme of a common circuit embodiment of a sense amplifier of the logic data stored in an array cell of the relative partition or sector of the memory device.

FIG. 4 depicts a sample timing diagram modified according to the invention such to ensure that no disturbance is present during a critical discrimination phase of the logic value of data read from a cell of a partition.

FIG. 5 is a basic diagram that depicts how the generation of turn on or turn off signals of a bank of sense amplifiers of a partition is conditioned in case of simultaneous read and verification operations in two different partitions.

FIG. 6 depicts a possible circuit scheme for freezing the turn on and turn off command of a bank of sense amplifiers verifying data being modified in a partition, according to a pre-established choice of penalizing verification operations for preserving the design access time of random read operations.

FIGS. 7 and 8 show the effectiveness of the invention in the two different situations of occurring simultaneously.

FIG. 9 depicts a basic circuit scheme according to the invention for momentarily preventing an aggressor circuit from causing a disturbance on common supply lines that may propagate to a victim circuit connected thereto and disturb its functioning.

FIG. 10 depicts a time graph of the main signals of the circuit scheme of FIG. 9.

Claims

1. A method of preventing errors in the execution of simultaneous read and verify operations of data being modified, in two different partitions of a nonvolatile memory device, due to disturbances caused by the turning on or by the turning off of a bank of sense amplifiers of a partition while a critical discrimination phase is being carried out by the sense amplifiers of the bank of the other partition, comprising the steps of: establishing an augmented duration of one of the two operations, exceeding the minimum duration of a critical discrimination phase of the sense amplifiers;conditionally delaying conditioning the generation of a turn on or turn off signal of the sense amplifiers of the bank of the partition in which said operation of augmented duration is in progress by a time determined by a command of termination or beginning of said critical discrimination phase by the sense amplifiers of the bank of the other partition wherein said other operation is in progress.

2. The method of claim 1, wherein said operation of augmented duration is a verify operation of data being modified in a first partition and said other operation is a read operation of data from said other partition.

3. The method of claim 1, wherein said operation of augmented duration is a read operation of data from said partition and said other operation is a verify operation of data being modified in said other partition.

4. The method of claim 1, wherein the duration of said operations and of relative signals is established in terms of number of pulses of a clock signal.

5. The method of claim 2, wherein an execution command (VERIFY) of a verify operation has a duration lasting twice the duration of a critical discrimination phase by the sense amplifiers of the banks of the two different partitions; the generation of a turn on or off signal (SAENABLE, SAENABLE_VER) of the sense amplifiers of the bank of the partition in which said verify operation is in progress is conditionally delayed by a time determined by a command (READ) for terminating or beginning said critical discrimination phase by the sense amplifiers of the bank that executes said other operation in the other partition.

6. The method of claim 5, wherein said conditionally delaying is carried out by introducing a pass-gate (1) and a latch (2) in the generation path of said turn on or turn off signal (SAENABLE, SAENABLE_VER) of the sense amplifiers of the bank of the partition in which said verify operation is in progress, controlled by said command (READ) for terminating or beginning said critical discrimination phase by the sense amplifiers of the bank that is executing said other operation in the other partition.

7. A method of preventing errors in the execution of simultaneous operations in two different circuits first and second of a device, due to disturbances caused by output switchings in the first circuit while a critical operation is being carried out by the second circuit, comprising the steps of: establishing an augmented duration of a certain phase of operation of the first circuit, to exceed the maximum duration of said critical operation of the second circuit;conditionally delaying the generation of an output switching signal of the first circuit in which said phase of augmented duration is in progress by a time determined by either a start or an end command of said critical operation executed in the second circuit.