Claims
- 1. A data converter for converting a group of vectors from a time serial to a time parallel format, wherein in the time serial format, sets of corresponding components of the vectors each have a time slot, and in time parallel format, each vector has a time slot, the converter comprising:
an input rotator configured to rotate each set of corresponding components of all vectors by an amount that depends on the time slot of the set of corresponding components; a bank of register files coupled to the input rotator to receive the rotated set of corresponding components, and having a register file in the bank configured to store each rotated set of corresponding components; an output rotator coupled to the bank of registers files, for receiving and rotating the components of a vector an amount that depends on the time slot of the vector; and a controller configured to control the addressing of the bank of register files when the corresponding components of each vector are stored in a register of the bank, and to control the addressing of the bank to collect the components of each vector for subsequent output rotation.
- 2. The data converter of claim 1,
wherein each vector has n components indexed from 0 to n−1 such that there are 0 to n−1 sets of corresponding components; and wherein the amount of rotation by the input rotator is zero for the 0th set of corresponding components, and n−1 steps clockwise for the (n−1)th set, any intervening sets of corresponding components being rotated by an amount equal to the ordinal number of the set.
- 3. The data converter of claim 1,
wherein there are n vectors indexed from 0 to n−1; and wherein the amount of rotation by the output rotator is zero for the oth vector and n−1 steps counter-clockwise for the (n−1)th vector, any intervening vectors being rotated by an amount equal to the ordinal number of the vector.
- 4. The data converter of claim 1, wherein each register file in the bank includes a register for storing the vector components.
- 5. The data converter of claim 4, wherein each vector has n components and each register file in the bank has n component registers.
- 6. The data converter of claim 5, wherein there are n register files in the bank.
- 7. The data converter of claim 1, wherein the bank of register files is configured to write and read the vector components at the same clock cycle.
- 8. The data converter of claim 1, wherein the controller can alternate between horizontal writing and reading operations and vertical writing and reading operations on the bank of register files.
- 9. The data converter of claim 8, wherein the vector has n components and the controller horizontally writes n sets of corresponding components and horizontally reads n vectors.
- 10. The data converter of claim 9, wherein, after the controller horizontally writes n sets of corresponding components and horizontally reads n vectors, the controller vertically writes n sets of corresponding components and vertically reads n vectors.
- 11. The data converter of claim 1, wherein the output rotator rotates the vector component a position equal and opposite to the input rotator.
- 12. A method for converting a group of vectors from a time serial to a time parallel format, wherein in the time serial format, sets of corresponding components of the vectors each have a time slot, and in time parallel format, each vector has a time slot, the method comprising:
for each set of corresponding components, rotating the corresponding components an amount that depends on the time slot of the corresponding component and writing each set of rotated corresponding components in a separate set of registers in a bank of register files; and for each vector in the group, reading selected registers in the bank to collect the components of the vector and rotating the collected components of the vector an amount that depends on the time slot of the vector.
- 13. The method of claim 12, wherein if the vector components are written horizontally to the bank of register files, then the vector components are read horizontally from the bank of register files.
- 14. The method of claim 12, wherein if the vector components are written vertically to the bank of register files, then the vector components are read vertically from the bank of register files.
- 15. The method of claim 12, wherein a set of corresponding components is written and the components of a vector are read in the same clock cycle.
- 16. The method of claim 12,
wherein the vector has n components; and wherein n sets of corresponding components are horizontally written over n clock cycles and vectors are horizontally read over the same n clock cycles.
- 17. The method of claim 16, wherein in another n clock cycles subsequent to the n clock cycles, n sets of corresponding components are vertically written over n clock cycles and vectors are vertically read over the same n clock cycles.
- 18. An data converter for converting a group of vectors from a time serial to a time parallel format, wherein in the time serial format, sets of corresponding components of the vectors each have a time slot, and in time parallel format, each vector has a time slot, the converter comprising:
input rotation means for rotating each set of corresponding components of all vectors by a first prescribed amount depending on the particular set; storage means coupled to the input rotation means, for storing the rotated set of corresponding components; and output rotation means coupled to the storage means, for receiving components of a vector from the storage means and rotating the components of the vector by a second prescribed amount depending on the particular vector.
- 19. The data converter of claim 18, wherein:
the input rotation means is an input rotator configured to rotate each set of corresponding components of all vectors by an amount that depends on the time slot of the set of corresponding components; the storage means is a bank of register files with a register file in the bank configured to store each rotated set of corresponding components; and the output rotation means is an output rotator configured to receive and rotate the components of a vector an amount that depends on the time slot of the vector.
- 20. The data converter of claim 19, wherein the storage means is configured to write and read the vector components in the same clock cycle.
- 21. The data converter of claim 20, wherein the storage means is configured to write corresponding components horizontally and then read vectors horizontally over a prescribed number of clock cycles.
- 22. The data converter of claim 21, wherein, during another prescribed number of clock cycles, the storage means is configured to write corresponding components vertically and then read vectors vertically.
- 23. The data converter of claim 18 further comprising controller means communicably coupled to the input rotator means, the storage means and the output rotator means, for controlling the operations thereof.
- 24. The data converter of claim 23, wherein the controller means is operable to control the writing and reading of the vector components to the storage means and operable to control the rotation of the vector components by the output rotation means and the input rotation means.
- 25. The data converter of claim 18, wherein the output rotation means rotates time parallel vector components in a direction opposite to the direction that the input rotation means rotates a set of corresponding vector components.
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This application is a continuation-in-part application of U.S. application entitled “SIMD PROCESSOR WITH SCALAR ALUS CAPABLE OF PROCESSING GRAPHICS VECTOR”, filed Jan. 29, 2003, Ser. No. 10/354,795, which application is hereby incorporated by reference into the instant application.
Continuation in Parts (1)
|
Number |
Date |
Country |
Parent |
10354795 |
Jan 2003 |
US |
Child |
10666083 |
Sep 2003 |
US |