Claims
- 1. A synchronous semiconductor memory device, comprising:
- a memory storing data;
- a clock signal buffer buffering an external clock signal to generate an internal clock signal;
- an input buffering responsive to said internal clock signal and buffering an external control signal to generate an internal control signal;
- an address buffer responsive to said internal clock signal and buffering an external address signal to generate an internal address signal;
- a mode register in which operation mode can be set designating a reading procedure of said data from said memory and a writing procedure of external data into said memory;
- a data reading circuit reading said data stored in said memory in response to said operation mode set in said mode register and in response to said internal clock signal and a read signal;
- a data writing circuit writing external data into said memory in response to said operation mode set in said mode register and in response to said internal clock signal and a write signal;
- a command decoder generating a mode set signal for setting said operation mode in said mode register in response to said internal control signal and generating said read signal and said write signal; and
- a non-volatile memory storing said mode set signal and said internal address signal and supplying said stored mode set signal and said stored internal address signal to said mode register.
REFERENCE TO RELATED APPLICATION
This Application is a continuation of International Application No. PCT/JP96/02781, whose international filing date is Sep. 26, 1996 the disclosures of which Application are incorporated by reference herein. The benefit of the filing and priority date of the International and Application is respectfully requested.
US Referenced Citations (8)
Foreign Referenced Citations (5)
Number |
Date |
Country |
63-206852 |
Aug 1988 |
JPX |
64-23548 |
Jan 1989 |
JPX |
3-35498 |
Feb 1991 |
JPX |
7-93970 |
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Continuations (1)
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Number |
Date |
Country |
Parent |
PCTJP9602781 |
Sep 1996 |
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