Patent Application
20100007363
The present invention relates generally to semiconductor wafer fabrication and more particularly but not exclusively to advanced process control methodologies for measuring in-line contact resistance in relation to oxide formations.
Demand for semiconductors, wafers, integrated circuits and semiconductor devices (i.e., collectively “semiconductors”) continues to rapidly increase. With the continued market demand, there remain market pressures to increase the number of wafers that can be processed, reduce the geometries of finished wafers and their associated chip footprints, and increase component counts in the reduced geometries. Being able to sustain and meet the market demands with a reliable and consistent offering is a challenge however, in part because wafer manufacture is an environment that is both process sensitive and equipment intensive. Similarly, since wafer fabrication is an expense process, determining as early as possible potential problems or limitations of a process are desired.
The fabrication of wafers (i.e., fabrication, fab, or fab environment) requires advanced processing equipment, unique toolings and extensive research efforts. Process tools (i.e., toolings) in these environments may often run in parallel or have multiple components to produce similar products (i.e., yields or outputs). Yet these same process tools, even when of the same manufacturer or source, may have unique variances in their individual performances which may create substantial differences in the quality and performance of fabricated wafers as well as the products comprising the wafers.
The LOCOS process is in effect an isolation scheme commonly used in metal oxide semiconductors (MOS) and complementary MOS (CMOS) technology in which a thick pad of thermally grown SiO2 separates adjacent devices such as P-channel MOS and N-channel MOS transistors. Local oxidation is often accomplished by using silicon nitride to prevent oxidation of silicon in predetermined areas, and silicon is typically implanted between a silicon nitride region to form channel stops.
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In a traditional furnace or furnace bank, there may exist more than one furnace tube in which a predetermined number of furnace tubes perform a similar process.
By example, the furnace bank of
In one deposition example, during the fabrication operation, a layer of insulating material and a layer of polycrystalline silicon are typically provided on a surface of a silicon wafer. In many operations, the layer of polycrystalline silicon includes a tunnel window, and the layer of insulating material is then removed from the surface of the silicon wafer within the window and below an edge of the layer of polycrystalline silicon adjacent to the window. Thereafter, the silicon is selectively deposited on the monocrystalline and polycrystalline silicon exposed in and adjacent to the window via various vapor deposition processes at various pressures or temperatures, in relation to a particular process. At a reduced pressure, such an operation may provide a reasonably smooth deposition layer of silicon having a generally homogeneous thickness.
Alternatively, a nitride layer or an oxynitride layer can be deposited onto a substrate utilizing known deposition methods such as thermal chemical vapor deposition (TCVD), that is carried out in the absence of a plasma, plasma-enhanced chemical vapor deposition (PECVD), or atomic layer deposition (ALD). Similarly, other types of deposition methods are envisioned by the present invention including but not limited to depositions involving metals (i.e., metallization) and barrier metals. Collectively, these methods of deposition are generally referenced and included herein as “deposition methods.”
However these deposition methods are directly affected by the presence of oxide on a Si wafer surface.
The presence of oxides, also known as native oxides, on a Si wafer surface is recognized as directly affecting the performance of a wafer, in part as the success or failure of the deposition step is impacted. In certain situations, the oxide present may affect the quality and deposition processes of polysilicon and dielectric thin films. In other situations, by example, the oxide present may cause incubation before film growth during low-pressure CVD. It will also be appreciated by those in skilled in the art that the presence of the oxide may also present further ramifications affecting the wafer, fabrication of the wafer, and performance of the wafer. However, attempts to suppress the native oxide growth during the surface cleaning and precisely control the interface (i.e., interfacial oxide) have not alleviated these concerns nor the formation of oxide.
For instance, in a fabrication environment, there may exist multiple deposition locations where a polysilicon, such as but not limited to polycrystalline silicon, is to be deposited on a silicon substrate surface of a wafer. Prior to the deposition process, the wafers are typically cleaned within the facility by a cleaning step that may include treating the wafer surface with dilute hydrofluoric acid, rinsing the wafer with ultra pure water, and drying the wafer. Often, there may be multiple cleaning process locations and depositing process locations within the facility, each process having identically calibrated equipment and each set of equipment for each process following a common cleaning or deposition regiment. However, even under these circumstances, following a deposition process, future examination of produced wafers from these processes may show that the polysilicon deposition results of one wafer versus another are sufficiently different. For instance grain sizes, grain distributions, and unwanted contamination at one location versus another may be present wafers having sufficient differences resulting in the success or failure of one produced set of wafers over another. In these situations, the additional or unexpected formation of oxide at one location versus the other location results in insufficient polysilicon deposition thereby producing wafers from which are substandard.
Unfortunately, the determination of a fabricated wafer having poor performance characteristics is typically determinable only at an end-of-line point, post-fabrication, or well after the fabrication is fully completed.
For example, following a wafer fabrication process, a wafer is typically situated for inspection and testing. The wait for an inspection and testing may be of a period in excess of two weeks after fabrication. Accordingly, an interfacial oxide layer formed in the wafer may be determined to be of an inconsistent or inaccurate thickness at such time, thereby rendering the produced wafer, and possibly the related batch of produced wafers, unusable well-after the wafer was produced.
Further, for instance, a logic bipolar transistor (LPT) is an example of a semiconductor device that has improved performance provided it has a low polysilicon to silicon substrate contact resistance (i.e., also used herein as contact resistivity). In other semiconductor devices, the contact resistance is also a determinate in the performance of the device. However, using traditional approaches, the contact resistance cannot be determined until well-after the fabrication production is completed resulting in a situation where a produced wafer and its production group may ultimately be discarded weeks after being completed and having taken up inventory space and planning.
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Typically a thickness of the interfacial oxide layer 420 may range from a few angstroms to over 20 angstroms, and the polysilicon deposition layer may be approximately one or more microns, depending on a process. However, the interfacial oxide may be not be uniformly consistent, may be inconsistent in thickness due to the process or anomalies encountered in a process, and the oxide grown during the cleaning process in a deposition method may also be unexpectedly affected. As the oxide may be inconsistent or may have grown at varied rates, the contact resistance of a produced wafer, which is directly proportionate to the presence of oxide at the end of the process (i.e., “end of the line” amount), may also be affected.
Accordingly, it is desired to determine the layers of the interfacial oxide and hence the contact resistance as soon as is possible following production operations with minimal interruption to the process schedule. The present invention, in accordance with its various implementations herein, addresses such needs.
In one implementation of the present invention, a method of determining contact resistance across and a number of interfacial oxide monolayers of a semiconductor wafer, comprising: measuring a voltage and a current across a wafer using a probe assembly, relating the measured voltage and current to a predetermined contact resistance association, and, determining the contact resistance value and the number of monolayers of the wafer, is set forth.
In another implementation, the present invention is a method of in-line resistance testing a wafer during fabrication to determine contact resistance and identify an interfacial oxide composition, comprising: measuring a voltage and a current across a wafer using an in-line multi-tipped probe being conductive with a surface of the wafer, determining (i) a contact resistance in relation to the measured voltage and current and (ii) a number of monolayers for the interfacial oxide composition in relation to the determined contact resistance, and, passing or failing the wafer in relation to the determining step.
In a further implementation, the present invention is a computer program product for passing or failing a wafer during fabrication in response to determined contact resistance, comprising, the computer program product comprising a computer-readable storage medium having computer-readable program code portions stored therein, the computer-readable program code portions comprising: a first executable portion having instructions providing a capability of: measuring a voltage and a current across a wafer via instructions to an in-line multi-tipped probe being conductive with a surface of the wafer, determining (i) a contact resistance in relation to the measured voltage and current and (ii) a number of monolayers for the interfacial oxide composition in relation to the determined contact resistance, and, signaling the passing or failing of the wafer in relation to the determining step.
The present invention relates generally to semiconductor wafer fabrication and more particularly but not exclusively to advanced process control methodologies for measuring in-line contact resistance in relation to oxide formations.
The following description is presented to enable one of ordinary skill in the art to make and use the invention and is provided in the context of a patent application and its requirements. Various modifications to the preferred embodiments and the generic principles and features described herein will be readily apparent to those skilled in the art. Thus, the present invention is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features described herein.
The four-point probe 500 having four probes (520) with pressure-contact tips (511, 512, 513 and 514) can be brought into electrical contact with a stationary wafer 510 produced through an in-line test following the deposition process. The probe is capable of measuring a current (I) and voltage (V) information of the substrate and thereby relating the measurements to thickness of oxides and contact resistance of the produced wafer, in accordance with an implementation of the present invention.
The current/voltage tips of the four-point probe may be arranged in a predetermined manner (e.g., in a line, pattern or other configuration) using an adapted probe tip to minimize physical damage to the wafer surface. In one particular example, in an implementation of the present invention, the probe consists of four equally spaced (525) metal tips, each with a finite radius and configured with a dampening device at 530 (i.e., springs) to minimize sample damage during probing. The four metal tips may also be configured with an auto-mechanical stage (optionally 530) which travels up and down during measurements. A high impedance current source is used to supply current through the outer two probes at 540. A voltmeter measures the voltage across the inner two probes at 550 to determine the contact resistance. In a further implementation, the typical probe spacing may approximate a distance of about 1 mm between each probe.
In the present invention, in one or more implementations, the probe is positioned at a point in the fabrication process (i.e., oxidation cycle) which follows precleaning and deposition, such that it is “in-line” with the fabrication process. By example a cleaning process may include a standard wet clean operation having sulfuric acid, hydrofluoric acid and a spin rinse dryer (SRD), though other variations are also envisioned. The probe is capable of measuring the V and I across a wafer at this stage of the fabrication so as to determine whether the polysilicon layer of the wafer is monolithic or polylithic as a result of manufacture. Typically, in one or more implementations of the present invention, a monolayer (i.e., monolithic) of polysilicon is approximately equal to or less than one micron in dimension, whereas a wafer having more than one monolayer or being multilayered will have a thickness is excess of this measurement. Since the contact resistance across the polysilicon is determined in relation to the thickness of the polysilicon layer, measurements by the probe of V/I for a particular wafer may then result in determining the wafer as being of a monolayer or multilayer of polysilicon based upon predetermined V/I values in relation to contact resistivity values. In a preferred embodiment, where the measured V/I by the probe of a wafer is approximately equal to or less than 50 ohm centimeters (Ωcm) then the wafer has less than one single monolayer of polysilicon as an interfacial oxide layer. In a further preferred embodiment, where the measured V/I by the probe of a wafer is approximately greater than 1000 ohm centimeters (Ωcm) then the wafer has two or more monolayers of polysilicon in the interfacial oxide layer.
In operation, the present invention in one or more implementations, is positioned in-line to the fabrication process such that the probe tips are in conductive arrangement with a polysilicon layer of the wafer to be tested. A high impedance current source is used to supply current through the outer two probes tips of the probe, and a voltmeter measures the voltage across the inner two probes tips to determine the sample resistivity of the wafer. The wafer resistivity is determined as V/I for the purposes of the present invention. In relation to the resulting V/I determination, where the measured V/I by the probe of a wafer is approximately equal to or less than 50 ohm centimeters (Ωcm) then it is determined that wafer has less than one single monolayer of polysilicon as an interfacial oxide layer. In a further preferred embodiment, where the measured V/I by the probe of a wafer is determined as being approximately greater than 1000 ohm centimeters (Ωcm) then the wafer is determined as having two or more monolayers of polysilicon in the interfacial oxide layer.
The present invention is further advantageous over traditional methods as no additional modifications or change-outs are required in the functional or operative nature of the fab process to which it impacts. Time savings, costs savings, inventory and scrap savings are also readily anticipated by the present invention in an operational environment. A further advantage is that the present invention does not require the need to “profile” tooling such as furnaces, contradistinctive to the traditional approach.
As used herein it will be understood that the performance of a wafer or memory cell may be impacted by one or more, or any of: film thickness, stress and dopant percentages, oxide thickness, dielectric constants of the floating gate electrode and layers of the ONO layer, physical attributes, footprint, shape, formation details, thickness, conductivity, uniformity, capacitance, band voltage, resistance, and growth impacts dues to temperature and/or pressure during the deposition process, and other characteristics which may affect performance.
As used herein, it is envisioned that the present invention in one or more implementations may be hardware, software, firmware, or combinations thereof, in its composition and operation, and may therefore further comprise software, instructional code, other applications, and be a computer program product.
Various implementations of a wafer process and methods for fabricating the wafer have been described. Nevertheless, one of ordinary skill in the art will readily recognize that various modifications may be made to the implementations, and any variations would be within the spirit and scope of the present invention. For example, the above-described process flow is described with reference to a particular ordering of process actions. However, the ordering of many of the described process actions may be changed without affecting the scope or operation of the invention. Accordingly, many modifications may be made by one of ordinary skill in the art without departing from the spirit and scope of the following claims.
