Claims
- 1. An apparatus for verifying a property associated with a target circuit, comprising:
a partitioned ordered binary decision diagram (POBDD) data structure operable to receive information associated with a target circuit, the information identifying a property within the target circuit to be verified, the POBDD data structure operable to execute one or more operations in order to generate a set of transition relations for performing a reachability analysis associated with the target circuit, the POBDD data structure operable to partition an image associated with the target circuit into a plurality of leaves that may each represent a subset of a final image to be generated by the POBDD data structure, wherein the POBDD data structure is operable to compute an analysis for one or more of the leaves using a selected one or both of conjunction and quantification operations separately.
- 2. The apparatus of claim 1, further comprising:
an algorithm element coupled to the POBDD data structure, wherein the algorithm element includes one or more algorithms that may be executed in order to verify the property included within the target circuit.
- 3. The apparatus of claim 1, wherein the partitioning is executed based on a selected one of primary inputs, state variables, and local decomposition variables associated with the target circuit.
- 4. The apparatus of claim 1, wherein one or more of the leaves are computed separately using a separate variable order.
- 5. The apparatus of claim 1, further comprising:
a plurality of managers, wherein one or more of the managers are operable to analyze a selected one of the leaves, and wherein one or more of the leaves may be combined into a single BDD.
- 6. The apparatus of claim 1, wherein one or more of the leaves are transferred after the computation has been completed.
- 7. The apparatus of claim 1, wherein the information includes a time interval in which the POBDD data structure executes verification in order to generate a set of states at a designated depth.
- 8. The apparatus of claim 1, wherein the POBDD data structure is operable to produce a resultant that reflects an integrity parameter associated with the property being verified, the integrity parameter identifying whether one or more errors are present in the target circuit.
- 9. A method for verifying a property associated with a target circuit, comprising:
receiving information associated with a target circuit, the information identifying a property within the target circuit to be verified; executing one or more operations in order to generate a set of transition relations for performing a reachability analysis associated with the target circuit; partitioning an image associated with the target circuit into a plurality of leaves that may each represent a subset of a final image to be generated by a partitioned ordered binary decision diagram (POBDD) data structure; and computing an analysis of one or more of the leaves using a selected one or both of conjunction and quantification operations separately.
- 10. The method of claim 9, further comprising:
executing one or more algorithms in order to verify the property included within the target circuit.
- 11. The method of claim 9, wherein the partitioning is executed based on a selected one of primary inputs, state variables, and local decomposition variables associated with the target circuit.
- 12. The method of claim 9, wherein one or more of the leaves are computed separately using a separate variable order.
- 13. The method of claim 9, further comprising:
transferring one or more of the leaves after the computation has been completed.
- 14. The method of claim 9, further comprising:
producing a resultant that reflects an integrity parameter associated with the property being verified, the integrity parameter identifying whether one or more errors are present in the target circuit.
- 15. Software for verifying a property associated with a target circuit, the software being embodied in a computer readable medium and including computer code such that when executed is operable to:
receive information associated with a target circuit, the information identifying a property within the target circuit to be verified; execute one or more operations in order to generate a set of transition relations for performing a reachability analysis associated with the target circuit; partition an image associated with the target circuit into a plurality of leaves that may each represent a subset of a final image to be generated a partitioned ordered binary decision diagram (POBDD) data structure; and compute an analysis of one or more of the leaves using a selected one or both of conjunction and quantification operations separately.
- 16. The medium of claim 15, wherein the code is further operable to:
execute one or more algorithms in order to verify the property included within the target circuit.
- 17. The medium of claim 15, wherein the partitioning is executed based on a selected one of primary inputs, state variables, and local decomposition variables associated with the target circuit.
- 18. The medium of claim 15, wherein one or more of the leaves are computed separately using a separate variable order.
- 19. The medium of claim 15, wherein the code is further operable to:
transfer one or more of the leaves after the computation has been completed.
- 20. The medium of claim 15, wherein the code is further operable to:
produce a resultant that reflects an integrity parameter associated with the property being verified, the integrity parameter identifying whether one or more errors are present in the target circuit.
- 21. A system for verifying a property associated with a target circuit, comprising:
means for receiving information associated with a target circuit, the information identifying a property within the target circuit to be verified; means for executing one or more operations in order to generate a set of transition relations for performing a reachability analysis associated with the target circuit; means for partitioning an image associated with the target circuit into a plurality of leaves that may each represent a subset of a final image to be generated by a partitioned ordered binary decision diagram (POBDD) data structure; and means for computing an analysis of one or more of the leaves using a selected one or both of conjunction and quantification operations separately.
- 22. The system of claim 21, further comprising:
means for executing one or more algorithms in order to verify the property included within the target circuit.
- 23. The system of claim 21, further comprising:
means for transferring one or more of the leaves after the computation has been completed.
- 24. The system of claim 21, further comprising:
means for producing a resultant that reflects an integrity parameter associated with the property being verified, the integrity parameter identifying whether one or more errors are present in the target circuit.
RELATED APPLICATIONS
[0001] This application claims priority under 35 U.S.C. §119 of provisional patent application serial No. 60/426207 entitled: “Verifying a Circuit Using One or More Partitioned Ordered Binary Decision Diagrams (POBDDs)” filed Nov. 13, 2002.
Provisional Applications (1)
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Number |
Date |
Country |
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60426207 |
Nov 2002 |
US |