Patent Application
20130252350
Defect inspection to detect manufacturing defects of semiconductor wafers has become a standard part of micro-fabrication manufacturing processes. To set up the inspection process, typical systems require the user to manually define care areas on the die of the wafer. Care areas are the areas where the user is interested in inspecting for defects of interest (DOI), such as the array areas.
The care area generation process is generally very tedious and error-prone. For example, a physical wafer is required to be loaded into an inspection tool. The user then analyzes the design pattern on the wafer and manually defines the inspection care areas. In order to maximize inspection sensitivity, it is common to have more than 10,000 care areas defined in, for example, a static random access memory (SRAM) region, to allow for multiple thresholds. As a result, the user may spend numerous hours to define care areas. Moreover, it is difficult to suppress the nuisance defect while maintaining DOI detection.
As such, what is needed is an improved technique for identifying inspection care areas on wafers.
A method of generating care areas is disclosed. An artwork file of a layout of a product is provided and a cell tree of the layout is formed. The cell tree includes a plurality of cells of the layout arranged in a hierarchical order. The method also includes defining care areas in the artwork file of the layout.
In another embodiment, a method of forming a device is presented. The method includes providing a wafer having a plurality of devices formed thereon. It also includes providing an inspection tool for inspecting the wafer for defects. The inspection tool contains information of care areas for inspection. The care areas are determined by forming a cell tree of cells in a hierarchical order of a layout of the device representing the plurality of devices from an artwork file of the device. The care areas on the wafer are inspected.
In yet another embodiment, a computer program storage medium is disclosed. The computer program storage medium includes a program with instructions to determine care areas of a layout of a device. The instructions include reading an artwork file containing the layout of the device, creating a hierarchical cell tree which is a logical representation of the cells of the device, and identifying the care areas of the device from the cell tree.
These and other objects, along with advantages and features of the present invention herein disclosed, will become apparent through reference to the following description and the accompanying drawings. Furthermore, it is to be understood that the features of the various embodiments described herein are not mutually exclusive and can exist in various combinations and permutations.
In the drawings, like reference characters generally refer to the same parts throughout the different views. Also, the drawings are not necessarily to scale, emphasis instead generally being placed upon illustrating the principles of the invention. In the following description, various embodiments of the present invention are described with reference to the following drawings, in which:
a-b show an embodiment of a process for generating care areas;
c shows a graphical illustration of a process of
a-b illustrate care areas in a product artwork file; and
The following description sets forth techniques that facilitate automatic generation of care areas for defect inspection. Embodiments relate to care areas for defect inspection of wafers used in the fabrication process of semiconductor devices.
The wafer includes an active surface 111 on which devices 115 are formed. A plurality of devices may be formed on the wafer in parallel. The devices are subsequently singulated into individual dies, assembled and tested. In other embodiments, the wafer may include a single device.
The fabrication of devices, such as integrated circuits (ICs), involves the formation of features on a substrate that make up circuit components, such as transistors, resistors and capacitors. The devices are interconnected, enabling the device to perform the desired functions. Interconnections are formed by forming contacts and conductive lines in a dielectric layer using, for example, damascene techniques. Devices may include a plurality of interconnect levels.
The various features and interconnections are strategically placed on the device to minimize the use of space and/or optimize performance. The placement of various features and interconnections is referred to as a product or device layout.
The product layout is contained in an artwork file. The artwork file contains 3-dimensional information of the product layer. For example, the various layers of the product are contained in the artwork file. The artwork file can be various types of artwork file. The artwork file, for example, can be a GDSII, LEF, DEG, OASIS or CIF type of file. Other types of artwork file may also be useful.
a illustrates an exemplary method 300 of generating care areas of a device. In one embodiment, the care areas are generated from design data. “Design data” generally refers to data derived or contained in an artwork file representing a layout of the device of interest. This methodological implementation may be performed in software, hardware, or a combination thereof. For ease of understanding, the method steps are delineated as separate steps; however, these separately delineated steps should not be construed as necessarily order-dependent in their performance or as distinct steps.
At step 305, an artwork file containing a layout of the product is obtained. The artwork file, for example, may be in GDSII format. Providing an artwork file in other formats, such as OASIS, may also be useful. GDSII and OASIS are binary file formats. In other embodiments, the artwork file may be in a predefined text format or a combination of formats. For example, the artwork file may be in GDSII and OASIS.
The artwork file contains design data of a layout of the product in hierarchical form which can be used to reconstruct the artwork. For example, the design data is a hierarchy of structures containing elements situated on layers. The design data is contained in a library or record of cells. Cells may contain geometrical objects, such as polygons, paths and other cells. Objects in a cell are assigned to layers of the layout.
The design data is input into a processor for processing at step 310. The processor, in one embodiment, flattens the design data to a 2-dimensional layout with information of the various layers provided as a single layer. The design data is processed to form a cell tree. For example, the processor constructs a database of a logical tree structure of cells. The cell tree corresponds to a logical presentation of the layout.
The cell at the highest level of the cell tree is referred to as the TOPCELL. The TOPCELL, for example, corresponds to the whole product. The TOPCELL may have numerous branches. A branch may have any number of levels. For example, a branch may have three levels, including the top level. Providing a branch with other number of levels may also be useful. Additionally, branches in the tree need not have the same number of levels. For example, some branches may have three levels while others may have four levels. A cell which has a lower level is referred to a PARENTCELL with respect to the cells at the higher level. The cell at a lower level of a PARENTCELL is referred to as a LEAFCELL. A PARENTCELL should have at least two LEAFCELLs or two branches. The cells at the lowest level of the cell tree are LEAFCELLs of the cell tree. Other configurations of the cell tree may also be useful.
In one embodiment, the design data is processed using electronic design automation (EDA) software. The EDA software, for example, may include Mentor Graphics Calibre, Synopsys Hercules, or Cadence Assura. Using other types of EDA software may also be useful. A script may be created to instruct the EDA software to create the cell tree.
At step 315, the care area of the product layout is defined or generated. In one embodiment, the care area is the combined boundaries of the LEAFCELLs in the TOPCELL. For example, the care area is defined as a polygon or polygons of combined LEAFCELL boundaries in the TOPCELL. A boundary of a LEAFCELL is represented by coordinates indicating the spatial location of the boundary in the layout. The spaces between the LEAFCELLs represent the don't care area. The LEAFCELLs may be LEAFCELLs of the TOPCELLL. In other embodiments, the LEAFCELLs may be LEAFCELLs of PARENTCELLs disposed at an intermediate level of the cell tree. In some embodiments, the care area is a combination of LEAFCELLs of the TOPCELL and PARENTCELLs at one or more intermediate levels of the cell tree. In one embodiment, a scanline technique is employed to determine boundaries of LEAFCELLs for combining to define the care area. Alternatively, a sorting technique can be used to trace the boundaries of the LEAFCELLs for combining to define the care area. Such techniques, for example, are described in Lauther, “An O (N log N) Algorithm For Boolean Mask Operations”, IEEE 18th Design Automation Conf., pages 555-562. 1981; and Carlson et al., “A Scanline Data Structure Processor for VLSI Geometry Checking”, IEEE Transactions on Computer-Aided Design, vol. CAD-6, No. 5, September 1987, which are all incorporated by reference for all purposes.
The process continues to step 320 to determine whether the x-y coordinates of the artwork need to be translated. For example, the x-y coordinates of the artwork may have different orientations from the layout on the wafer. In such case, the coordinates need to be rotated to match the layout on the wafer. Additionally, coordinates may need to be shifted to match different die locations of the wafer. At step 325, the care areas are generated in the artwork file format.
As described, the generation of care areas is achieved without the existence of a physical wafer. This enables care area analysis to be performed once the artwork is completed, expediting the development and manufacturing process. Furthermore, the present process can significantly reduce the time needed for care area definition. Additionally, the number of care areas can be adjusted to achieve the desired sensitivity of the area of interest and nuisance noise. For example, larger number of care areas increases sensitivity of the area of interest and reduces the nuisance generated by open regions. The number of care areas in the TOPCELL can be increased or decreased, depending on the level that the LEAFCELLs are combined. For example, there would be a larger number of care areas when LEAFCELLs of intermediate PARENTCELLs are used as compared to LEAFCELLs of the TOPCELL.
b shows an embodiment of a process 310 for forming a hierarchical cell tree. At step 350, the TOPCELL cell boundary is determined. At step 355, LEAFCELLs of a PARENTCELL are identified. For the first iteration (e.g., x=1), the PARENTCELL is the TOPCELL, encompassing the product layout. Since there is only one PARENTCELL for the first iteration, there would be no more PARENTCELLs to analyze at step 360. The process then continues to 365 to determine if there are more tree levels to analyze. If there are, the process returns to step 355 and repeats until no more tree levels are left to analyze at step 365. When no more tree levels are left to analyze, the process terminates at step 370 with the completion of the cell tree.
c is a graphical illustration of an exemplary process 310, as depicted in
The process or processes of
As shown, the top level cell (x=1) includes two second level (x=2) LEAFCELLs. One of the second level cells is a PARENTCELL comprising two third level (x=3) cells while the other one does not have any third level cells. As for the third level cells, one is a PARENTCELL with two fourth level (x=4) LEAFCELLs while the other does not have any. The hierarchical cell tree continues to the lowest level (x=n). Other configurations of hierarchical cell trees are also useful, and may depend on the product layout.
a-b illustrate examples of care area generation. Referring to
b shows a product layout 500 as shown in
The output of the format conversion is a compatible file with care and don't care areas. The care and don't care areas, for example, are in the form of rectangular polygons. Providing care and don't care areas in other shapes may also be useful. For example, the care and don't care areas may be in non-rectangular polygons. The don't care areas may be the areas between the care areas. At step 615, the converted file is input into the inspection tool. For example, the file can be loaded into the inspection tool using conventional techniques, such as via network or via a storage medium on which the file is stored.
With the care and don't care areas defined in the inspection tool, the inspection parameters may be set. The inspection recipe is defined for the inspection tool at step 620. The inspection tool is programmed with the inspection recipe. In one embodiment, the inspection recipe includes parameters or settings from a best known method inspection recipe. The best known method inspection recipe, for example, is used for the initial scan. Inspection recipe parameters, for example, are threshold parameters used for the initial scan of a wafer which contains devices of the artwork file. For the initial scan, the threshold values are generally set low to capture both defects of interest and nuisance.
The inspection tool, at step 625, inspects a wafer on which devices are formed. The devices, for example, are devices associated with the artwork file. The inspection is based on the care area definition and the initial inspection recipe provided. Based on the scan results, the inspection recipe may be adjusted at step 630. For example, the inspection recipe may be modified to improve capturing defects of interst while truncating nuisances. The steps of 625 and 630 may be repeated until the desired defect of interest regions are localized and high nuisance regions are masked off.
If no weak points are detected by the final scan, the mask set used to form the devices on the wafer are qualified and used in production to form devices. In the event that weak points are detected by the final scan, the mask set used to form the devices on the wafer may be repaired or retrofitted until no weak points are detected. Wafers using the qualified mask set are produced. The devices on the wafer are separated into individual devices.
By providing an artwork file with care areas, inspection recipes can be more easily formed. Furthermore, critical and non-critical areas can be quickly identified through analysis of the artwork file. This enables inspection recipes to be more effectively tailored to produce more accurate inspection results.
Although the one or more above-described implementations have been described in language specific to structural features and/or methodological steps, it is to be understood that other implementations may be practiced without the specific features or steps described. Rather, the specific features and steps are disclosed as preferred forms of one or more implementations.
