Patent Application
20090113182
1. Technical Field
The present invention relates in general to the field of data processing systems and in particular, to the field of processing data within data processing systems. Still more particularly, the present invention relates to efficiently processing data within data processing systems.
2. Description of the Related Art
Early microprocessors executed only one instruction at a time and executed instructions in an order determined by the compiled machine-language program running on the microprocessor. Such microprocessors are known as “sequential” microprocessors. Various techniques, such as pipelining, superscaling, and speculative instruction execution, are utilized to improve the performance of sequential microprocessors. Pipelining breaks the execution of instructions into multiple stages, in which each stage corresponds to a particular execution step. Pipelined designs enable new instructions to begin executing before previous instructions are finished, thereby increasing the rate at which instructions can be executed.
“Superscalar” microprocessors typically include multiple pipelines and can process instructions in parallel using two or more instruction execution pipelines in order to execute multiple instructions per microprocessor clock cycle. Parallel processing requires that instructions can be dispatched for execution at a sufficient rate. However, the execution rate of microprocessors has typically outpaced the ability of memory devices and data buses to supply instructions to the microprocessors. Therefore, conventional microprocessors utilize one or more levels of on-chip cache memory to increase memory access rates.
Conventional microprocessors utilize speculative instruction execution to address pipeline stalls by enabling a second instruction that is data dependent on a first instruction to enter an execution pipeline before the first instruction has passed completely through the execution pipeline. Thus, in speculative instruction microprocessors, the data dependent second instruction, which is often referred to as a “consumer” instruction, depends on the first instruction, which is referred to as a “producer” instruction.
In microprocessors that utilize speculative instruction execution, there is a delay between the decision to issue an instruction and the actual execution of the instruction. Thus, in the case of load instructions, there may be a significant delay between the issue of a load instruction and the corresponding data fetch from cache memory. A consumer instruction, dependent on a delayed load producer instruction, may be issued before confirmation by the cache system that the load data required is available in the cache. When the required data is not found in the cache, dependent consumer instructions can execute and access incorrect data.
The present invention includes a system and method for issuing load-dependent instructions from an issue queue in a processing unit in a data processing system. A LSU determines if a load request from a load instruction missed a first level in a memory hierarchy. In response to determining the load request missed a first level in a memory hierarchy, a LMQ allocates a load-miss queue entry corresponding to the load instruction. The LMQ determines if at least one dispatched instruction dependent on the load request is located in at least one issue queue in said processing unit. In response to determining at least one dispatched instruction dependent on the load request is located in at least one issue queue in the processing unit, the LMQ associates the load-miss queue entry with at least one dispatch instruction. A memory manager retrieves data associated with the load request into the first level in said memory hierarchy from another level within the memory hierarchy. In response to retrieving data associated with the load request, the LMQ selects at least one dispatched instruction dependent on said load request for issue from at least one issue queue. In response to selecting, the issue queue issues the dispatched instruction dependent on the load request on a next processing unit cycle. The execution unit executes the dispatched instruction. The execution unit outputs a result of executing the dispatched instruction.
The above, as well as additional objectives, features, and advantages of the present invention, will become apparent in the following detailed written description.
The invention itself, as well as a preferred mode of use, further objects, and advantages thereof, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein:
With reference now to
Instructions are fetched and ordered for processing by instruction sequencing logic 13 within processor 10. In the depicted embodiment, instruction sequencing logic 13 includes an instruction fetch address register (IFAR) 30 that contains an effective address (EA) indicating a cache line of instructions to be fetched from L1 I-cache 18 for processing. During each cycle, a new instruction fetch address may be loaded into IFAR 30 from one of at least three sources: branch prediction unit (BPU) 36, which provides speculative target path addresses resulting from the prediction of conditional branch instructions, global completion table (GCT) 38, which provides sequential path addresses, and branch execution unit (BEU) 92, which provides non-speculative addresses resulting from the resolution of predicted conditional branch instructions. The effective address loaded into IFAR 30 is selected from among the addresses provided by the multiple sources according to a prioritization scheme, which may take into account, for example, the relative priorities of the sources presenting addresses for selection in a given cycle and the age of any outstanding unresolved conditional branch instructions.
If hit/miss logic 22 determines, after translation of the EA contained in IFAR 30 by effective-to-real address translation (ERAT) 32 and lookup of the real address (RA) in I-cache directory 34, that the cache line of instructions corresponding to the EA in IFAR 30 does not reside in L1 I-cache 18, then hit/miss logic 22 provides the RA to L2 cache 16 as a request address via I-cache request bus 24. Such request addresses may also be generated by prefetch logic within L2 cache 16 or elsewhere within processor 10 based upon recent access patterns. In response to a request address, L2 cache 16 outputs a cache line of instructions, which are loaded into prefetch buffer (PB) 28 and L1 I-cache 18 via I-cache reload bus 26, possibly after passing through predecode logic (not illustrated).
Once the cache line specified by the EA in IFAR 30 resides in L1 cache 18, L1 I-cache 18 outputs the cache line to both branch prediction unit (BPU) 36 and to instruction fetch buffer (IFB) 40. BPU 36 scans the cache line of instructions for branch instructions and predicts the outcome of conditional branch instructions, if any. Following a branch prediction, BPU 36 finishes a speculative instruction fetch address to IFAR 30, as discussed above, and passes the prediction to branch instruction queue 64 so that the accuracy of the prediction can be determined when the conditional branch instruction is subsequently resolved by branch execution unit 92.
IFB 40 temporarily buffers the cache line of instructions received from L1 I-cache 18 until the cache line of instructions can be translated by instruction translation unit (ITU) 42. In the illustrated embodiment of processor 10, ITU 42 translates instructions from user instruction set architecture (UISA) instructions (e.g., PowerPC® instructions) into a possibly different number of internal ISA (IISA) instructions that are directly executable by the execution units of processor 10. Such translation may be performed, for example, by reference to microcode stored in a read-only memory (ROM) template. In at least some embodiments, the UISA-to-IISA translation results in a different number of IISA instructions than UISA instructions and/or IISA instructions of different lengths than corresponding UISA instructions. The resultant IISA instructions are then assigned by global completion table 38 to an instruction group, the members of which are permitted to be executed out-of-order with respect to one another. Global completion table 38 tracks each instruction group for which execution has yet to be completed by at least one associated EA, which is preferably the EA of the oldest instruction in the instruction group.
Following UISA-to-IISA instruction translation, instructions are dispatched in-order to one of latches 44, 46, 48, 50, and 51 according to instruction type. That is, branch instructions and other condition register (CR) modifying instructions are dispatched to latch 44, fixed-point and load-store instructions are dispatched to either of latches 46 and 48, floating-point instructions are dispatched to latch 50, and vector instructions are dispatched to latch 57. Each instruction requiring a rename register for temporarily storing execution results is then assigned one or more registers within a register file by the appropriate one of CR mapper 53, link and count register (LCR) mapper 55, exception register (XER) mapper 57, general-purpose register (GPR) mapper 59, floating-point register (FPR) mapper 61, and vector register (VR) mapper 65. According to the illustrative embodiment, register mapping may be performed by a simplified register file mapper, a reorder buffer (ROB), or other similar devices known to those skilled in the art. Register file mapping can thus be performed at instruction issue time or close to result write-back time, thereby reducing the lifetimes of allocated renames and increasing the efficiency of rename usage.
Instruction sequencing logic 13 tracks the allocation of register resource to each instruction using the appropriate one of CR last definition (DEF) table 52, LCR last DEF table 54, XER last DEF table 56, GPR last DEF table 58, FPR last DEF table 60, and VR last DEF table 63.
Data processing system 8 also includes flush recovery array 43, which is coupled to next DEF tables 41. Flush recovery array 43 enables instruction sequencing logic 13 to utilize next DEF tables 41 to track instruction data dependencies and perform flush recovery operations.
After latches 44, 46, 48, 50, and 51, the dispatched instructions are temporarily placed in an appropriate one of CR issue queue (CRIQ) 62, branch issue queue (BIQ) 64, fixed-point issue queues (FXIQs) 66 and 68, floating-point issue queues (FPIQs) 70 and 72, and VR issue queue (VRIQ) 73. From issue queues 62, 64, 66, 68, 70, 72, and 73, instructions can be issued opportunistically (i.e., possibly out-of-order) to the execution units of processor 10 for execution. In some embodiments, the instructions are also maintained in issue queues 62-73 until execution of the instructions is complete and the result data, if any, are written back, in case any of the instructions needs to be reissued.
As illustrated, the execution units of processor 10 include a CR unit (CRU) 90 for executing CR-modifying instructions, a branch execution unit (BEU) 92 for executing branch instructions, two fixed-point units (FXUs) 94 and 100 for executing fixed-point instructions, two load-store units (LSUs) 96 and 98 for executing load and store instructions, two floating-point units (FPUs) 102 and 104 for executing floating-point instructions, and vector execution unit (VEU) 105 for executing vector instructions. Each of execution units 90-105 is preferably implemented as an execution pipeline having a number of pipeline stages.
During execution within one of execution units 90-105, an instruction receives operands, if any, from one or more architected and/or rename registers within a register file coupled to the execution unit. When executing CR-modifying or CR-dependent instructions, CRU 90 and BEU 92 access the CR register file 80, which in a preferred embodiment contains a CR and a number of CR rename registers that each comprise a number of distinct fields formed of one or more bits. Among these fields are LT, GT, and EQ fields that respectively indicate if a value (typically the result or operand of an instruction) is less than zero, greater than zero, or equal to zero. Link and count register (LCR) register file 82 contains a count register (CTR), a link register (LR) and rename registers of each, by which BEU 92 may also resolve conditional branches to obtain a path address. Similarly, when executing vector instructions, VRU 105 accesses the VR register file 89, which in a preferred embodiment contains multiple VRs and a number of VR rename registers. General-purpose register files (GPRs) 84 and 86, which are synchronized, duplicate register files, store fixed-point and integer values accessed and produced by FXUs 94 and 100 and LSUs 96 and 98. Floating-point register file (FPR) 88, which like GPRs 84 and 86 may also be implemented as duplicate sets of synchronized registers, contains floating-point values that result from the execution of floating-point instructions by FPUs 102 and 104 and floating-point load instructions by LSUs 96 and 98.
After an execution unit finishes execution of an instruction, the execution notifies GCT 38, which schedules completion of instructions in program order. To complete an instruction executed by one of CRU 90, FXUs 94 and 100, FPUs 102 and 104, or VEU 105, GCT 38 signals the appropriate last DEF table. The instruction is then removed from the issue queue, and once all instructions within its instruction group have completed, is removed from GCT 38. Other types of instructions, however, are completed differently.
When BEU 92 resolves a conditional branch instruction and determines the path address of the execution path that should be taken, the path address is compared against the speculative path address predicted by BPU 36. If the path addresses match, BPU 36 updates its prediction facilities, if necessary. If, however, the calculated path address does not match the predicted path address, BEU 92 supplies the correct path address to IFAR 30, and BPU 36 updates its prediction facilities, as described further below. In either event, the branch instruction can then be removed from BIQ 64, and when all other instructions within the same instruction group have completed, from GCT 38.
Following execution of a load instruction (including a load-reserve instruction), the effective address computed by executing the load instruction is translated to a real address by a data ERAT (not illustrated) and then provided to L1 D-cache 20 as a request address. At this point, the load operation is removed from FXIQ 66 or 68 and placed in load data queue (LDQ) 114 until the indicated load is performed. If the request address misses in L1 D-cache 20, the request address is placed in load miss queue (LMQ) 116, from which the requested data is retrieved from L2 cache 16, and failing that, from another processor 10 or from system memory 12. LMQ 116 is discussed herein in more detail in conjunction with
Store instructions (including store-conditional instructions) are similarly completed utilizing a store queue (STQ) 110 into which effective addresses for stores are loaded following execution of the store instructions. From STQ 110, data can be stored into either or both of L1 D-cache 20 and L2 cache 16, following effective-to-real translation of the target address.
Those will skill in the art will appreciate that in a modern pipelined, superscalar microprocessor, it is desirable to minimize pipeline stalls such as pipeline “bubbles” (i.e., non-consecutive instruction sequences where microprocessor facilities are idle because no instruction was issued for processing at some point in the instruction stream). One way to address pipeline stalls is to optimize the operating of the issue queue to ensure that instructions are issued is as much of a continuous stream as possible.
In a non-shifting issue queue, one timing critical sequence includes: (1) searching for instructions with all of their source operands “ready”; (2) determining which one of the “ready” instructions is the oldest “ready” instruction; and (3) issuing the instruction that satisfies conditions (1) and (2). Once an instruction is issued, a broadcast of a data tag to the issue queue occurs to identify and wakeup any dependent instructions resident in the issue queue. The first instruction is a “producer” instruction while the dependent instructions are “consumer” instructions, as previously discussed. As processing speeds and demands increase, steps (1) and (2) above need to be refined.
One method utilized to refine steps (1) and (2) in a non-shifting issue queue includes determining the instruction that will issue one cycle before that instruction is actually issued. Utilizing this method, an entire cycle may be utilized to evaluate all “ready” instructions to find the oldest “ready” instruction.
For load producer instructions that miss the L1 data cache, the scheduling of the issue of consumer instructions dependent (hereinafter referred to as “load-dependent instructions”) on those load producer instructions is a challenge, since the issue of the load-dependent instructions is predicated on when data is returned from other levels of the memory hierarchy (e.g., L2 cache, system memory, hard disk drive, etc.). Typically, a data tag for the load data is broadcast to the issue queue just in time to “wakeup” load-dependent instructions to issue during the following cycle. However, those with skill in the art will appreciate that in the abovementioned non-shifting issue queue, the load-dependent instructions must be marked as “ready” a cycle earlier than the actual time of issue. Therefore, the normal method of broadcasting the data tag against the issue queue will issue any load-dependent instruction a cycle later than normal in a non-shifting issue queue. The later issuance of load-dependent instructions negatively impacts performance, since load-dependent instructions often lie in a critical path of code streams.
According to an embodiment of the present invention, as load instructions are determined to miss the L1 data cache, a unique entry corresponding to the missed load instruction is placed in (LMQ) 116.
Referring back to
If the load missed L1 D-cache 20, the process proceeds to step 308, which depicts LSU 96 or 98 sending the load instruction to LMQ 118 and allocating an entry within LMQ 118 corresponding to the load instruction. The process continues to step 310, which illustrates LSU 96 or 98 setting RTAG field 202 and TYPE field 210 to indicate the physical address of where the requested load data will be stored and the data type of the requested load data, respectively.
The process continues to step 312, which depicts LMQ 118 determining if the load instruction has any load-dependent instructions that are already present any of the issue queues. If not, the process continues to step 316, which illustrates LMQ 118 determining if any dispatched instructions from latches 44, 46, 48, 50, and 51 are load dependent on the current load instruction. If not, the process continues to step 318, which depicts LMQ 118 continuing to examine the dispatched instructions to determine if any of the dispatched instructions are load dependent on the current load instruction. The process returns to step 316. Returning to step 316, if there are dispatched instructions that are load dependent on the current load instruction, the process proceeds to step 314.
Returning to step 312, if the current load instruction has at least one load-dependent instruction that is already present in any of the issue queues, the process continues to step 314, which illustrates LMQ 116 setting Dep QTAG field 204, and DQv field 206 corresponding to the load-dependent instruction. The process continues to step 320, which depicts LMQ 116 determining if the instruction referred to by Dep QTAG field 204 in the LMQ 116 entry corresponding to the present load instruction has been flushed. Some reasons why an instruction may be flushed include branch prediction errors, instructions that take an exception or interrupt, and the like. If not, the process continues to step 324. If the instruction has been flushed, the process proceeds to step 322, which illustrates LMQ 116 clearing DQv field 206 corresponding to the current load instruction, which indicates that the load-dependent instruction has been flushed from LMQ 116.
According to a first embodiment of the present invention, selecting a dependent QTAG (e.g., Dep QTAG field 204) for issue the following cycle will be acceptable most of the time, since the load dependent instructions' other sources would also likely be ready. If the dependent QTAG is selected for issue the following cycle, but the dependent QTAG has a different source that is not ready for issue, then the instruction corresponding to the dependent QTAG cannot be issued as well. This effectively leads to a wasted issue cycle, since the normal age-based mechanism may have selected an instruction to issue. Essentially, this embodiment of the present invention speculates that other sources of the consumer will be ready when selected for issue by the dependent QTAG.
According to a second embodiment of the present invention, LMQ 116 may only set the bit in DQv field 206 if all of the other sources in the load-dependent instruction are ready. This removes speculation in the first embodiment, but also limits the potential number of cases where a fast wakeup can occur.
According to a third embodiment of the present invention, LMQ 116 gives priority (in selecting the next issue QTAG pointer) to the normal age-based issue selection, over the fast dependent QTAG wakeup. The normal age-based selection is usually non-speculative, so if no instruction is found to be ready with this selection, then the dependent QTAG is selected. In this case, if the dependent instruction does not have all of its sources ready for issue, it does not issue. This is not a wasted slot, since the normal age-based issue selection did not find a ready instruction either. However, the fast wakeup of dependent instructions may benefit the performance of a critical section of code, in which case giving fast wakeup lower priority would hurt overall performance.
According to a fourth embodiment of the present invention, a soft switch (e.g., a programmable register, etc.) may be implemented by hardware, software, or a combination of hardware and software to select between any of the three embodiments of the present invention. Software can be optimized to select an embodiment of the present invention that would be most beneficial performance-wise to the currently executing computer code.
Returning to step 324, LMQ 116 determines if a load recycle has occurred for the current load instruction, as illustrated. If not, the process returns to step 320. If so, the process continues to step 328, which illustrates LMQ 116 determining if DQv field 206 corresponding to the current load instruction has a value of 1. If not, the process continues to step 334, which illustrates a selected instruction being issued by an issue queue to a corresponding execution unit. The process proceeds to step 336, which depicts the execution unit executing the selected instruction and outputting the result of the execution. The process ends, as illustrated in step 338.
If returning to step 328, if LMQ 116 determines that DQv field 206 corresponding to the current load instruction has a value of 1, the process continues to step 330, which depicts LMQ 116 selecting the instruction corresponding to Dep QTAG field 204 for issue during the next cycle. It should be understood that a load dependent instruction can reside in any of issue queues FXIQ 66, FXIQ 68, FPIQ 70, FPIQ 72, or VRIQ 73. TYPE field 210 can be utilized to determine the particular issue queue in which the load-dependent instruction resides. The process continues to step 334, which illustrates a selected instruction being issued by an issue queue to a corresponding execution unit. The process proceeds to step 336, which depicts the execution unit executing the selected instruction and outputting the result of the execution. The process ends, as illustrated in step 338.
As discussed, the present invention includes a system and method for issuing load-dependent instructions from an issue queue in a processing unit in a data processing system. A LSU determines if a load request from a load instruction missed a first level in a memory hierarchy. In response to determining the load request missed a first level in a memory hierarchy, a LMQ allocates a load-miss queue entry corresponding to the load instruction. The LMQ determines if at least one dispatched instruction dependent on the load request is located in at least one issue queue in said processing unit. In response to determining at least one dispatched instruction dependent on the load request is located in at least one issue queue in the processing unit, the LMQ associates the load-miss queue entry with at least one dispatch instruction. A memory manager retrieves data associated with the load request into the first level in said memory hierarchy from another level within the memory hierarchy. In response to retrieving data associated with the load request, the LMQ selects at least one dispatched instruction dependent on said load request for issue from at least one issue queue. In response to selecting, the issue queue issues the dispatched instruction dependent on the load request on a next processing unit cycle. The execution unit executes the dispatched instruction. The execution unit outputs a result of executing the dispatched instruction.
It should be understood that at least some aspects of the present invention may alternatively be implemented in a computer-usable medium that contains a program product. Programs defining functions in the present invention can be delivered to a data storage system or a computer system via a variety of signal-bearing media, which include, without limitation, non-writable storage media (e.g., CD-ROM), writable storage media (e.g., hard disk drive, read/write CD-ROM, optical media), system memory such as, but not limited to random access memory (RAM), and communication media, such as computer networks and telephone networks, including Ethernet, the Internet, wireless networks, and like networks. It should be understood, therefore, that such signal-bearing media, when carrying or encoding computer-readable instructions that direct method functions in the present invention, represent alternative embodiments of the present invention. Further, it is understood that the present invention may be implemented by a system having means in the form of hardware, software, or a combination of software and hardware as described herein or their equivalent.
While the present invention has been particularly shown and described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made herein without departing from the spirit and scope of the invention.
