Patent Application
20100332718
1. Field of the Invention
Embodiments of the invention relate generally to the field of memory devices. More specifically, embodiments of the present invention may provide one or more techniques for reducing latency times in memory devices.
2. Description of the Related Art
Electronic devices typically utilize one or more memory devices, such as a dynamic random access memory (DRAM), for storing data that may be used by the electronic device. For instance, the stored data may represent applications, media, an operating system, or any other type of suitable data that may be used by the electronic device. Typically, a memory device, such as a synchronous DRAM (SDRAM), includes a memory array divided into a plurality of memory banks, or other divisions. Based upon addressing information received by the memory device during operation, data may be stored into and read out of appropriate banks of the memory array.
The rate at which data may be read from a memory array is typically limited by the row cycle latency time (tRC) of the memory array, which may be defined as the minimum time interval that must elapse between issuing successive ACTIVE commands to the same physical bank of the memory array. By way of example, in a DDR2 SDRAM device, a typical tRC may be approximately 55 ns. As will be appreciated, due to tRC limitations, random read requests to the same physical bank must wait for tRC to elapse before a subsequent read may be performed. Thus, in applications where there is a need to issue repeated random read requests for reading a particular segment of data from a memory device at high speeds and low cycle times, it may be desirable to reduce the effective tRC of the memory device.
Some conventional solutions for addressing the latency drawbacks of conventional DRAM memory devices include providing low latency static RAM (SRAM) devices or reduced latency DRAM (RLDRAM) devices in place of conventional SDRAM devices. While such devices are capable of providing a lower tRC, such devices are also generally substantially higher in cost relative to SDRAM devices. Additionally, SRAM and RLDRAM devices also typically have higher power consumption requirements relative to SDRAM devices offering a similar storage capacity.
Another conventional technique for reducing tRC includes providing a copy of the requested read data to each of a plurality of DRAM devices and interleaving read requests among the plurality of DRAM devices. However, this technique not only requires that multiple DRAM devices be provided, but may also require a separate control circuitry to manage the interleaving of of read requests between the multiple devices, thus disadvantageously increasing costs, bus turn-around times, and amount of component space required relative to using a single memory device.
Accordingly, embodiments of the present invention may be directed to one or more of the problems set forth above.
One or more embodiments of the present invention relate to techniques for masking the row cycle time of a memory array. In one embodiment, a memory device that is configurable to operate in full or reduced density modes is provided. When operating in a reduced density mode, certain banks within such a memory array of the device may function as duplicate memory banks associated with a directly addressable memory bank. Thus, a write operation performed in a reduced density mode may not only write a data segment to the memory bank addressed by a write command, but may further duplicate the data segment by creating a copy of the data segment in each duplicate bank associated with the directly addressed bank. When repeated read requests are initiated for the data segment, the read requests may be interleaved between the addressed bank and its duplicate banks. Using such an interleaving technique, the interval between each read out of the data segment from the memory array is less than the row cycle time of each bank. As will be discussed further below, such embodiments of the present invention are particularly well-suited for applications in which a generally fixed or static segment of data is subject to a high rate of read requests. For instance, techniques disclosed herein may be implemented in the context of a network device, particularly where generally static lookup tables or network translation tables are repeatedly read. These and other features, aspects, and advantages will be discussed in further advantages will be discussed in further detail with regard to the following description of various embodiments of the present invention.
Keeping the foregoing points in mind and turning now to
The memory device 10 may be a component of an electronic device, such as a computer, portable media player, mobile phone, personal digital assistant, or a network router/switch, for instance. As shown in
The memory device 10 may interface with a memory access device, for example, a processor 12, such as a microprocessor, by way of the data bus 14 and address bus 16. Alternatively, the memory device 10 may interface with other memory access devices, such as an SDRAM controller, a microcontroller, a chip set, or other electronic system or device. As shown, the processor 12 may also provide a number of control signals 18 to the memory device 10. Such signals may include row and column address strobe signals RAS and CAS, a write enable signal WE, a clock enable signal CKE, a chip select signal CS, and other conventional control signals. By way of these control signals 18, the controller 20 may control the many available functions of the memory device 10, including the selection of operating the memory device 10 in either a full density or reduced density mode, as will be discussed in further detail below. In addition, various below. In addition, various other control circuits and signals not detailed herein may contribute to the operation of the memory device 10, as can be appreciated by those of ordinary skill in the art.
Address information from the address bus 16 may be received in the memory device 10 using the address register 24. A row address buffer 26 and row decoder circuitry 28 may receive and decode row addresses from the row address signals received by the address register 24. Each unique row address may correspond to a row of cells in the memory array 22. The row decoder 28 typically includes a word line driver, an address decoder tree, and circuitry which translates a given row address received from the row address buffer 26 and selectively activates the appropriate word line of the memory array 22 by way of the word line drivers.
The memory device 10 may also include a column address buffer 30 and column decoder circuitry 32 configured to receive and decode column address signals received by the address register 24. The column decoder 32 may also determine when a column within the memory array 22 is defective, as well as provide the address of a replacement column. As shown, the column decoder 32 is coupled to sense amplifiers 34, each of which may be coupled to complementary pairs of bit lines within the memory array 22.
In the present embodiment, the sense amplifiers 34 are coupled to data-in (e.g., write) circuitry 38 and data-out (e.g., read) circuitry 40. The data-in circuitry 38 and the data-out circuitry 40 may include I/O gating circuitry, data drivers, and latches configured to provide input and output data on the data bus 14 of the memory device 10. The data-in circuitry 38 and data-out circuitry 40 may be further coupled to a data buffer 42, which may include one or more buffers for buffers for delaying, regenerating, and storing data signals communicated between the processor 12 and the memory device 10. For instance, during a write operation, the data bus 14 provides data to the data-in circuitry 38. The sense amplifiers 34 receive the data from the data-in circuitry 38 and store the data to corresponding cells in the memory array 22, for example, as a charge on a capacitor of a memory cell located at an address specified on the address bus 16. By way of example only, the data bus 14, in one embodiment, may be an 8-bit data bus capable of transferring data at a frequency of 400 MHz or higher.
During a read operation, the memory device 10 transfers data to the processor 12 from the memory array 22. Complementary bit lines for the accessed cell are equilibrated during a precharge operation to a reference voltage provided by an equilibration circuit (not shown) and a reference voltage supply. The charge stored in the accessed cell is then shared with the corresponding bit lines. The sense amplifier 34 then detects and amplifies a difference in voltage between the complementary bit lines. The address information received on address bus 16 is used to select a subset of the bit lines, which is then coupled to complementary pairs of input/output (I/O) wires or lines. The I/O wires pass the amplified voltage signals to the data-out circuitry 40, the data buffer 42, and eventually out to the data bus 14 to be transmitted to the processor 12.
The data-out circuitry 40 may include a data driver (not shown) to drive data out onto the data buffer 42 and the data bus 14 in response a read request directed to the memory array 22. Further, the data-out circuitry 40 may include a data latch (not shown) to latch the read data until it is driven out onto the data buffer 42 and the data bus 14 by the data driver. Though not shown in in the present embodiment, it should be appreciated that a synchronization device, such as a delay lock loop circuit (DLL) may be utilized to provide a shifted clock signal that is synchronous with an external system clock CLK, thus synchronizing the output data signal with the system clock CLK.
As will be appreciated, the memory array 22 may be divided into a plurality of logical banks. Each logical bank may further include a plurality of addressable physical banks. By way of example only, the memory array 22 may be a 1 gigabit (Gb) array providing 8 logical banks and 16 physical banks, such that each logical bank includes 2 physical banks, each capable of storing 64 megabits (Mb) of data. Before any READ or WRITE commands may be issued to a particular memory bank, a row in that bank is activated. This is typically accomplished using an ACTIVE command, which may be initiated by low CS and RAS signals in combination with high CAS and WE signals occurring during the rising edge of the CLK signal. During the ACTIVE command, bank address signals 36 may be provided to bank control logic 46 via the address register 24. The bank control logic 46 may further provide the bank address signals 36 to the row decoder circuitry 28 and column decoder circuitry 32, as indicated by control signals 48 and 50, respectively. Based upon the row address signals, column address signals, and bank address signals, an appropriate memory bank within the memory array 22 may be activated.
As discussed above, the memory device 10 may be capable of operating in a full density mode or in one or more reduced density modes. In a full density mode of operation, all 8 logical banks may be directly addressable. That is, a memory access device, such as a processor, external to the memory device 10 may directly address each bank of the memory array 22 in a full full density mode of operation. As will be appreciated, each physical bank of a memory array has a row cycle latency time (tRC), which may be generally defined as the minimum time interval that must elapse between issuing successive ACTIVE commands to the same bank of the memory array 22. Generally, the tRC may be determined as the sum of the minimum RAS active time (tRAS) and the row precharge time (tRP) of the memory array 22. For instance, the tRC may be expressed by the following formula:
tRC=tRAS+tRP
By way of example only, a DDR2 SDRAM memory device utilizing the 8-logical bank/16-physical bank arrangement discussed above may have a tRC of approximately 55 ns.
When the memory device 10 operates in a reduced density mode, the memory array 22 may utilize a reduced bank count, in which only a portion of the number of banks within the memory array 22 are directly addressable by external commands (e.g., issued by the processor 12). For the purposes of the present disclosure, the term “directly addressable bank” or the like shall be understood to mean a memory bank that is directly addressable by something external to the memory device. For instance, in a reduced density mode, only half or a quarter of the banks within the memory array 22 may be directly addressable. Additionally, the term “inactive bank” shall be understood to mean a memory bank that is not a directly addressable bank. While the term “inactive” is used to describe such memory banks, it should be understood that these memory banks are not literally “inactive.” As will be explained in further detail below, when operating in a reduced density mode, “inactive banks” may be associated with a directly addressable bank and may function as a duplicate bank to which data written to the associated directly addressable bank directly addressable bank is duplicated. In this manner, the speed at which read requests for a segment of data stored in a particular directly addressable bank are read out from the memory array may overcome the inherent tRC of the memory array 22 by interleaving the reading of the requested data segment between the directly addressable bank and one or more associated duplicate banks.
Referring still to
Referring now to
To provide some examples, the memory array 22, in one embodiment, may be a 1 GB array in which each logical bank 60 has a size of 128 Mb, and each physical bank 62 has a size of 64 Mb. In another embodiment, the memory array 22 may be a 2 Gb array in which each logical bank 60 has a size of 256 Mb and each physical bank 62 has a size of 128 Mb. It should be understood that the presently illustrated embodiment is only meant to provide one example of a particular layout that may be implemented. In other embodiments, any suitable type of memory bank layout may be utilized, such as an 8-logical bank/32-physical bank layout or a 4-logical bank/16-physical bank layout (e.g., each having 4 physical banks per logical bank).
As illustrated by
Referring now to
As discussed above, due to the tRC of the physical bank in which DATA0 is stored (e.g., physical bank 0 (62a)), subsequent ACTIVE and READ commands to read DATA0 from physical bank 0 (62a) may not be issued until the tRC has elapsed. As shown in the timing diagram 68, if the tRC is 55 ns, a subsequent ACTIVE command (A0) and READ command (R0) may not be issued to physical bank 0 (62a) until 55 ns after the original ACTIVE command (A0). Then, following the read latency time of 5 clock cycles, DATA0 may be read out from physical bank 0 (62a) again at 85 ns, as indicated by the reference number 72. Thus, it should be understood that the interval between the time (30 ns) at which DATA0 was read out during the first read command and the time (85 ns) at which DATA0 is read out during the second read command is equivalent to the tRC of the memory array 22, which is 55 ns in the present example.
Following the second read command, a third read command may be issued at 110 ns (55 ns after issuing the previous ACTIVE command), and may include an ACTIVE command (A0) for activating physical bank 0 (62a). As depicted by the timing diagram 68, following a READ command (R0) at 115 ns, DATA0 may be read out from physical bank 0 once again at 140 ns. Thus, when operating in full density mode, the frequency at which DATA0 may be read from the memory array is limited by the tRC. As shown above, where the tRC is 55 ns, physical bank 0 (62a) may be issued ACTIVE commands at the times 0 ns, 55 ns, and 110 ns, and DATA0 may be read from physical bank 0 (62a) at times 30 ns, 85 ns, and 140 ns, respectively.
While the present full tRC may be suitable for some applications, in certain applications it may be desirable to provide a reduced effective tRC, such that DATA0 may be read out more frequently (e.g., at a faster rate). For instance, in applications where DATA0 represents a generally static segment of data in high demand, it may be desirable to utilize a reduced density mode of operation in accordance with aspects of the present technique in order to provide a reduced latency time between each READ command such that DATA0 may be read from the memory array more frequently. By way of example, one such application may pertain to high speed network routers. Such systems typically store a fixed segment or segments of data in the form of a lookup table or Network Address Translation (NAT) table that is generally written once (or infrequently) to a memory device. Such lookup tables or NAT tables are typically read out at typically read out at high speeds and low cycle times to provide internet protocol (IP) address translation and/or port mapping/forwarding.
As discussed above, a reduced effective tRC may be provided by operating the memory array 22 in a reduced density mode. Referring now to
As mentioned above, when operating in a reduced density mode, the memory controller 20 may implement appropriate WRITE and READ algorithms for facilitating a reduced tRC when reading data from the memory array 22. As shown in
As discussed above, the duplicate banks 60b, 60d, 60f, and 60h are “inactive” in the sense that when operating in the half-density mode, these duplicate banks are not directly addressable by a WRITE command issued by the processor 12. Rather, from the viewpoint of the processor 12, the memory array 22, when operating in half-density mode, has four directly addressable logical banks. When a WRITE command to write data to any of the directly addressable logical banks is received from the processor 12, the controller 20 instructs the memory device 10, such as by providing appropriate control signals 44 to the bank control logic 46, to write the data to the logical bank addressed by the WRITE command, and to additionally write the data to a duplicate bank associated with the directly addressed logical bank. However, it should be noted that an external device, such as the processor 12, may not have visibility of the write operation performed to the duplicate bank, and that such operations are carried out under the control of the memory controller 20. Further, as will be appreciated, because the write operations to a directly addressable bank and its associated duplicate bank are performed sequentially in half-density mode, a write operation in this mode may require more clock cycles to complete (e.g., to complete (e.g., approximately twice as many clock cycles). However, as will be discussed with respect to
Referring now to
Next, at 30 ns, a second read request is initiated by an ACTIVE command (A0) and READ command (R0). From the viewpoint of the processor 12, the commands A0 and R0 that are issued at 30 ns are no different than the commands A0 and R0 issued at 0 ns. However, from the viewpoint of the controller 20, because the tRC of physical bank 0 (62a) prevents this bank from being activated again at 30 ns, the controller 20 effectively “forwards” the second read request to duplicate bank 0 (60b), thereby activating the physical bank 2 (62c) in which the duplicate of DATA0 is stored. Thus, following a read latency of 5 clock cycles, DATA0 may be read from physical bank 2 (62c) of duplicate bank 0 (60b) at 60 ns, as indicated by reference number 94.
Subsequently, a third read request addressing logical bank 0 (60a) may be initiated, as shown by the ACTIVE (A0) and READ (R0) commands issued by the processor 12 at 60 ns. In the present example, the tRC of physical bank 2 (62c) of duplicate bank 0 (60b) has not yet elapsed, and thus physical bank 2 (62c) may not be activated at 60 ns. However, because the tRC of 55 ns has since elapsed with respect physical bank 0 (62a) of logical bank 0 (60a), physical bank 0 (62a) is available and may be activated in response to the request at 60 ns. Thus, the controller 20, upon receiving the ACTIVE (A0) and READ commands (R0) at 60 ns for reading DATA0, may activate physical bank 0 (62a) and carry out the READ command (R0). Accordingly, DATA0 may be read out again from physical bank 0 (62a) at 90 ns, as shown in timing diagram 90 and referred to by reference number 96.
Thereafter, a fourth read request addressing logical bank 0 (60a) may be initiated, as shown by the ACTIVE (A0) and READ (R0) commands issued by the processor 12 at 90 ns. In the present example, the tRC of physical bank 0 (62a) of logical bank 0 (60a) has not yet elapsed and, accordingly, physical bank 0 (62c) may not be activated at 90 ns. However, because the tRC of 55 ns has now elapsed with respect physical bank 2 (62c) of duplicate bank 0 (60b), physical bank 2 (62c) is available and may be activated. Thus, the controller 20, upon receiving the ACTIVE (A0) and READ commands (R0) at 90 ns may activate physical bank 2 (62c) and carry out the READ command (R0) thereto. Following the read latency time (RL), DATA0 may be read from physical bank 2 (62c) at 120 ns, as indicated by reference number 98.
Thus, as shown in
Further, it will be appreciated by those skilled in the art that the memory controller 20 may implement any suitable technique for monitoring the status of memory banks based on row cycle latency times to determined when ACTIVE commands may be issued, such as by using timers/counters, status registers, pointers, and so forth. For example, in the half-density operation mode illustrated in
Continuing now to
As shown in
In other words, DATA0 is written to the directly addressable target physical bank 0 (62a), and then duplicated into each of the duplicate banks 60b-60d. Again, it should be understood that the duplicate banks 60b-60d are “inactive” in the sense that are not directly addressable by the processor 12 when issuing a WRITE command, as the processor 12 may not have visibility with regard to the duplicate banks 60b-d (and 60f-h) of the memory array 22. Instead, when a WRITE command (e.g., 100) is issued, the controller 20 instructs the memory device 10 (e.g., by control signals 44 to the bank control logic 46) to duplicate the written data to each of the duplicate banks associated with the logical bank directly addressed by the issued WRITE command. Additionally, because the write operations to an addressable bank and its associated duplicate banks are performed sequentially in the quarter-density mode, a write operation in this mode may require more clock cycles to complete (e.g., approximately four times as many clock cycles). However, as will be discussed with respect to
Referring now to
For example, as illustrated by the timing diagram 102, ACTIVE commands (A0), each followed by a READ command (R0) to logical bank 0 (60a) are received at times 0 ns, 15 ns, 30 ns, 45 ns, and 60 ns. A first read operation, which begins at 0 ns, activates physical bank 0 (62a) of logical bank 0 (60a). Following the read latency (RL) time, DATA0 may be read from physical bank 0 (62a) at 30 ns, as indicated by reference number 104. Meanwhile, a second read operation is initiated at 15 ns. Because the tRC for physical bank 0 (62a) has not elapsed, the controller 20 may forward the ACTIVE command (A0) and READ command (R0) to the next available duplicate bank 60b. Thus, DATA0 may be read from physical bank 2 (62c) of duplicate bank 60b at 45 ns, as indicated by reference number 106.
Continuing along the timing diagram 102, a third read operation is initiated at 30 ns. At this point, the tRCs for physical bank 0 (62a) and physical bank 2 (62c) have not yet elapsed. Accordingly, the ACTIVE command (A0) and READ command (R0) received at 30 ns may be forwarded by the controller 20 to the next available duplicate bank 60c, whereby DATA0 is read from physical bank 4 (62e) of duplicate bank 60c at 60 ns, as indicated by the reference number 108. Next, a fourth operation is initiated at 45 ns. Here, the tRC (e.g., 55 ns) for physical bank 0 (62a), physical bank 2 (62c), and physical bank 4 (62e) have not yet elapsed. As such, the controller 20 may forward the ACTIVE command (A0) and READ command (R0) received at 45 ns to the final duplicate bank 60d associated with logical bank 0 (60a). Thus, DATA0 may be read from physical bank 6 (62g) at 75 ns, as indicated by reference number 110.
Referring now to the fifth read operation initiated at 60 ns, it should be noted that at this point of the timing diagram 102, the duplicate physical banks 62c, 62e, and 62g cannot be activated because their respective tRCs have not fully elapsed. However, because the present embodiment utilizes a tRC of 55 ns, physical bank 0 (62a) is available since 60 ns have elapsed since physical bank 0 was last activated at 0 ns. Thus, the ACTIVE command (A0) and READ command (R0) received at 60 ns may result in DATA0 being read out again from physical bank 0 (62a) of logical bank 0 (60a), as indicated by reference number 112.
As will be appreciated, the process of interleaving read requests using the illustrated quarter-density mode of operation essentially repeats from this point forward. That is, a subsequent read command received at 75 ns would be issued to duplicate bank 60b by the controller 20, a subsequent read command received at 90 ns would be issued to duplicate bank 60c by the controller 20, and so forth. In other words, read commands issued to logical bank 0 (60a) by the processor 12 are interleaved between logical bank 0 (60a) and the corresponding duplicate banks 60b-60d to mask the tRC of the individual physical banks of the memory array 22. Using this technique of interleaving the read requests between the addressable bank and the three corresponding duplicate banks, each storing duplicate copies of DATA0 (e.g., using the duplicating WRITE command 100 shown in
Additionally, it should also be appreciated that the controller 20 may utilize any suitable technique for managing the interleaving of the read commands issued to physical bank 0 (62a), such as the counter/register scheme discussed above, or by using a pointer that is incremented after each directly addressable physical or duplicate bank is activated. For instance, the pointer may be reset once the directly addressable bank and all its associated duplicate banks have been activated.
Referring now to
Referring now to the WRITE command 124, when operating in the presently illustrated quarter-density mode, the controller 20 may implement a write algorithm that writes a first data segment DATA0 into physical bank 0 (122a) of logical bank 0 (120a). Thereafter, the first data segment DATA0 is also written into duplicate physical banks 122b-122d, such that all physical banks within logical bank 0 store a copy of DATA0. A similar write command 126 is illustrated illustrated with respect to logical bank 1 (120b), in which a second data segment DATA1 is written into physical bank 4 (122e), and then duplicated into associated duplicate banks 122f-122h using successive write operations to each duplicate bank.
Referring now to
As shown by the timing diagram 128, ACTIVE commands (A0), each followed by a READ command (R0) to logical bank 0 (120a) are issued by the processor 12 at times 0 ns, 15 ns, 30 ns, 45 ns, and 60 ns. A first read operation, which begins at 0 ns, activates physical bank 0 (122a), whereby DATA0 may be read from physical bank 0 (122a) at 30 ns, as indicated by reference number 130, following a read latency (RL) time equivalent to 5 clock cycles. A second read operation is initiated at 15 ns. As explained above, the tRC for physical bank 0 (122a) has not elapsed and, thus, the controller 20 may forward the ACTIVE command (A0) and READ command (R0) received at 15 ns to the duplicate bank 122b. Accordingly, DATA0 may be read from duplicate bank 122b at 45 ns, as indicated by reference number 132.
Continuing along timing diagram 128, a third read operation is initiated at 30 ns. At this point, the tRCs for physical bank 0 (122a) and duplicate bank 122b have not yet elapsed. Thus, the controller 20 may forward the ACTIVE command (A0) and READ command (R0) received at 30 ns to the next available duplicate bank 122c, whereby DATA0 is read from duplicate bank 122c at 60 ns, as indicated by the reference number 134. Next, a fourth read operation is initiated at 45 ns. Here, the tRCs for physical bank 0 (122a) and duplicate banks 122b and 122c have not yet elapsed. As such, the controller 20 may forward the ACTIVE command (A0) and READ command (R0) received at 45 ns to the final duplicate bank 122d within logical bank 0 (120a). Thus, DATA0 may be read from duplicate bank 122d at 75 ns, as indicated by reference number 136.
Referring now to the fifth read operation, which is initiated at 60 ns, the duplicate physical banks 122b, 122c, and 122d cannot be issued ACTIVE commands because their tRCs have not fully elapsed. However, because the memory array 22 of the present embodiment has a tRC of 55 ns, physical bank 0 (122a) is available because at least 55 ns have elapsed since physical bank 0 was last activated at 0 ns. Thus, the ACTIVE command (A0) and READ command (R0) received at 60 ns may result in DATA0 being read out from physical bank 0 (122a) again at 90 ns, as indicated by reference number 130. As will be appreciated, additional read requests received from this point forward may essentially repeat the interleaved manner of reading of DATA0 from the physical banks 122a-122d of logical bank 0 (120a). For instance, a sixth ACTIVE and READ sixth ACTIVE and READ command at 75 ns may be issued to duplicate bank 122b, a seventh ACTIVE and READ command at 90 ns may be issued to duplicate bank 122c, and so forth.
As discussed above, the interleaving of the read requests using the quarter-density mode in the manner described herein provides for an effective tRC that, from the viewpoint of the processor 12, may be significantly less than the tRC of the individual physical banks of the memory array 22. For instance, in the present example, DATA0 may be read repeatedly from the memory array 22 at approximately every 15 ns, whereas the tRC of any single physical bank is 55 ns. Additionally, it should also be understood that the memory controller 20 may utilize any suitable technique for managing the interleaving of the read requests between physical banks 122a-122d, such as by using the counter/register scheme discussed above, or via using a pointer that is incremented after each directly addressable physical or duplicate physical bank is activated, such that a subsequently received ACTIVE command is directed to a different physical bank address within the logical bank 0 (120a).
While the memory device 10 discussed in the above embodiments has generally been referred to as a DDR SDRAM device having a tRC of 55 ns, it should be understood that this particular timing is provided merely by way of example. For instance, in some faster DDR3 SRDAM devices, tRCs as low as approximately 45 ns for each physical bank may be achieved. Still, in other embodiments, tRCs may also be greater than 55 ns. For example, referring now to
As shown by the timing diagram 129, first, second, third, and fourth read requests (including an ACTIVE and READ command) are initiated by the processor 12 at times corresponding to 0 ns, 15 ns, 30 ns, and 45 ns, respectively. The first read request at 0 ns may result in DATA0 being read out from physical bank 0 (122a) at 30 ns, as discussed above and indicated by reference number 130. The second read request to physical bank 0 (122a) at 15 ns may be forwarded by the controller 20 to duplicate bank 122b, whereby DATA0 is read out from duplicate bank 122b at 45 ns, as indicated by reference number 132. Next, the third read request to physical bank 0 (122a) at 30 ns may be forwarded to the duplicate bank 122c. Thus, at 60 ns, DATA0 may be read out from duplicate bank 122c, as indicated by reference number 134. Further, the fourth read request to physical bank 0 (122a) at 45 ns may be forwarded by the controller 20 to the duplicate bank 122d, whereby DATA0 is read out from the duplicate bank 122d at 75 ns, as indicated by reference number 136.
As mentioned above, in the present example, the tRC of each physical bank is 65 ns. Thus, at 60 ns, none of the physical banks 122a-122d within logical bank 0 (120a) is available to receive an ACTIVE command. Thus, the controller 20 may either wait until a physical bank is available or, as shown in
The above-discussed techniques may be further illustrated by the flowcharts depicted in
Returning to decision step 146, if it is determined that the memory device 10 is operating in a reduced density mode of operation, one or more duplicate banks that may be associated with the destination bank determined at step 144 are identified at step 152. Duplicate banks may include other “inactive” logical banks, as discussed above with reference to
Referring now to
Returning to step 164, if it is determined that memory device 10 is operating in a reduced density mode of operation, the method 160 proceeds to step 174, in which one or more duplicate banks that may be associated with the target bank are identified. Next, at step 176, DATA0 is read from the target bank. Thereafter, at step 178, in response to a subsequent read request from the multiple read requests received at step 162 above, DATA0 is read from a duplicate bank. Continuing to decision step 180, a determination is made as to whether additional additional duplicate banks are available. As discussed above, by interleaving read requests for DATA0 between the target bank and its duplicate banks, the effective tRC may be reduced from the viewpoint of the processor 12. As will be appreciated, the number of duplicate banks may depend on the layout of the memory array 22 and the reduced density mode being utilized. For instance, the 8-logical bank arrangement shown in
Returning to step 180, if no additional duplicate banks are available, a determination is made at step 182 as to whether additional read commands for DATA0 have been issued by the processor 12. If additional read commands have been issued, then the method 160 continues to decision step 184 to determine whether the tRC for the target bank has elapsed. As shown in
It should be understood that the specific memory array 22 layouts (e.g., 1 Gb memory array having 8-logical banks and 16 physical banks or 32 physical banks) and timing schemes (e.g., tRC=60 ns at full density mode; tRC=30 ns at half-density mode; and tRC=15 ns at quarter-density mode) discussed above are provided merely by way of example in order to facilitate and simplify the discussion of the configurable density and latency features of the memory devices disclosed herein. Indeed, it should be appreciated that embodiments of the present invention may utilize any suitable timing configuration or layout depending on the specific needs for a particular implementation.
For instance, as discussed above, the presently disclosed techniques may be particularly useful in applications, such as high-speed network routing, in which a generally static segment of data, such as a NAT table is subject to a high frequency of read requests. Thus, to implement a reduced density operation mode on a memory device storing the NAT table, the memory array 22 may be selected based upon the size of the NAT table. For instance, if the total size of the NAT table is less than 64 Mb, then a 1 Gb array utilizing 16 physical banks arranged in 8 logical banks, as shown in
It should be further appreciated that the present technique offers several advantages over conventional methods for reducing or masking tRC. As mentioned above, one conventional technique for reducing tRC in applications includes providing SRAM devices or RLDRAM devices with lower tRCs in place of conventional DRAMS or SDRAMS. While it is possible to provide tRCs of as low as 15 ns using such devices, those skilled in the art will appreciate that SRAMs and RLDRAMs are typically substantially higher in cost relative to SDRAM devices. Additionally, the power consumption of an SRAM or RLDRAM device is also generally higher than a typical SDRAM device having comparable storage capacities, due at least partially to increased complexity in the memory circuitry of SRAM and RLDRAM architectures.
Another conventional technique for reducing tRC relates to interleaving read requests for a segment of data copied among a plurality of DRAM devices. As mentioned above, however, this technique not only requires that multiple DRAM devices be provided, but may also require a separate control circuitry to manage the interleaving of read requests between the multiple devices, thus disadvantageously increasing costs, bus turn-around times, and amount of component space required relative to using a single memory device. Thus, the presently disclosed techniques, which may be carried out using a single DRAM device, greatly reduces the cost and complexity of such conventional multiple device configuration for masking tRCs.
While the invention may be susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and will be described in detail herein. However, it should be understood that the invention is not intended to be limited to the particular forms disclosed. Rather, the invention is to cover all modifications, equivalents equivalents and alternatives falling within the spirit and scope of the invention as defined by the following appended claims.
