Patent Application
20120062615
This disclosure relates to the dynamic selection of drive scheme voltages.
Electromechanical systems include devices having electrical and mechanical elements, actuators, transducers, sensors, optical components (e.g., mirrors) and electronics. Electromechanical systems can be manufactured at a variety of scales including, but not limited to, microscales and nanoscales. For example, microelectromechanical systems (MEMS) devices can include structures having sizes ranging from about a micron to hundreds of microns or more. Nanoelectromechanical systems (NEMS) devices can include structures having sizes smaller than a micron including, for example, sizes smaller than several hundred nanometers. Electromechanical elements may be created using deposition, etching, lithography, and/or other micromachining processes that etch away parts of substrates and/or deposited material layers, or that add layers to form electrical and electromechanical devices.
One type of electromechanical systems device is called an interferometric modulator (IMOD). As used herein, the term interferometric modulator or interferometric light modulator refers to a device that selectively absorbs and/or reflects light using the principles of optical interference. In some implementations, an interferometric modulator may include a pair of conductive plates, one or both of which may be transparent and/or reflective, wholly or in part, and capable of relative motion upon application of an appropriate electrical signal. In an implementation, one plate may include a stationary layer deposited on a substrate and the other plate may include a reflective membrane separated from the stationary layer by an air gap. The position of one plate in relation to another can change the optical interference of light incident on the interferometric modulator. Interferometric modulator devices have a wide range of applications, and are anticipated to be used in improving existing products and creating new products, especially those with display capabilities.
The systems, methods and devices of the disclosure each have several innovative aspects, no single one of which is solely responsible for the desirable attributes disclosed herein.
One innovative aspect of the subject matter described in this disclosure can be implemented in a method of calibrating an array. The method may include driving an array using a selected set of drive scheme voltages. The method may also determine a first drive response characteristic of the array based at least in part on a measurement of a first subset of the array, determine a first updated drive scheme voltage for the array based at least in part on the determined response characteristic, and may drive the array using the first updated drive scheme voltage. Further, the method may determine a second drive response characteristic of the array based at least in part on a measurement of a second subset of the array, determine a second updated drive scheme voltage for the array based at least in part on the determined response characteristic, and may drive the array using the first and second updated drive scheme voltages. In some aspects, the first and second subsets are associated with different colors.
In another aspect, an apparatus for calibrating drive scheme voltages is provided. The apparatus may include an array of elements, element state sensing circuitry, and driver and processor circuitry. The driver and processor circuitry may be configured to drive an array using a selected set of drive scheme voltages, determine a first drive response characteristic of the array based at least in part on a measurement of a subset of the array, determine a first updated drive scheme voltage for the array based at least in part on the determined response characteristic, and may be configured to drive the array using the first updated drive scheme voltage. Furthermore, the driver and processor circuitry may be configured to determine a second drive response characteristic of the array based at least in part on a measurement of a subset of the array, determine a second updated drive scheme voltage for the array based at least in part on the determined response characteristic, and may be configured to drive the array using the first and second updated drive scheme voltages. In some aspects, the apparatus may include a temperature sensor and a look up table containing information relating drive response characteristics or drive scheme voltages with temperature.
In another aspect, an apparatus for calibrating a display may include an array of elements, means for sensing element states, means for determining a first drive response characteristic of the array based at least in part on a measurement of a first subset of the array, means for determining a first updated drive scheme voltage for the array based at least in part on the determined response characteristic, and means for driving the array using the first updated drive scheme voltage. The apparatus may further include means for determining a second drive response characteristic of the array based at least in part on a measurement of a second subset of the array, means for determining a second updated drive scheme voltage for the array based at least in part on the determined response characteristic, and means for driving the array using the first and second updated drive scheme voltages. In some aspects, the apparatus may include means for measuring temperature and means for storing and retrieving information relating drive response characteristics or drive scheme voltages with temperature.
In another aspect, a non-transient computer readable media is provided. The computer readable media may have stored thereon instructions causing a driver circuit to drive an array using a selected set of drive scheme voltages, determine a first drive response characteristic of the array based at least in part on a measurement of a first subset of the array, determine a first updated drive scheme voltage for the array based at least in part on the determined response characteristic, and drive the array using the first updated drive scheme voltage. The instructions may further cause the driver circuit to determine a second drive response characteristic of the array based at least in part on a measurement of a second subset of the array, determine a second updated drive scheme voltage for the array based at least in part on the determined response characteristic, and drive the array using the first and second updated drive scheme voltages.
Details of one or more implementations of the subject matter described in this specification are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages will become apparent from the description, the drawings, and the claims. Note that the relative dimensions of the following figures may not be drawn to scale.
Like reference numbers and designations in the various drawings indicate like elements.
The following detailed description is directed to certain implementations for the purposes of describing the innovative aspects. However, the teachings herein can be applied in a multitude of different ways. The described implementations may be implemented in any device that is configured to display an image, whether in motion (e.g., video) or stationary (e.g., still image), and whether textual, graphical or pictorial. More particularly, it is contemplated that the implementations may be implemented in or associated with a variety of electronic devices such as, but not limited to, mobile telephones, multimedia Internet enabled cellular telephones, mobile television receivers, wireless devices, smartphones, bluetooth devices, personal data assistants (PDAs), wireless electronic mail receivers, hand-held or portable computers, netbooks, notebooks, smartbooks, tablets, printers, copiers, scanners, facsimile devices, GPS receivers/navigators, cameras, MP3 players, camcorders, game consoles, wrist watches, clocks, calculators, television monitors, flat panel displays, electronic reading devices (e.g., e-readers), computer monitors, auto displays (e.g., odometer display, etc.), cockpit controls and/or displays, camera view displays (e.g., display of a rear view camera in a vehicle), electronic photographs, electronic billboards or signs, projectors, architectural structures, microwaves, refrigerators, stereo systems, cassette recorders or players, DVD players, CD players, VCRs, radios, portable memory chips, washers, dryers, washer/dryers, parking meters, packaging (e.g., electromechanical systems (EMS), MEMS and non-MEMS), aesthetic structures (e.g., display of images on a piece of jewelry) and a variety of electromechanical systems devices. The teachings herein also can be used in non-display applications such as, but not limited to, electronic switching devices, radio frequency filters, sensors, accelerometers, gyroscopes, motion-sensing devices, magnetometers, inertial components for consumer electronics, parts of consumer electronics products, varactors, liquid crystal devices, electrophoretic devices, drive schemes, manufacturing processes, and electronic test equipment. Thus, the teachings are not intended to be limited to the implementations depicted solely in the Figures, but instead have wide applicability as will be readily apparent to a person having ordinary skill in the art.
In some drive scheme implementations, the process of writing information to a pixel is accomplished by applying drive scheme voltages across the pixel that are sufficient to actuate the pixel, release the pixel, or hold the pixel in its current state. Because the voltages which actuate and release the pixels may be different for different display elements, determination of appropriate drive scheme voltages to avoid artifacts in displaying an image can be difficult.
The task of determining appropriate drive scheme voltages can be further complicated by the fact that the voltages which actuate and release the pixels can change through the life of the display, e.g., with wear or with a change in temperature. Accurately measuring these values by examining the entire array to update the drive scheme voltages may be time-consuming. Thus, in some implementations, drive scheme voltages are dynamically updated based on measurements of subsets of the entire array. For example, in some implementations, updated drive scheme voltages are determined based on measurements of a representative line or set of lines.
Particular implementations of the subject matter described in this disclosure can be implemented to realize one or more of the following potential advantages. Implementations described herein allow for the changing pixel actuation and release voltages to be dynamically compensated for, thereby reducing the number of artifacts in displaying an image or series of images, e.g., actuation when actuation is not desired or non-actuation when actuation is desired. Further, by updating the drive scheme voltages based on measurements of subsets of the entire array, the process can be performed quickly and frequently, thus reducing perceptible artifacts in the display over the life of the display and in varying environmental conditions.
An example of a suitable EMS or MEMS device, to which the described implementations may apply, is a reflective display device. Reflective display devices can incorporate interferometric modulators (IMODs) to selectively absorb and/or reflect light incident thereon using principles of optical interference. IMODs can include an absorber, a reflector that is movable with respect to the absorber, and an optical resonant cavity defined between the absorber and the reflector. The reflector can be moved to two or more different positions, which can change the size of the optical resonant cavity and thereby affect the reflectance of the interferometric modulator. The reflectance spectrums of IMODs can create fairly broad spectral bands which can be shifted across the visible wavelengths to generate different colors. The position of the spectral band can be adjusted by changing the thickness of the optical resonant cavity, i.e., by changing the position of the reflector.
The IMOD display device can include a row/column array of IMODs. Each IMOD can include a pair of reflective layers, i.e., a movable reflective layer and a fixed partially reflective layer, positioned at a variable and controllable distance from each other to form an air gap (also referred to as an optical gap or cavity). The movable reflective layer may be moved between at least two positions. In a first position, i.e., a relaxed position, the movable reflective layer can be positioned at a relatively large distance from the fixed partially reflective layer. In a second position, i.e., an actuated position, the movable reflective layer can be positioned more closely to the partially reflective layer. Incident light that reflects from the two layers can interfere constructively or destructively depending on the position of the movable reflective layer, producing either an overall reflective or non-reflective state for each pixel. In some implementations, the IMOD may be in a reflective state when unactuated, reflecting light within the visible spectrum, and may be in a dark state when unactuated, reflecting light outside of the visible range (e.g., infrared light). In some other implementations, however, an IMOD may be in a dark state when unactuated, and in a reflective state when actuated. In some implementations, the introduction of an applied voltage can drive the pixels to change states. In some other implementations, an applied charge can drive the pixels to change states.
The depicted portion of the pixel array in
In
The optical stack 16 can include a single layer or several layers. The layer(s) can include one or more of an electrode layer, a partially reflective and partially transmissive layer and a transparent dielectric layer. In some implementations, the optical stack 16 is electrically conductive, partially transparent and partially reflective, and may be fabricated, for example, by depositing one or more of the above layers onto a transparent substrate 20. The electrode layer can be formed from a variety of materials, such as various metals, for example indium tin oxide (ITO). The partially reflective layer can be formed from a variety of materials that are partially reflective, such as various metals, e.g., chromium (Cr), semiconductors, and dielectrics. The partially reflective layer can be formed of one or more layers of materials, and each of the layers can be formed of a single material or a combination of materials. In some implementations, the optical stack 16 can include a single semi-transparent thickness of metal or semiconductor which serves as both an optical absorber and conductor, while different, more conductive layers or portions (e.g., of the optical stack 16 or of other structures of the IMOD) can serve to bus signals between IMOD pixels. The optical stack 16 also can include one or more insulating or dielectric layers covering one or more conductive layers or a conductive/absorptive layer.
In some implementations, the layer(s) of the optical stack 16 can be patterned into parallel strips, and may form row electrodes in a display device as described further below. As will be understood by one having skill in the art, the term “patterned” is used herein to refer to masking as well as etching processes. In some implementations, a highly conductive and reflective material, such as aluminum (Al), may be used for the movable reflective layer 14, and these strips may form column electrodes in a display device. The movable reflective layer 14 may be formed as a series of parallel strips of a deposited metal layer or layers (orthogonal to the row electrodes of the optical stack 16) to form columns deposited on top of posts 18 and an intervening sacrificial material deposited between the posts 18. When the sacrificial material is etched away, a defined gap 19, or optical cavity, can be formed between the movable reflective layer 14 and the optical stack 16. In some implementations, the spacing between posts 18 may be about 1-1000 um, while the gap 19 may be less than about 10,000 Angstroms (Å).
In some implementations, each pixel of the IMOD, whether in the actuated or relaxed state, is essentially a capacitor formed by the fixed and moving reflective layers. When no voltage is applied, the movable reflective layer 14 remains in a mechanically relaxed state, as illustrated by the pixel 12 on the left in
The processor 21 can be configured to communicate with an array driver 22. The array driver 22 can include a row driver circuit 24 and a column driver circuit 26 that provide signals to, e.g., a display array or panel 30. The cross section of the IMOD display device illustrated in
In some implementations, a frame of an image may be created by applying data signals in the form of “segment” voltages along the set of column electrodes, in accordance with the desired change (if any) to the state of the pixels in a given row. Each row of the array can be addressed in turn, such that the frame is written one row at a time. To write the desired data to the pixels in a first row, segment voltages corresponding to the desired state of the pixels in the first row can be applied on the column electrodes, and a first row pulse in the form of a specific “common” voltage or signal can be applied to the first row electrode. The set of segment voltages can then be changed to correspond to the desired change (if any) to the state of the pixels in the second row, and a second common voltage can be applied to the second row electrode. In some implementations, the pixels in the first row are unaffected by the change in the segment voltages applied along the column electrodes, and remain in the state they were set to during the first common voltage row pulse. This process may be repeated for the entire series of rows, or alternatively, columns, in a sequential fashion to produce the image frame. The frames can be refreshed and/or updated with new image data by continually repeating this process at some desired number of frames per second.
The combination of segment and common signals applied across each pixel (that is, the potential difference across each pixel) determines the resulting state of each pixel.
As illustrated in
When a hold voltage is applied on a common line, such as a high hold voltage VCHOLD
When an addressing, or actuation, voltage is applied on a common line, such as a high addressing voltage VCADD
In some implementations, hold voltages, address voltages, and segment voltages may be used which always produce the same polarity potential difference across the modulators. In some other implementations, signals can be used which alternate the polarity of the potential difference of the modulators. Alternation of the polarity across the modulators (that is, alternation of the polarity of write procedures) may reduce or inhibit charge accumulation which could occur after repeated write operations of a single polarity.
During the first line time 60a: a release voltage 70 is applied on common line 1; the voltage applied on common line 2 begins at a high hold voltage 72 and moves to a release voltage 70; and a low hold voltage 76 is applied along common line 3. Thus, the modulators (common 1, segment 1), (1,2) and (1,3) along common line 1 remain in a relaxed, or unactuated, state for the duration of the first line time 60a, the modulators (2,1), (2,2) and (2,3) along common line 2 will move to a relaxed state, and the modulators (3,1), (3,2) and (3,3) along common line 3 will remain in their previous state. With reference to
During the second line time 60b, the voltage on common line 1 moves to a high hold voltage 72, and all modulators along common line 1 remain in a relaxed state regardless of the segment voltage applied because no addressing, or actuation, voltage was applied on the common line 1. The modulators along common line 2 remain in a relaxed state due to the application of the release voltage 70, and the modulators (3,1), (3,2) and (3,3) along common line 3 will relax when the voltage along common line 3 moves to a release voltage 70.
During the third line time 60c, common line 1 is addressed by applying a high address voltage 74 on common line 1. Because a low segment voltage 64 is applied along segment lines 1 and 2 during the application of this address voltage, the pixel voltage across modulators (1,1) and (1,2) is greater than the high end of the positive stability window (i.e., the voltage differential exceeded a predefined threshold) of the modulators, and the modulators (1,1) and (1,2) are actuated. Conversely, because a high segment voltage 62 is applied along segment line 3, the pixel voltage across modulator (1,3) is less than that of modulators (1,1) and (1,2), and remains within the positive stability window of the modulator; modulator (1,3) thus remains relaxed. Also during line time 60c, the voltage along common line 2 decreases to a low hold voltage 76, and the voltage along common line 3 remains at a release voltage 70, leaving the modulators along common lines 2 and 3 in a relaxed position.
During the fourth line time 60d, the voltage on common line 1 returns to a high hold voltage 72, leaving the modulators along common line 1 in their respective addressed states. The voltage on common line 2 is decreased to a low address voltage 78. Because a high segment voltage 62 is applied along segment line 2, the pixel voltage across modulator (2,2) is below the lower end of the negative stability window of the modulator, causing the modulator (2,2) to actuate. Conversely, because a low segment voltage 64 is applied along segment lines 1 and 3, the modulators (2,1) and (2,3) remain in a relaxed position. The voltage on common line 3 increases to a high hold voltage 72, leaving the modulators along common line 3 in a relaxed state.
Finally, during the fifth line time 60e, the voltage on common line 1 remains at high hold voltage 72, and the voltage on common line 2 remains at a low hold voltage 76, leaving the modulators along common lines 1 and 2 in their respective addressed states. The voltage on common line 3 increases to a high address voltage 74 to address the modulators along common line 3. As a low segment voltage 64 is applied on segment lines 2 and 3, the modulators (3,2) and (3,3) actuate, while the high segment voltage 62 applied along segment line 1 causes modulator (3,1) to remain in a relaxed position. Thus, at the end of the fifth line time 60e, the 3×3 pixel array is in the state shown in
In the timing diagram of
The details of the structure of interferometric modulators that operate in accordance with the principles set forth above may vary widely. For example,
As illustrated in
In implementations such as those shown in
The process 80 continues at block 84 with the formation of a sacrificial layer 25 over the optical stack 16. The sacrificial layer 25 is later removed (e.g., at block 90) to form the cavity 19 and thus the sacrificial layer 25 is not shown in the resulting interferometric modulators 12 illustrated in
The process 80 continues at block 86 with the formation of a support structure e.g., a post 18 as illustrated in
The process 80 continues at block 88 with the formation of a movable reflective layer or membrane such as the movable reflective layer 14 illustrated in
The process 80 continues at block 90 with the formation of a cavity, e.g., cavity 19 as illustrated in
Still with reference to
As described in detail above, to write a line of display data, the segment driver 902 may apply voltages to the segment electrodes or buses connected thereto. Thereafter, the common driver 904 may pulse a selected common line connected thereto to cause the display elements along the selected line to display the data, for example by actuating selected display elements along the line in accordance with the voltages applied to the respective segment outputs.
After display data is written to the selected line, the segment driver 902 may apply another set of voltages to the buses connected thereto, and the common driver 904 may pulse another line connected thereto to write display data to the other line. By repeating this process, display data may be sequentially written to any number of lines in the display array.
The time of writing display data (a.k.a. the write time) to the display array using such process is generally proportional to the number of lines of display data being written. In many applications, however, it may be advantageous to reduce the write time, for example to increase the frame rate of a display or reduce any perceivable flicker.
In order to reduce the write time of a display array, the display array may be separated into two portions that can be driven in parallel.
To write lines of display data in parallel to the display array of
Returning now to
As described above, these values are different for different interferometric modulators. It is possible to characterize an approximate median positive and negative actuation voltage for the array, designated VA50+ and VA50− respectively in
Similarly, at a positive polarity release voltage above the center voltage and at a negative polarity release voltage below the center voltage, the interferometric modulator changes from the actuated state to the released state. As with the positive and negative actuation voltages, it is possible to characterize an approximate middle or average positive and negative release voltage for the array, designated VR50+ and VR50− respectively in
These average or representative values for the array can be used to derive drive scheme voltages for the array. In some implementations, a positive hold voltage (designated 72 in
When the array is a color array having different common lines of different colors as described above with reference to
As mentioned above, the values for VA50+, VA50−, VR50+, and VR50− may vary between different arrays due to manufacturing tolerances, and may also vary in a single array with temperature, over time, depending on use, and the like. To initially set and later adjust these voltages to produce a display that functions well over its lifetime it is possible to incorporate testing and state sensing circuitry into a display apparatus. This is illustrated in
In the implementation of
As one example test protocol, each segment driver output could be set to a voltage, VS+, for example. Switches 648 and 646 of the integrator are initially closed. To test line 620, for example, switch 632a and switch 642a are closed, and a test voltage is applied to the common line 620, charging the capacitive display elements and an isolation capacitor 644. Then, switch 632a, 648, and 646 are opened, and the voltages output from the segment drivers are changed by an amount ΔV. The charge on the capacitors formed by the display elements is changed by an amount equal to about ΔV times the total capacitance of all the display elements. This charge flow from the display elements is converted to a voltage output by the integrator 650 with integration capacitor 652, such that the voltage output of the integrator is a measure of the total capacitance of the display elements along the common line 620.
This can be used to determine the parameters VA50+, VA50−, VR50+ and VR50− for a line of display elements being tested. To accomplish this, a first test voltage is applied that is known to release all of the display elements in the line. This may be 0 volts for example. In this instance, the total voltage across the display elements is VS+, which is, for example, 2V, which is within the release window of all the display elements. The output voltage of the capacitor when the segment voltages are modulated by ΔV is recorded. This integrator output may be referred to as Vmin for the line, which corresponds to the lowest line capacitance Cmin of the line. This is repeated with a common line test voltage that is known to actuate all of the display elements in the line, for example 20V. This integrator output may be referred to as Vmax for the line, which corresponds to the highest line capacitance Cmax of the line.
To determine VA50+ (positive polarity being defined here as common line at higher potential than segment line), the display elements of the line are first released with a low voltage, such as 0V on the common line. Then, a test voltage between 0V and 20V is applied. If the difference between the test voltage and the segment voltage is at VA50+, then the output of the integrator will be (Vmax+Vmin)/2.
Since there may be no prior knowledge of the correct value for VA50+, it can be found efficiently with a binary search for the correct test voltage in some implementations. For instance, if VA50+ is exactly 12V, then the proper test voltage will be 14V, which will produce 12V across the display elements when the segment voltage is 2V as discussed in the example above. To run a binary search, the first test voltage can be the midpoint between the low and high voltages of 0V and 20V, which is 10V. When 10V test voltage is applied and the segment voltages are modulated, the integrator output will be less than (Vmax Vmin)/2, which indicates that 10V is too low. In a binary search, each next “guess” is halfway between the last value known to be too low and the last value known to be too high. Thus, the next voltage attempt will be midway between 10V and 20V, which is 15V. When 15V test voltage is applied and the segment voltages are modulated, the integrator output will be more than (Vmax+Vmin)/2, which indicates that 15V is too high. Repeating the binary search algorithm, the next test voltage will be 12.5V. This will produce an integrator output that is too low, and the next test voltage will be 13.75V. This process can continue until the integrator output and test voltage are as close as desired to the actual values of (Vmax+Vmin)/2 and 14V. In some implementations, eight iterations are almost always sufficient to determine VA50+ as the last applied test voltage minus the applied segment voltage. The search can be terminated prior to eight iterations if the integrator output is sufficiently close to (Vmax+Vmin)/2, for example, within about 10%, or within about 1% of the desired (Vmax+Vmin)/2 target value. To determine VA50− the process is repeated with negative test voltages applied to the common line. VR50+ and VR50− may be determined in an analogous manner, but the display elements are first actuated prior to each test, rather than released.
During manufacture of the array, this process can be performed on each line of the array to determine the parameters VA50+, VA50−, VR50+, and VR50− for each line. For a monochrome array, the values of VA50+, VA50−, VR50+, and VR50− for the array can be the average of the determined values for each line, and drive scheme voltages can be derived for the array as described above. For a color array, the values can be grouped by color, and drive scheme voltages for the array can also be derived as described above.
During use of such an array, it would be possible to repeat the above described process for each line and derive new drive scheme voltages that are suitable for the current condition of the array, temperature, etc. However, this can be undesirable because this procedure can take a significant amount of time and be visible to the user. To improve speed and to reduce interference with display viewing by the user, the array can be divided into subsets, and only one or more subsets of the array may be tested and characterized. These subsets can be sufficiently representative of the whole array such that the drive scheme voltages derived from these subset measurements are suitable for the whole array. This reduces the time required to perform the measurements, and can allow the process to be performed during use of the array with less inconvenience to the user. Referring back to
In some implementations, during different loops of blocks 730 and 740, different subsets of the array can be used. Also, different drive response characteristics of the array can be measured. For example, during one loop, VA50+ can be determined for one line (or group of lines), and during a second loop, VR50− can be determined for a different line (or group of lines). With each loop, the drive scheme voltages can be updated with the new information. This can speed the measurement process within each loop between display image updates, reducing the visibility of the process to the user. This may further allow different subsets to be used for different drive response characteristics, as different subsets may be more representative of the entire array for certain drive response characteristics.
Although this can help maintain the drive scheme voltages closer to their desired values, the data in the look up table 824 may contain some inaccurate values, and in addition, the actual values for VA50+, VA50−, VR50+ and VR50− for the display array as a function of temperature may change over time. To account for this, the system of
Referring now to
At block 912, a frame of image data is written to the display array. At block 914 one of the set of representative lines is selected. Also, one of the response characteristics is selected for evaluation. For example, a representative red line may be selected, and VR50+ for red may be selected for measurement. The current value in the look up table for this parameter, in this case VR50+ for red at the current temperature is retrieved and a test voltage is selected that will place this voltage across the display elements of the selected line. This test voltage is applied (after actuating all the elements since a VR parameter is being measured) to the selected line. The segments are modulated as described above at block 916 and the integrator output is measured as a measure of the capacitance of the line at that applied voltage. If the selected parameter VR50+ for red from the look up table is accurate, the integrator output will be at or very close to the known (Vmin+Vmax)/2 for that line. A suitable threshold may be defined to decide whether the integrator output is close enough to the known (Vmin+Vmax)/2 to consider the current value accurate, for example, within about 10%, or within about 1% of the desired (Vmax Vmin)/2 target value. At decision block 920 it is determined whether the integrator output is within the desired range. If it is, the method may proceed to block 922 where the next line and response characteristic are selected for use in the next maintenance mode routine. From block 922, the method may exit the maintenance mode at block 924.
If it is determined at decision block 920 that the integrator output is too far above or below the known value for (Vmin+Vmax)/2, then the test voltage to be applied next to the selected line may be increased or decreased depending on the integrator measurement by a certain amount, such as 50-100 mV at block 926. Then, at block 928 image data is again written to the display array. Blocks 914, 916, 918, and 920 are then essentially repeated at blocks 930, 932, 934, and 936 with the new test voltage, and the integrator output is again compared to the known (Vmin+Vmax)/2. If the integrator output is still not within the desired range, the method loops back to block 926, where another test voltage adjustment is made and tested. After some repetitions of this loop, the correct test voltage that produces an integrator output close to (Vmin+Vmax)/2 is obtained, and the method proceeds to block 938, where a new VR50+ is derived from the test voltage and the look up table is updated with the new value.
In this case, because the method has determined that the first value checked was in error, the method will proceed to check all of the response characteristics, and at decision block 940 will determine that at this stage not all parameters VA50+, VA50−, VR50+, and VR50− for all colors are within range. The method will then proceed to block 942 and select a new line and new response characteristic to check, e.g. the method may now select a green line, and test for the accuracy of the current look up table value for VA50+. The method then loops back to block 928, writes another frame of image data, and performs the illustrated test protocol for the new line and new response characteristic. This will be repeated until all response characteristics for all colors have been measured and updated where necessary. For a display with three colors and four response characteristics VA50+, VA50−, VR50+ and VR50− there will be twelve total iterations of selecting lines and response characteristics for test.
This method has several advantages. For each frame of image data written, only one test is performed, so it is very fast, typically less than 2 ms, and invisible to the user. When the user is using the display, and it is being updated at, for example, 15 frames per second, a test of one response characteristic for one line can be performed with each frame update without affecting the use or appearance of the display. In addition, because the look up table is initially populated with at least approximately accurate values and is being continually updated with new values, usually only small corrections need to be made with each run of the maintenance mode routine. This speeds up the process and eliminates the need to perform a binary search for a correct value with each test.
The process of
The display device 40 includes a housing 41, a display 30, an antenna 43, a speaker 45, an input device 48, and a microphone 46. The housing 41 can be formed from any of a variety of manufacturing processes, including injection molding, and vacuum forming. In addition, the housing 41 may be made from any of a variety of materials, including, but not limited to: plastic, metal, glass, rubber, and ceramic, or a combination thereof. The housing 41 can include removable portions (not shown) that may be interchanged with other removable portions of different color, or containing different logos, pictures, or symbols.
The display 30 may be any of a variety of displays, including a bi-stable or analog display, as described herein. The display 30 also can be configured to include a flat-panel display, such as plasma, EL, OLED, STN LCD, or TFT LCD, or a non-flat-panel display, such as a CRT or other tube device. In addition, the display 30 can include an interferometric modulator display, as described herein.
The components of the display device 40 are schematically illustrated in
The network interface 27 includes the antenna 43 and the transceiver 47 so that the display device 40 can communicate with one or more devices over a network. The network interface 27 also may have some processing capabilities to relieve, e.g., data processing requirements of the processor 21. The antenna 43 can transmit and receive signals. In some implementations, the antenna 43 transmits and receives RF signals according to the IEEE 16.11 standard, including IEEE 16.11(a), (b), or (g), or the IEEE 802.11 standard, including IEEE 802.11a, b, g or n. In some other implementations, the antenna 43 transmits and receives RF signals according to the BLUETOOTH standard. In the case of a cellular telephone, the antenna 43 is designed to receive code division multiple access (CDMA), frequency division multiple access (FDMA), time division multiple access (TDMA), Global System for Mobile communications (GSM), GSM/General Packet Radio Service (GPRS), Enhanced Data GSM Environment (EDGE), Terrestrial Trunked Radio (TETRA), Wideband-CDMA (W-CDMA), Evolution Data Optimized (EV-DO), 1xEV-DO, EV-DO Rev A, EV-DO Rev B, High Speed Packet Access (HSPA), High Speed Downlink Packet Access (HSDPA), High Speed Uplink Packet Access (HSUPA), Evolved High Speed Packet Access (HSPA+), Long Term Evolution (LTE), AMPS, or other known signals that are used to communicate within a wireless network, such as a system utilizing 3G or 4G technology. The transceiver 47 can pre-process the signals received from the antenna 43 so that they may be received by and further manipulated by the processor 21. The transceiver 47 also can process signals received from the processor 21 so that they may be transmitted from the display device 40 via the antenna 43.
In some implementations, the transceiver 47 can be replaced by a receiver. In addition, the network interface 27 can be replaced by an image source, which can store or generate image data to be sent to the processor 21. The processor 21 can control the overall operation of the display device 40. The processor 21 receives data, such as compressed image data from the network interface 27 or an image source, and processes the data into raw image data or into a format that is readily processed into raw image data. The processor 21 can send the processed data to the driver controller 29 or to the frame buffer 28 for storage. Raw data typically refers to the information that identifies the image characteristics at each location within an image. For example, such image characteristics can include color, saturation, and gray-scale level.
The processor 21 can include a microcontroller, CPU, or logic unit to control operation of the display device 40. The conditioning hardware 52 may include amplifiers and filters for transmitting signals to the speaker 45, and for receiving signals from the microphone 46. The conditioning hardware 52 may be discrete components within the display device 40, or may be incorporated within the processor 21 or other components.
The driver controller 29 can take the raw image data generated by the processor 21 either directly from the processor 21 or from the frame buffer 28 and can re-format the raw image data appropriately for high speed transmission to the array driver 22. In some implementations, the driver controller 29 can re-format the raw image data into a data flow having a raster-like format, such that it has a time order suitable for scanning across the display array 30. Then the driver controller 29 sends the formatted information to the array driver 22. Although a driver controller 29, such as an LCD controller, is often associated with the system processor 21 as a stand-alone Integrated Circuit (IC), such controllers may be implemented in many ways. For example, controllers may be embedded in the processor 21 as hardware, embedded in the processor 21 as software, or fully integrated in hardware with the array driver 22.
The array driver 22 can receive the formatted information from the driver controller 29 and can re-format the video data into a parallel set of waveforms that are applied many times per second to the hundreds, and sometimes thousands (or more), of leads coming from the display's x-y matrix of pixels.
In some implementations, the driver controller 29, the array driver 22, and the display array 30 are appropriate for any of the types of displays described herein. For example, the driver controller 29 can be a conventional display controller or a bi-stable display controller (e.g., an IMOD controller). Additionally, the array driver 22 can be a conventional driver or a bi-stable display driver (e.g., an IMOD display driver). Moreover, the display array 30 can be a conventional display array or a bi-stable display array (e.g., a display including an array of IMODs). In some implementations, the driver controller 29 can be integrated with the array driver 22. Such an implementation is common in highly integrated systems such as cellular phones, watches and other small-area displays.
In some implementations, the input device 48 can be configured to allow, e.g., a user to control the operation of the display device 40. The input device 48 can include a keypad, such as a QWERTY keyboard or a telephone keypad, a button, a switch, a rocker, a touch-sensitive screen, or a pressure- or heat-sensitive membrane. The microphone 46 can be configured as an input device for the display device 40. In some implementations, voice commands through the microphone 46 can be used for controlling operations of the display device 40.
The power supply 50 can include a variety of energy storage devices as are well known in the art. For example, the power supply 50 can be a rechargeable battery, such as a nickel-cadmium battery or a lithium-ion battery. The power supply 50 also can be a renewable energy source, a capacitor, or a solar cell, including a plastic solar cell or solar-cell paint. The power supply 50 also can be configured to receive power from a wall outlet.
In some implementations, control programmability resides in the driver controller 29 which can be located in several places in the electronic display system. In some other implementations, control programmability resides in the array driver 22. The above-described optimization may be implemented in any number of hardware and/or software components and in various configurations.
The various illustrative logics, logical blocks, modules, circuits and algorithm steps described in connection with the implementations disclosed herein may be implemented as electronic hardware, computer software, or combinations of both. The interchangeability of hardware and software has been described generally, in terms of functionality, and illustrated in the various illustrative components, blocks, modules, circuits and steps described above. Whether such functionality is implemented in hardware or software depends upon the particular application and design constraints imposed on the overall system.
The hardware and data processing apparatus used to implement the various illustrative logics, logical blocks, modules and circuits described in connection with the aspects disclosed herein may be implemented or performed with a general purpose single- or multi-chip processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, or, any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration. In some implementations, particular steps and methods may be performed by circuitry that is specific to a given function.
In one or more aspects, the functions described may be implemented in hardware, digital electronic circuitry, computer software, firmware, including the structures disclosed in this specification and their structural equivalents thereof, or in any combination thereof. Implementations of the subject matter described in this specification also can be implemented as one or more computer programs, i.e., one or more modules of computer program instructions, encoded on a computer storage media for execution by, or to control the operation of, data processing apparatus.
If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. The steps of a method or algorithm disclosed herein may be implemented in a processor-executable software module which may reside on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that can be enabled to transfer a computer program from one place to another. A storage media may be any available media that may be accessed by a computer. By way of example, and not limitation, such computer-readable media may include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that may be used to store desired program code in the form of instructions or data structures and that may be accessed by a computer. Also, any connection can be properly termed a computer-readable medium. Disk and disc, as used herein, includes compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk, and blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media. Additionally, the operations of a method or algorithm may reside as one or any combination or set of codes and instructions on a machine readable medium and computer-readable medium, which may be incorporated into a computer program product.
Various modifications to the implementations described in this disclosure may be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other implementations without departing from the spirit or scope of this disclosure. Thus, the claims are not intended to be limited to the implementations shown herein, but are to be accorded the widest scope consistent with this disclosure, the principles and the novel features disclosed herein. The word “exemplary” is used exclusively herein to mean “serving as an example, instance, or illustration.” Any implementation described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other implementations. Additionally, a person having ordinary skill in the art will readily appreciate, the terms “upper” and “lower” are sometimes used for ease of describing the figures, and indicate relative positions corresponding to the orientation of the figure on a properly oriented page, and may not reflect the proper orientation of the IMOD as implemented.
Certain features that are described in this specification in the context of separate implementations also can be implemented in combination in a single implementation. Conversely, various features that are described in the context of a single implementation also can be implemented in multiple implementations separately or in any suitable subcombination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination.
Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. Further, the drawings may schematically depict one more example processes in the form of a flow diagram. However, other operations that are not depicted can be incorporated in the example processes that are schematically illustrated. For example, one or more additional operations can be performed before, after, simultaneously, or between any of the illustrated operations. In certain circumstances, multitasking and parallel processing may be advantageous. Moreover, the separation of various system components in the implementations described above should not be understood as requiring such separation in all implementations, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products. Additionally, other implementations are within the scope of the following claims. In some cases, the actions recited in the claims can be performed in a different order and still achieve desirable results.
This disclosure claims priority under 35 U.S.C. §119(e) to U.S. Provisional Patent Application No. 61/380,187, filed Sep. 3, 2010, which is hereby incorporated by reference in its entirety.
| Number | Date | Country | |
|---|---|---|---|
| 61380187 | Sep 2010 | US |
