Patent Grant
11256657
Embodiments relate to dynamic control of an interconnect.
Modern processors are typically formed of cores and additional processing circuitry. Various interconnection structures are used to couple cores and other circuitry. Area growth of processing circuitry creates frequency challenges in the interconnect structure, across its entire operating voltage range. There is an increasing gap between operating characteristics (e.g., voltage and frequency as identified in frequency/voltage (F/V) curves) between interconnect communication paths and logic of the interconnect. A F/V curve for interconnect communication paths can limit operating voltage, thus forcing the entire interconnect to operate at a non-optimal power profile, where this gap increases at higher voltages. Since the interconnect communication paths may be a small component of the entire interconnect, it is not optimal to let it define the power profile of the interconnect. With current techniques in power constrained environments, operating an interconnect at an artificially high voltage causes performance loss.
In various embodiments, an interconnect structure includes circuitry to dynamically configure controllable latencies on the interconnect. More specifically, in embodiments one or more pipe stages may be dynamic added into or removed from communication paths of the interconnect. Such dynamic update to interconnect structures may occur in the context of a performance state change process. It is also possible to dynamically update pipe stage operation in this context even if voltage and/or frequency does not change. While embodiments herein are described in the context of a mesh interconnect, understand that the techniques are applicable to other interconnect structures.
In an embodiment, for high frequency non-mesh latency sensitive workloads, such pipe stages are added, and at low frequency they may be dynamically removed under power management (PM) control. In this way, embodiments enable performance states of interconnect communication paths to track performance states of logic of the interconnect. That is, embodiments enable an interconnect F/V curve to track a scalable coherent fabric (SCF) IP F/V curve for mesh stops and related logic without increasing area and power requirements. With embodiments, a mesh F/V curve is optimized to not be a limiter as compared to a SCF IP F/V curve. For latency critical hops on a fabric, additional pipe stages may be inserted, e.g., at a pre-determined point on the F/V curve.
In an embodiment, a mesh fabric is a combination of horizontal and vertical ring fabrics. With this arrangement, there is flexibility to stay on mesh fabric or IP F/V curves at any given voltage, which in turn enables a dynamic choice between low latency fabric operation at higher power, or power savings at higher latency fabric operation. In addition, mesh bandwidth may be increased at lower voltage based on workload needs. Power savings may be achieved by enabling higher frequency operation at the same voltage. By enabling a higher bandwidth on a mesh at a lower voltage, efficiency of certain workloads like machine learning workloads increases, where mesh bandwidth and power are both important.
Although the following embodiments are described with reference to energy conservation and energy efficiency in specific integrated circuits, such as in computing platforms or processors, other embodiments are applicable to other types of integrated circuits and logic devices. Similar techniques and teachings of embodiments described herein may be applied to other types of circuits or semiconductor devices that may also benefit from better energy efficiency and energy conservation. For example, the disclosed embodiments are not limited to any particular type of computer systems. That is, disclosed embodiments can be used in many different system types, ranging from server computers (e.g., tower, rack, blade, micro-server and so forth), communications systems, storage systems, desktop computers of any configuration, laptop, notebook, and tablet computers (including 2:1 tablets, phablets and so forth), and may be also used in other devices, such as handheld devices, systems on chip (SoCs), and embedded applications. Some examples of handheld devices include cellular phones such as smartphones, Internet protocol devices, digital cameras, personal digital assistants (PDAs), and handheld PCs. Embedded applications may typically include a microcontroller, a digital signal processor (DSP), network computers (NetPC), set-top boxes, network hubs, wide area network (WAN) switches, wearable devices, or any other system that can perform the functions and operations taught below. More so, embodiments may be implemented in mobile terminals having standard voice functionality such as mobile phones, smartphones and phablets, and/or in non-mobile terminals without a standard wireless voice function communication capability, such as many wearables, tablets, notebooks, desktops, micro-servers, servers and so forth. Moreover, the apparatuses, methods, and systems described herein are not limited to physical computing devices, but may also relate to software optimizations for energy conservation and efficiency. As will become readily apparent in the description below, the embodiments of methods, apparatuses, and systems described herein (whether in reference to hardware, firmware, software, or a combination thereof) are vital to a ‘green technology’ future, such as for power conservation and energy efficiency in products that encompass a large portion of the US economy.
Referring now to
As seen, processor 110 may be a single die processor including multiple cores 120a-120n. In addition, each core may be associated with an integrated voltage regulator (IVR) 125a-125n which receives the primary regulated voltage and generates an operating voltage to be provided to one or more agents of the processor associated with the IVR. Accordingly, an IVR implementation may be provided to allow for fine-grained control of voltage and thus power and performance of each individual core. As such, each core can operate at an independent voltage and frequency, enabling great flexibility and affording wide opportunities for balancing power consumption with performance. In some embodiments, the use of multiple IVRs enables the grouping of components into separate power planes, such that power is regulated and supplied by the IVR to only those components in the group. During power management, a given power plane of one IVR may be powered down or off when the processor is placed into a certain low power state, while another power plane of another IVR remains active, or fully powered.
Still referring to
Also shown is a power control unit (PCU) 138, which may include hardware, software and/or firmware to perform power management operations with regard to processor 110. As seen, PCU 138 provides control information to external voltage regulator 160 via a digital interface to cause the voltage regulator to generate the appropriate regulated voltage. PCU 138 also provides control information to IVRs 125 via another digital interface to control the operating voltage generated (or to cause a corresponding IVR to be disabled in a low power mode). In various embodiments, PCU 138 may include a variety of power management logic units to perform hardware-based power management. Such power management may be wholly processor controlled (e.g., by various processor hardware, and which may be triggered by workload and/or power, thermal or other processor constraints) and/or the power management may be performed responsive to external sources (such as a platform or management power management source or system software).
Furthermore, while
While not shown for ease of illustration, understand that additional components may be present within processor 110 such as additional control circuitry, and other components such as internal memories, e.g., one or more levels of a cache memory hierarchy and so forth. Furthermore, while shown in the implementation of
Note that the power management techniques described herein may be independent of and complementary to an operating system (OS)-based power management (OSPM) mechanism. According to one example OSPM technique, a processor can operate at various performance states or levels, so-called P-states, namely from P0 to PN. In general, the P1 performance state may correspond to the highest guaranteed performance state that can be requested by an OS. In addition to this P1 state, the OS can further request a higher performance state, namely a P0 state. This P0 state may thus be an opportunistic or turbo mode state in which, when power and/or thermal budget is available, processor hardware can configure the processor or at least portions thereof to operate at a higher than guaranteed frequency. In many implementations a processor can include multiple so-called bin frequencies above the P1 guaranteed maximum frequency, exceeding to a maximum peak frequency of the particular processor, as fused or otherwise written into the processor during manufacture. In addition, according to one OSPM mechanism, a processor can operate at various power states or levels. With regard to power states, an OSPM mechanism may specify different power consumption states, generally referred to as C-states, C0, C1 to Cn states. When a core is active, it runs at a C0 state, and when the core is idle it may be placed in a core low power state, also called a core non-zero C-state (e.g., C1-C6 states), with each C-state being at a lower power consumption level (such that C6 is a deeper low power state than C1, and so forth).
Understand that many different types of power management techniques may be used individually or in combination in different embodiments. As representative examples, a power controller may control the processor to be power managed by some form of dynamic voltage frequency scaling (DVFS) in which an operating voltage and/or operating frequency of one or more cores or other processor logic may be dynamically controlled to reduce power consumption in certain situations. In an example, DVFS may be performed using Enhanced Intel SpeedStep™ technology available from Intel Corporation, Santa Clara, Calif., to provide optimal performance at a lowest power consumption level. In another example, DVFS may be performed using Intel TurboBoost™ technology to enable one or more cores or other compute engines to operate at a higher than guaranteed operating frequency based on conditions (e.g., workload and availability).
Embodiments can be implemented in processors for various markets including server processors, desktop processors, mobile processors and so forth. Referring now to
In addition, by interfaces 250a0-250n, connection can be made to various off-chip components such as peripheral devices, mass storage and so forth. While shown with this particular implementation in the embodiment of
Referring now to
In general, each core 310 may further include low level caches in addition to various execution units and additional processing elements. In turn, the various cores may be coupled to each other and to a shared cache memory formed of a plurality of units of a last level cache (LLC) 3400-340n. In various embodiments, LLC 340 may be shared amongst the cores and the graphics engine, as well as various media processing circuitry. As seen, a ring interconnect 330 thus couples the cores together, and provides interconnection between the cores, graphics domain 320 and system agent circuitry 350. In one embodiment, interconnect 330 can be part of the core domain. However in other embodiments the ring interconnect can be of its own domain.
As further seen, system agent domain 350 may include display controller 352 which may provide control of and an interface to an associated display. As further seen, system agent domain 350 may include a power control unit 355 which can include logic to perform the power management techniques described herein. In the embodiment shown, power control unit 355 includes an interconnect update control circuit 358, which may dynamically control routing of communications through an interconnect, e.g., by way of imposition or removal of pipe stages, as described herein.
As further seen in
Referring to
In one embodiment, a processing element refers to hardware or logic to support a software thread. Examples of hardware processing elements include: a thread unit, a thread slot, a thread, a process unit, a context, a context unit, a logical processor, a hardware thread, a core, and/or any other element, which is capable of holding a state for a processor, such as an execution state or architectural state. In other words, a processing element, in one embodiment, refers to any hardware capable of being independently associated with code, such as a software thread, operating system, application, or other code. A physical processor typically refers to an integrated circuit, which potentially includes any number of other processing elements, such as cores or hardware threads.
A core often refers to logic located on an integrated circuit capable of maintaining an independent architectural state, wherein each independently maintained architectural state is associated with at least some dedicated execution resources. In contrast to cores, a hardware thread typically refers to any logic located on an integrated circuit capable of maintaining an independent architectural state, wherein the independently maintained architectural states share access to execution resources. As can be seen, when certain resources are shared and others are dedicated to an architectural state, the line between the nomenclature of a hardware thread and core overlaps. Yet often, a core and a hardware thread are viewed by an operating system as individual logical processors, where the operating system is able to individually schedule operations on each logical processor.
Physical processor 400, as illustrated in
Yet to further the discussion, the functional units illustrated in core 401 are described in further detail below, as the units in core 402 operate in a similar manner. As depicted, core 401 includes two hardware threads 401a and 401b, which may also be referred to as hardware thread slots 401a and 401b. Therefore, software entities, such as an operating system, in one embodiment potentially view processor 400 as four separate processors, i.e., four logical processors or processing elements capable of executing four software threads concurrently. As alluded to above, a first thread is associated with architecture state registers 401a, a second thread is associated with architecture state registers 401b, a third thread may be associated with architecture state registers 402a, and a fourth thread may be associated with architecture state registers 402b. Here, each of the architecture state registers (401a, 401b, 402a, and 402b) may be referred to as processing elements, thread slots, or thread units, as described above. As illustrated, architecture state registers 401a are replicated in architecture state registers 401b, so individual architecture states/contexts are capable of being stored for logical processor 401a and logical processor 401b. In core 401, other smaller resources, such as instruction pointers and renaming logic in allocator and renamer block 430 may also be replicated for threads 401a and 401b. Some resources, such as re-order buffers in reorder/retirement unit 435, ILTB 420, load/store buffers, and queues may be shared through partitioning. Other resources, such as general purpose internal registers, page-table base register(s), low-level data-cache and data-TLB 415, execution unit(s) 440, and portions of out-of-order unit 435 are potentially fully shared.
Processor 400 often includes other resources, which may be fully shared, shared through partitioning, or dedicated by/to processing elements. In
Core 401 further includes decode module 425 coupled to fetch unit 420 to decode fetched elements. Fetch logic, in one embodiment, includes individual sequencers associated with thread slots 401a, 401b, respectively. Usually core 401 is associated with a first ISA, which defines/specifies instructions executable on processor 400. Often machine code instructions that are part of the first ISA include a portion of the instruction (referred to as an opcode), which references/specifies an instruction or operation to be performed. Decode logic 425 includes circuitry that recognizes these instructions from their opcodes and passes the decoded instructions on in the pipeline for processing as defined by the first ISA. For example, decoders 425, in one embodiment, include logic designed or adapted to recognize specific instructions, such as transactional instruction. As a result of the recognition by decoders 425, the architecture or core 401 takes specific, predefined actions to perform tasks associated with the appropriate instruction. It is important to note that any of the tasks, blocks, operations, and methods described herein may be performed in response to a single or multiple instructions; some of which may be new or old instructions.
In one example, allocator and renamer block 430 includes an allocator to reserve resources, such as register files to store instruction processing results. However, threads 401a and 401b are potentially capable of out-of-order execution, where allocator and renamer block 430 also reserves other resources, such as reorder buffers to track instruction results. Unit 430 may also include a register renamer to rename program/instruction reference registers to other registers internal to processor 400. Reorder/retirement unit 435 includes components, such as the reorder buffers mentioned above, load buffers, and store buffers, to support out-of-order execution and later in-order retirement of instructions executed out-of-order.
Scheduler and execution unit(s) block 440, in one embodiment, includes a scheduler unit to schedule instructions/operation on execution units. For example, a floating point instruction is scheduled on a port of an execution unit that has an available floating point execution unit. Register files associated with the execution units are also included to store information instruction processing results. Exemplary execution units include a floating point execution unit, an integer execution unit, a jump execution unit, a load execution unit, a store execution unit, and other known execution units.
Lower level data cache and data translation buffer (D-TLB) 450 are coupled to execution unit(s) 440. The data cache is to store recently used/operated on elements, such as data operands, which are potentially held in memory coherency states. The D-TLB is to store recent virtual/linear to physical address translations. As a specific example, a processor may include a page table structure to break physical memory into a plurality of virtual pages.
Here, cores 401 and 402 share access to higher-level or further-out cache 410, which is to cache recently fetched elements. Note that higher-level or further-out refers to cache levels increasing or getting further away from the execution unit(s). In one embodiment, higher-level cache 410 is a last-level data cache—last cache in the memory hierarchy on processor 400—such as a second or third level data cache. However, higher level cache 410 is not so limited, as it may be associated with or includes an instruction cache. A trace cache—a type of instruction cache—instead may be coupled after decoder 425 to store recently decoded traces.
In the depicted configuration, processor 400 also includes bus interface module 405 and a power controller 460, which may perform power management in accordance with an embodiment of the present invention. In this scenario, bus interface 405 is to communicate with devices external to processor 400, such as system memory and other components.
A memory controller 470 may interface with other devices such as one or many memories. In an example, bus interface 405 includes a ring interconnect with a memory controller for interfacing with a memory and a graphics controller for interfacing with a graphics processor. In an SoC environment, even more devices, such as a network interface, coprocessors, memory, graphics processor, and any other known computer devices/interface may be integrated on a single die or integrated circuit to provide small form factor with high functionality and low power consumption.
Referring now to
As seen in
Coupled between front end units 510 and execution units 520 is an out-of-order (OOO) engine 515 that may be used to receive the micro-instructions and prepare them for execution. More specifically OOO engine 515 may include various buffers to re-order micro-instruction flow and allocate various resources needed for execution, as well as to provide renaming of logical registers onto storage locations within various register files such as register file 530 and extended register file 535. Register file 530 may include separate register files for integer and floating point operations. Extended register file 535 may provide storage for vector-sized units, e.g., 256 or 512 bits per register. For purposes of configuration, control, and additional operations, a set of machine specific registers (MSRs) 538 may also be present and accessible to various logic within core 500 (and external to the core). Note that for purposes of supporting multi-threading, multiple sets of registers within various register files may be provided such that they may be used concurrently by the different threads. Note however that the remaining structures of core 500, including front end units 510 and execution units 520, are not replicated.
Various resources may be present in execution units 520, including, for example, various integer, floating point, and single instruction multiple data (SIMD) logic units, among other specialized hardware. For example, such execution units may include one or more arithmetic logic units (ALUs) 522 and one or more vector execution units 524, among other such execution units.
Results from the execution units may be provided to retirement logic, namely a reorder buffer (ROB) 540. More specifically, ROB 540 may include various arrays and logic to receive information associated with instructions that are executed. This information is then examined by ROB 540 to determine whether the instructions can be validly retired and result data committed to the architectural state of the processor, or whether one or more exceptions occurred that prevent a proper retirement of the instructions. Of course, ROB 540 may handle other operations associated with retirement.
As shown in
Referring now to
A floating point pipeline 630 includes a floating point register file 632 which may include a plurality of architectural registers of a given bit with such as 128, 256 or 512 bits. Pipeline 630 includes a floating point scheduler 634 to schedule instructions for execution on one of multiple execution units of the pipeline. In the embodiment shown, such execution units include an ALU 635, a shuffle unit 636, and a floating point adder 638. In turn, results generated in these execution units may be provided back to buffers and/or registers of register file 632. Of course understand while shown with these few example execution units, additional or different floating point execution units may be present in another embodiment.
An integer pipeline 640 also may be provided. In the embodiment shown, pipeline 640 includes an integer register file 642 which may include a plurality of architectural registers of a given bit with such as 128 or 256 bits. Pipeline 640 includes an integer scheduler 644 to schedule instructions for execution on one of multiple execution units of the pipeline. In the embodiment shown, such execution units include an ALU 645, a shifter unit 646, and a jump execution unit 648. In turn, results generated in these execution units may be provided back to buffers and/or registers of register file 642. Of course understand while shown with these few example execution units, additional or different integer execution units may be present in another embodiment.
A memory execution scheduler 650 may schedule memory operations for execution in an address generation unit 652, which is also coupled to a TLB 654. As seen, these structures may couple to a data cache 660, which may be a L0 and/or L1 data cache that in turn couples to additional levels of a cache memory hierarchy, including an L2 cache memory.
To provide support for out-of-order execution, an allocator/renamer 670 may be provided, in addition to a reorder buffer 680, which is configured to reorder instructions executed out of order for retirement in order. Although shown with this particular pipeline architecture in the illustration of
Note that in a processor having asymmetric cores, such as in accordance with the micro-architectures of
Referring to
With further reference to
Referring to
Also shown in
Decoded instructions may be issued to a given one of multiple execution units. In the embodiment shown, these execution units include one or more integer units 835, a multiply unit 840, a floating point/vector unit 850, a branch unit 860, and a load/store unit 870. In an embodiment, floating point/vector unit 850 may be configured to handle SIMD or vector data of 128 or 256 bits. Still further, floating point/vector execution unit 850 may perform IEEE-754 double precision floating-point operations. The results of these different execution units may be provided to a writeback unit 880. Note that in some implementations separate writeback units may be associated with each of the execution units. Furthermore, understand that while each of the units and logic shown in
Note that in a processor having asymmetric cores, such as in accordance with the micro-architectures of
A processor designed using one or more cores having pipelines as in any one or more of
In the high level view shown in
Each core unit 910 may also include an interface such as a bus interface unit to enable interconnection to additional circuitry of the processor. In an embodiment, each core unit 910 couples to a coherent fabric that may act as a primary cache coherent on-die interconnect that in turn couples to a memory controller 935. In turn, memory controller 935 controls communications with a memory such as a DRAM (not shown for ease of illustration in
In addition to core units, additional processing engines are present within the processor, including at least one graphics unit 920 which may include one or more graphics processing units (GPUs) to perform graphics processing as well as to possibly execute general purpose operations on the graphics processor (so-called GPGPU operation). In addition, at least one image signal processor 925 may be present. Signal processor 925 may be configured to process incoming image data received from one or more capture devices, either internal to the SoC or off-chip.
Other accelerators also may be present. In the illustration of
Each of the units may have its power consumption controlled via a power manager 940, which may include control logic to perform various power management techniques and the selective MT configurable control described herein.
In some embodiments, SoC 900 may further include a non-coherent fabric coupled to the coherent fabric to which various peripheral devices may couple. One or more interfaces 960a0-960d enable communication with one or more off-chip devices. Such communications may be via a variety of communication protocols such as PCIe™, GPIO, USB, I2C, UART, MIPI, SDIO, DDR, SPI, HDMI, among other types of communication protocols. Although shown at this high level in the embodiment of
Referring now to
As seen in
With further reference to
As seen, the various domains couple to a coherent interconnect 1040, which in an embodiment may be a cache coherent interconnect fabric that in turn couples to an integrated memory controller 1050. Coherent interconnect 1040 may include a shared cache memory, such as an L3 cache, in some examples. In an embodiment, memory controller 1050 may be a direct memory controller to provide for multiple channels of communication with an off-chip memory, such as multiple channels of a DRAM (not shown for ease of illustration in
In different examples, the number of the core domains may vary. For example, for a low power SoC suitable for incorporation into a mobile computing device, a limited number of core domains such as shown in
In yet other embodiments, a greater number of core domains, as well as additional optional IP logic may be present, in that an SoC can be scaled to higher performance (and power) levels for incorporation into other computing devices, such as desktops, servers, high performance computing systems, base stations forth. As one such example, 4 core domains each having a given number of out-of-order cores may be provided. Still further, in addition to optional GPU support (which as an example may take the form of a GPGPU), one or more accelerators to provide optimized hardware support for particular functions (e.g., web serving, network processing, switching or so forth) also may be provided. In addition, an input/output interface may be present to couple such accelerators to off-chip components.
Referring now to
In turn, a GPU domain 1120 is provided to perform advanced graphics processing in one or more GPUs to handle graphics and compute APIs. A DSP unit 1130 may provide one or more low power DSPs for handling low-power multimedia applications such as music playback, audio/video and so forth, in addition to advanced calculations that may occur during execution of multimedia instructions. In turn, a communication unit 1140 may include various components to provide connectivity via various wireless protocols, such as cellular communications (including 3G/4G LTE), wireless local area protocols such as Bluetooth™ IEEE 802.11, and so forth.
Still further, a multimedia processor 1150 may be used to perform capture and playback of high definition video and audio content, including processing of user gestures. A sensor unit 1160 may include a plurality of sensors and/or a sensor controller to interface to various off-chip sensors present in a given platform. An image signal processor 1170 may be provided with one or more separate ISPs to perform image processing with regard to captured content from one or more cameras of a platform, including still and video cameras.
A display processor 1180 may provide support for connection to a high definition display of a given pixel density, including the ability to wirelessly communicate content for playback on such display. Still further, a location unit 1190 may include a GPS receiver with support for multiple GPS constellations to provide applications highly accurate positioning information obtained using as such GPS receiver. Understand that while shown with this particular set of components in the example of
Referring now to
In turn, application processor 1210 can couple to a user interface/display 1220, e.g., a touch screen display. In addition, application processor 1210 may couple to a memory system including a non-volatile memory, namely a flash memory 1230 and a system memory, namely a dynamic random access memory (DRAM) 1235. As further seen, application processor 1210 further couples to a capture device 1240 such as one or more image capture devices that can record video and/or still images.
Still referring to
As further illustrated, a near field communication (NFC) contactless interface 1260 is provided that communicates in a NFC near field via an NFC antenna 1265. While separate antennae are shown in
A PMIC 1215 couples to application processor 1210 to perform platform level power management. To this end, PMIC 1215 may issue power management requests to application processor 1210 to enter certain low power states as desired. Furthermore, based on platform constraints, PMIC 1215 may also control the power level of other components of system 1200.
To enable communications to be transmitted and received, various circuitry may be coupled between baseband processor 1205 and an antenna 1290. Specifically, a radio frequency (RF) transceiver 1270 and a wireless local area network (WLAN) transceiver 1275 may be present. In general, RF transceiver 1270 may be used to receive and transmit wireless data and calls according to a given wireless communication protocol such as 3G or 4G wireless communication protocol such as in accordance with a code division multiple access (CDMA), global system for mobile communication (GSM), long term evolution (LTE) or other protocol. In addition a GPS sensor 1280 may be present. Other wireless communications such as receipt or transmission of radio signals, e.g., AM/FM and other signals may also be provided. In addition, via WLAN transceiver 1275, local wireless communications can also be realized.
Referring now to
A variety of devices may couple to SoC 1310. In the illustration shown, a memory subsystem includes a flash memory 1340 and a DRAM 1345 coupled to SoC 1310. In addition, a touch panel 1320 is coupled to the SoC 1310 to provide display capability and user input via touch, including provision of a virtual keyboard on a display of touch panel 1320. To provide wired network connectivity, SoC 1310 couples to an Ethernet interface 1330. A peripheral hub 1325 is coupled to SoC 1310 to enable interfacing with various peripheral devices, such as may be coupled to system 1300 by any of various ports or other connectors.
In addition to internal power management circuitry and functionality within SoC 1310, a PMIC 1380 is coupled to SoC 1310 to provide platform-based power management, e.g., based on whether the system is powered by a battery 1390 or AC power via an AC adapter 1395. In addition to this power source-based power management, PMIC 1380 may further perform platform power management activities based on environmental and usage conditions. Still further, PMIC 1380 may communicate control and status information to SoC 1310 to cause various power management actions within SoC 1310.
Still referring to
As further illustrated, a plurality of sensors 1360 may couple to SoC 1310. These sensors may include various accelerometer, environmental and other sensors, including user gesture sensors. Finally, an audio codec 1365 is coupled to SoC 1310 to provide an interface to an audio output device 1370. Of course understand that while shown with this particular implementation in
Referring now to
Processor 1410, in one embodiment, communicates with a system memory 1415. As an illustrative example, the system memory 1415 is implemented via multiple memory devices or modules to provide for a given amount of system memory.
To provide for persistent storage of information such as data, applications, one or more operating systems and so forth, a mass storage 1420 may also couple to processor 1410. In various embodiments, to enable a thinner and lighter system design as well as to improve system responsiveness, this mass storage may be implemented via a SSD or the mass storage may primarily be implemented using a hard disk drive (HDD) with a smaller amount of SSD storage to act as a SSD cache to enable non-volatile storage of context state and other such information during power down events so that a fast power up can occur on re-initiation of system activities. Also shown in
Various input/output (I/O) devices may be present within system 1400. Specifically shown in the embodiment of
For perceptual computing and other purposes, various sensors may be present within the system and may be coupled to processor 1410 in different manners. Certain inertial and environmental sensors may couple to processor 1410 through a sensor hub 1440, e.g., via an I2C interconnect. In the embodiment shown in
Also seen in
System 1400 can communicate with external devices in a variety of manners, including wirelessly. In the embodiment shown in
As further seen in
In addition, wireless wide area communications, e.g., according to a cellular or other wireless wide area protocol, can occur via a WWAN unit 1456 which in turn may couple to a subscriber identity module (SIM) 1457. In addition, to enable receipt and use of location information, a GPS module 1455 may also be present. Note that in the embodiment shown in
An integrated camera module 1454 can be incorporated in the lid. To provide for audio inputs and outputs, an audio processor can be implemented via a digital signal processor (DSP) 1460, which may couple to processor 1410 via a high definition audio (HDA) link. Similarly, DSP 1460 may communicate with an integrated coder/decoder (CODEC) and amplifier 1462 that in turn may couple to output speakers 1463 which may be implemented within the chassis. Similarly, amplifier and CODEC 1462 can be coupled to receive audio inputs from a microphone 1465 which in an embodiment can be implemented via dual array microphones (such as a digital microphone array) to provide for high quality audio inputs to enable voice-activated control of various operations within the system. Note also that audio outputs can be provided from amplifier/CODEC 1462 to a headphone jack 1464. Although shown with these particular components in the embodiment of
Embodiments may be implemented in many different system types. Referring now to
Still referring to
Furthermore, chipset 1590 includes an interface 1592 to couple chipset 1590 with a high performance graphics engine 1538, by a P-P interconnect 1539. In turn, chipset 1590 may be coupled to a first bus 1516 via an interface 1596. As shown in
The RTL design 1615 or equivalent may be further synthesized by the design facility into a hardware model 1620, which may be in a hardware description language (HDL), or some other representation of physical design data. The HDL may be further simulated or tested to verify the IP core design. The IP core design can be stored for delivery to a third party fabrication facility 1665 using non-volatile memory 1640 (e.g., hard disk, flash memory, or any non-volatile storage medium). Alternately, the IP core design may be transmitted (e.g., via the Internet) over a wired connection 1650 or wireless connection 1660. The fabrication facility 1665 may then fabricate an integrated circuit that is based at least in part on the IP core design. The fabricated integrated circuit can be configured to perform operations in accordance with at least one embodiment described herein.
Referring now to
More specifically as shown in
As illustrated, output signal line 1715 couples to a first input of a selection circuit 1720, which may be implemented as a multiplexer, in an embodiment. As further illustrated, the directly received signal from input signal line 1705 is provided via a bypass path 1730 to another input of selection circuit 1720.
Based on dynamic control, e.g., under control of a control signal received from a power controller, selection circuit 1720 may output the incoming signal via a second output signal line 1725, either with a single cycle latency (as effected using bypass path 1730) or a multi-cycle latency (effected using the signal provided through pipe stage 1710). Understand while shown at this high level in the embodiment of
Referring now to
With reference to the left side of
As further shown on the left hand side of
Further with reference to the left hand side of
Still referring to
Referring now to
As illustrated, method 1900 begins by receiving a pipe drain signal from a power controller (block 1910). This pipe drain signal may be received in the interconnect in response to a determination that a performance state change to the fabric is to occur (and/or where a pipe stage insertion or removal process is to occur). In response to this pipe drain signal, at block 1920 injection of new messages into the interconnect may be blocked. To this end, the interconnect controller may communicate a block signal to mesh stops to prevent their injection of new messages into the fabric.
Thereafter, the fabric may continue to operate at a current frequency to seek to drain messages from the fabric. To this end, pending messages in the interconnect may traverse through the fabric so that they may be sunk into destination mesh stops (assuming sufficient credits exist in such mesh stops to accept these credited messages). In the case of a ring interconnect, the mesh may continue to operate according to the current clock frequency for a plurality of revolutions, e.g., two revolutions. Thus in this case, this first traversal of the fabric for a ring interconnect may be a full revolution on the ring (block 1930). Still with reference to
Still with reference to
At this point when any remaining traffic has been drained into this queue, the performance state change may be performed (block 1960). To this end one or more of an operating voltage and frequency of the fabric can be updated. For purposes of an increase in pipe stages, this performance state change may be to reduce at least the voltage of the fabric. And in the case of removal of such pipe stages, the performance state change may be to cause at least a voltage increase.
In any event, with reference now to
Next at block 1990 bounce traffic may be injected into the non-anti-deadlock slots. Such bounce traffic may be extracted from the drain-replay queue and inserted on the interconnect to allow these messages to drain into the mesh stops associated with their destinations. Finally, at block 1995 injection of new messages into the fabric may be unblocked. Thus at this point, mesh stops are free to inject new messages or other packets onto the fabric. Understand that with an embodiment as in
Referring now to
As illustrated method 2000 begins by determining whether an operating voltage of the interconnect is less than a first threshold (diamond 2010). In an embodiment, this first threshold may correspond to a relatively low operating voltage, such that the interconnect is operating at a low performance level. With this situation, the interconnect may operate with increased latency by inclusion of pipe stage components in the communication path. To this end, control passes to block 2020 where pipe stage circuits of the interconnect may be enabled to insert pipe stage components into the communication path. More specifically as discussed above, e.g., with regard to
Still with reference to
Otherwise, if it is determined at diamond 2040 that the workload exceeds a given workload threshold (or in situations where this determination does not occur), control passes to block 2050 where the pipe stage circuits may be controlled to remove pipe stage components. As such, the power controller may send control signals to the multiplexers or other selection circuits to cause them to pass signals received via bypass paths, rather than signals received through one or more pipe stage components.
With further reference to
Still referring to
In an embodiment, at high level there may be two transition types on the F/V curves: static zones where pipe stages are kept static within these zones and changed across these zones; and at least one dynamic zone, where pipe stages can be changed (across a performance state transition process) within this zone.
Referring now to
As further illustrated in
Both dynamic and leakage power reduce with voltage reduction. Dynamic and leakage power of a circuit as a function of voltage is as follows: dynamic power=CV2F (V: voltage, F: frequency, C: capacitance); and leakage power=IiN, where Ii is a function of voltage (V), and Ii is a sub-threshold leakage. For high voltage operation (Z4), if the workload is sensitive to mesh frequency for low latency and there is power headroom to increase voltage, higher frequency operation is enabled. Therefore in this scenario above threshold Z4, operation is with minimum pipe stages on the mesh.
Embodiments may deliver better power and better mesh fabric bandwidth profile without compromising on latency. Such advantages may be realized as the mesh fabric itself may be a small part of SCF domain power (as fabric data path sequentials may be an extremely small part of total SCF domain sequential/gate count/area). Thus anchoring an entire SCF domain voltage for fabric needs as is conventional is non-optimal. Embodiments remove this dependence and save power at higher voltage. In addition, as the fabric is RC dominated (as compared to core domains), the fabric may operate at higher voltages compared to SCF IP for higher frequency operation as described below. At high voltage, a selection circuit may insert the pipe stage component and making the fabric non-timing critical. Of course these representative values for both the voltage frequency curves and the thresholds are exemplary only and many different values are possible in other embodiments.
The following examples pertain to further embodiments.
In one example, an apparatus includes: a plurality of processing circuits each to execute instructions; and an interconnect to couple the plurality of processing circuits. The interconnect comprises: a pipe stage circuit coupled between a first processing circuit of the plurality of processing circuits and a second processing circuit of the plurality of processing circuits. The pipe stage circuit comprises: a pipe stage component having a first input to receive a signal via the interconnect and a first output to output the signal; and a selection circuit having a first input to receive the signal from the first output of the pipe stage component and a second input to receive the signal via a bypass path, where the selection circuit is dynamically controllable, based on a control signal, to output the signal received from the first output of the pipe stage component or the signal received via the bypass path.
In an example, the selection circuit is to receive the signal from the pipe stage component delayed with respect to the signal received via the bypass path.
In an example, the interconnect comprises: a mesh interconnect having a plurality of mesh stops; and a plurality of pipe stage circuits interposed between at least some of the plurality of mesh stops.
In an example, the plurality of pipe stage circuits are interposed between the at least some of the plurality of mesh stops coupled to a vertical portion of the mesh interconnect, and where a portion of the plurality of mesh stops coupled to a horizontal portion of the mesh interconnect are coupled to each other without interposition of pipe stage circuits.
In an example, the apparatus further comprises a power controller to provide the control signal to the selection circuit based at least in part on an operating voltage of the interconnect.
In an example, the power controller is to provide the control signal to cause the selection circuit to output the signal received from the pipe stage component when the operating voltage of the interconnect is less than a threshold level.
In an example, the power controller is to provide the control signal to cause the selection circuit to output the signal received from the pipe stage component further based on a workload of at least one of the plurality of processing circuits.
In an example, the apparatus further comprises: an interconnect controller; and a queue coupled to the interconnect, where the interconnect controller is to cause one or more messages pending on the interconnect to be stored in the queue prior to a performance state change to the interconnect.
In an example, after the performance state change, the interconnect controller is to cause the queue to output the one or more messages to the interconnect prior to enabling the plurality of processing circuits to inject new messages to the interconnect.
In an example, the pipe stage component is to be dynamically inserted into a communication path of the interconnect when an operating voltage of the interconnect exceeds a threshold level, the pipe stage component comprising a sequential circuit.
In another example, a method comprises: receiving, in a controller of an interconnect of a processor, a pipe drain signal from a power controller of the processor; in response to the pipe drain signal, causing one or more pending messages on the interconnect to be stored in a queue coupled to the interconnect; causing a performance state change to occur to the interconnect; and thereafter causing the one or more pending messages to be drained from the queue and injected onto the interconnect.
In an example, the method further comprises: prior to the performance state change, controlling one or more pipe stage circuits to operate in a single cycle configuration; and after the performance state change, controlling the one or more pipe stage circuits to operate in a multi-cycle configuration.
In an example, the method further comprises: controlling the one or more pipe stage circuits to operate in the single cycle configuration when an operating voltage of the interconnect exceeds a threshold level; and controlling the one or more pipe stage circuits to operate in the multi-cycle configuration when an operating voltage of the interconnect is less than the threshold level.
In an example, the method further comprises performing the performance state change to the interconnect without draining the interconnect of the one or more pending messages.
In an example, the method further comprises: in response to the pipe drain signal, preventing one or more agents coupled to the interconnect from injecting messages onto the interconnect; and enabling the one or more agents to inject the messages onto the interconnect after the one or more messages are drained from the queue.
In an example, the method further comprises: controlling communication path circuitry of the interconnect to operate at a first performance state; and controlling logic circuitry of the interconnect to operate at a second performance, the first performance state lower than the second performance state.
In another example, a computer readable medium including instructions is to perform the method of any of the above examples.
In another example, a computer readable medium including data is to be used by at least one machine to fabricate at least one integrated circuit to perform the method of any one of the above examples.
In another example, an apparatus comprises means for performing the method of any one of the above examples.
In another example, a system includes a system on chip and a system memory coupled to the system on chip. The system on chip comprises a plurality of cores each to execute instructions and a mesh interconnect to couple the plurality of cores. The mesh interconnect comprises: a vertical mesh having a plurality of mesh stops coupled thereto, where a plurality of pipe stage circuits are interposed along the vertical mesh, each of the plurality of pipe stage circuits comprising: a pipe stage component having a first input to receive a signal from the vertical mesh and a first output to output the signal; and a selection circuit having a first input to receive the signal from the first output of the pipe stage component and a second input to receive the signal from the vertical mesh, where the selection circuit is dynamically controllable to output the signal received from the first output of the pipe stage component or the signal received from the vertical mesh; and a horizontal mesh having the plurality of mesh stops coupled thereto. The system on chip further includes a power controller to control the selection circuit based at least in part on an operating voltage of the mesh interconnect.
In an example, the system further comprises a queue coupled to the mesh interconnect to store one or more messages pending on the mesh interconnect prior to a performance state change to the mesh interconnect.
In an example, the power controller is to cause the plurality of pipe stage circuits to operate in a single cycle configuration when the operating voltage of the mesh interconnect exceeds a threshold level, and cause the plurality of pipe stage circuits to operate in a multi-cycle configuration when the operating voltage of the mesh interconnect is less than the threshold level.
In an example, the power controller is to cause the vertical mesh and the horizontal mesh to operate at a first performance state, and cause the plurality of mesh stops to operate at a second performance, the first performance state lower than the second performance state.
Understand that various combinations of the above examples are possible.
Note that the terms “circuit” and “circuitry” are used interchangeably herein. As used herein, these terms and the term “logic” are used to refer to alone or in any combination, analog circuitry, digital circuitry, hard wired circuitry, programmable circuitry, processor circuitry, microcontroller circuitry, hardware logic circuitry, state machine circuitry and/or any other type of physical hardware component. Embodiments may be used in many different types of systems. For example, in one embodiment a communication device can be arranged to perform the various methods and techniques described herein. Of course, the scope of the present invention is not limited to a communication device, and instead other embodiments can be directed to other types of apparatus for processing instructions, or one or more machine readable media including instructions that in response to being executed on a computing device, cause the device to carry out one or more of the methods and techniques described herein.
Embodiments may be implemented in code and may be stored on a non-transitory storage medium having stored thereon instructions which can be used to program a system to perform the instructions. Embodiments also may be implemented in data and may be stored on a non-transitory storage medium, which if used by at least one machine, causes the at least one machine to fabricate at least one integrated circuit to perform one or more operations. Still further embodiments may be implemented in a computer readable storage medium including information that, when manufactured into a SoC or other processor, is to configure the SoC or other processor to perform one or more operations. The storage medium may include, but is not limited to, any type of disk including floppy disks, optical disks, solid state drives (SSDs), compact disk read-only memories (CD-ROMs), compact disk rewritables (CD-RWs), and magneto-optical disks, semiconductor devices such as read-only memories (ROMs), random access memories (RAMs) such as dynamic random access memories (DRAMs), static random access memories (SRAMs), erasable programmable read-only memories (EPROMs), flash memories, electrically erasable programmable read-only memories (EEPROMs), magnetic or optical cards, or any other type of media suitable for storing electronic instructions.
While the present invention has been described with respect to a limited number of embodiments, those skilled in the art will appreciate numerous modifications and variations therefrom. It is intended that the appended claims cover all such modifications and variations as fall within the true spirit and scope of this present invention.
| Number | Name | Date | Kind |
|---|---|---|---|
| 5163153 | Cole et al. | Nov 1992 | A |
| 5522087 | Hsiang | May 1996 | A |
| 5579525 | Suzuki | Nov 1996 | A |
| 5590341 | Matter | Dec 1996 | A |
| 5621250 | Kim | Apr 1997 | A |
| 5931950 | Hsu | Aug 1999 | A |
| 6748546 | Mirov et al. | Jun 2004 | B1 |
| 6792392 | Knight | Sep 2004 | B1 |
| 6823516 | Cooper | Nov 2004 | B1 |
| 6829713 | Cooper et al. | Dec 2004 | B2 |
| 6996728 | Singh | Feb 2006 | B2 |
| 7010708 | Ma | Mar 2006 | B2 |
| 7043649 | Terrell | May 2006 | B2 |
| 7093147 | Farkas et al. | Aug 2006 | B2 |
| 7111179 | Girson et al. | Sep 2006 | B1 |
| 7194643 | Gonzalez et al. | Mar 2007 | B2 |
| 7272730 | Acquaviva et al. | Sep 2007 | B1 |
| 7412615 | Yokota et al. | Aug 2008 | B2 |
| 7434073 | Magklis | Oct 2008 | B2 |
| 7437270 | Song et al. | Oct 2008 | B2 |
| 7454632 | Kardach et al. | Nov 2008 | B2 |
| 7529956 | Stufflebeam | May 2009 | B2 |
| 7539885 | Ma | May 2009 | B2 |
| 7730340 | Hu et al. | Jun 2010 | B2 |
| 10320386 | Ganusov | Jun 2019 | B1 |
| 20010044909 | Oh et al. | Nov 2001 | A1 |
| 20020194509 | Plante et al. | Dec 2002 | A1 |
| 20030014614 | Jarvis | Jan 2003 | A1 |
| 20030061383 | Zilka | Mar 2003 | A1 |
| 20040064752 | Kazachinsky et al. | Apr 2004 | A1 |
| 20040098560 | Storvik et al. | May 2004 | A1 |
| 20040139356 | Ma | Jul 2004 | A1 |
| 20040268166 | Farkas et al. | Dec 2004 | A1 |
| 20050022038 | Kaushik et al. | Jan 2005 | A1 |
| 20050033881 | Yao | Feb 2005 | A1 |
| 20050132238 | Nanja | Jun 2005 | A1 |
| 20060050670 | Hillyard et al. | Mar 2006 | A1 |
| 20060053326 | Naveh | Mar 2006 | A1 |
| 20060059286 | Bertone et al. | Mar 2006 | A1 |
| 20060069936 | Lint et al. | Mar 2006 | A1 |
| 20060117202 | Magklis et al. | Jun 2006 | A1 |
| 20060184287 | Belady et al. | Aug 2006 | A1 |
| 20070005995 | Kardach et al. | Jan 2007 | A1 |
| 20070016817 | Albonesi et al. | Jan 2007 | A1 |
| 20070079294 | Knight | Apr 2007 | A1 |
| 20070106827 | Boatright et al. | May 2007 | A1 |
| 20070156992 | Jahagirdar | Jul 2007 | A1 |
| 20070214342 | Newburn | Sep 2007 | A1 |
| 20070239398 | Song et al. | Oct 2007 | A1 |
| 20070245163 | Lu et al. | Oct 2007 | A1 |
| 20080028240 | Arai et al. | Jan 2008 | A1 |
| 20080250260 | Tomita | Oct 2008 | A1 |
| 20090006871 | Liu et al. | Jan 2009 | A1 |
| 20090138674 | Chang | May 2009 | A1 |
| 20090150695 | Song et al. | Jun 2009 | A1 |
| 20090150696 | Song et al. | Jun 2009 | A1 |
| 20090158061 | Schmitz et al. | Jun 2009 | A1 |
| 20090158067 | Bodas et al. | Jun 2009 | A1 |
| 20090172375 | Rotem et al. | Jul 2009 | A1 |
| 20090172428 | Lee | Jul 2009 | A1 |
| 20090198970 | Emma | Aug 2009 | A1 |
| 20090235105 | Branover et al. | Sep 2009 | A1 |
| 20100111081 | Diab | May 2010 | A1 |
| 20100115309 | Carvalho et al. | May 2010 | A1 |
| 20100146513 | Song | Jun 2010 | A1 |
| 20100161943 | Young Su | Jun 2010 | A1 |
| 20100191997 | Dodeja et al. | Jul 2010 | A1 |
| 20110154090 | Dixon et al. | Jun 2011 | A1 |
| 20120079290 | Kumar | Mar 2012 | A1 |
| 20120084540 | Lichtensteiger | Apr 2012 | A1 |
| 20120246506 | Knight | Sep 2012 | A1 |
| 20130061064 | Ananthakrishnan et al. | Mar 2013 | A1 |
| 20130080803 | Ananthakrishnan et al. | Mar 2013 | A1 |
| 20130080804 | Ananthakrishnan et al. | Mar 2013 | A1 |
| 20130111120 | Ananthakrishnan et al. | May 2013 | A1 |
| 20130111121 | Ananthakrishnan et al. | May 2013 | A1 |
| 20130111226 | Ananthakrishnan et al. | May 2013 | A1 |
| 20130111236 | Ananthakrishnan et al. | May 2013 | A1 |
| 20130179716 | Sistla et al. | Jul 2013 | A1 |
| 20130346774 | Bhandaru et al. | Dec 2013 | A1 |
| 20140068290 | Bhandaru et al. | Mar 2014 | A1 |
| 20140195829 | Bhandaru et al. | Jul 2014 | A1 |
| 20140208141 | Bhandaru et al. | Jul 2014 | A1 |
| 20190094904 | Yonemoto | Mar 2019 | A1 |
| Number | Date | Country |
|---|---|---|
| 1 282 030 | May 2003 | EP |
| 3449186 | Sep 2003 | JP |
| 2006522398 | Sep 2006 | JP |
| 100955433 | May 2010 | KR |
| Entry |
|---|
| Intel Developer Forum, IDF2010, Opher Kahn, et al., “Intel Next Generation Microarchitecture Codename Sandy Bridge: New Processor Innovations,” Sep. 13, 2010, 58 pages. |
| Intel Corporation, “Intel 64 and IA-32 Architectures Software Developer's Manual,” vol. 3B: System Programming Guide, Part 2, Apr. 2016, Chapter 14 Power and Thermal Management (14.1-14.9.5), 39 pages. |
| Intel Technology Journal, “Power and Thermal Management in the Intel Core Duo Processor,” May 15, 2006, pp. 109-122. |
| International Searching Authority, “Notification of Transmittal of the International Search Report and the Written Opinion of the International Searching Authority,” dated Jul. 2, 2020, in International application No. PCT/US2020/020927. |
| Number | Date | Country | |
|---|---|---|---|
| 20200311018 A1 | Oct 2020 | US |
