BRIEF DESCRIPTION OF THE DRAWINGS
The present invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:
FIGS. 1A to 1F are cross sections of an embodiment of a method for fabricating a system for displaying images incorporating a thin film transistor device.
FIG. 2 schematically shows another embodiment of a system for displaying images.
DETAILED DESCRIPTION OF THE INVENTION
The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.
Systems for displaying images and fabrication methods for same are provided. FIG. 1F illustrates an exemplary embodiment of such a system. Specifically, the system incorporates a thin film transistor (TFT) device comprising a substrate 100 comprising a driving circuit region D and a pixel region P. A buffer layer 102 may be optionally disposed on the substrate 100 to serve as an adhesion layer or a contamination barrier layer between the substrate 100 and the subsequent active layer. An active layer 111a is disposed on the substrate 100 of the pixel region P and an active layer 111b on the substrate 100 of the driving circuit region D. The active layer 111a may comprise a channel region 113a and a pair of source/drain regions 113b separated by the channel region 113a. The other active layer 111b may also comprise a channel region 113c and a pair of source/drain regions 113d separated by the channel region 113c. In this embodiment, the channel region 113a comprises dopants with a first conductivity type and a second conductivity type opposite to the first conductivity type. For example, the first conductivity type is N-type and dopants with the first conductivity type comprise phosphor. The second conductivity type is P-type and dopants with the second conductivity type comprise boron. The channel region 113c may be an intrinsic channel region or comprise dopants with only one conductivity type, such as N-type or P-type.
Fabrication of two gate structures are disposed on the active layers 111a and 111b, respectively, thus TFTs are complete. The TFT in the pixel region P may comprise a NMOS or a CMOS. The TFT in the driving circuit region D may comprise a NMOS, a PMOS, or a CMOS. The gate structure disposed on the active layer 111a comprises a stack of a gate dielectric layer 112 and a gate layer 114. The gate structure disposed on the active layer 111b also comprises a stack of the gate dielectric layer 112 and a gate layer 116.
Referring to FIGS. 1A to 1F, which illustrate an embodiment of a method for fabricating a system for displaying images incorporating a thin film transistor device. In FIG. 1A, a substrate 100 comprising a driving circuit region D and a pixel region P is provided. The substrate 100 may comprise glass, quartz, or plastic. A buffer layer 102 may be optionally formed on the substrate 100 to serve as an adhesion layer or a contamination barrier layer between the substrate 100 and the subsequent layer formed thereon. The buffer layer 102 may be a single layer or multiple layers. For example, the buffer layer 102 may comprise silicon oxide, silicon nitride, or a combination thereof.
A layer 104 is formed on the substrate 100 of the driving circuit and pixel regions D and P. In this embodiment, the layer 104 may comprise polysilicon and may be formed by a conventional low temperature polysilicon (LTPS) process. For example, an amorphous silicon layer (not shown) is formed on the substrate 100. A laser annealing treatment, such as an excimer laser annealing (ELA) treatment, is performed, such that the amorphous silicon layer is transformed into a polysilicon layer. Next, a channel doping process may be optionally performed on the polysilicon layer 104.
In FIG. 1B, a masking layer 106 is formed on the polysilicon layer 104 in the driving circuit region D to expose the polysilicon layer 104 in the pixel region P. The masking layer 106 may be formed by conventional lithography. Ion implantation 107 of a first conductivity type is performed on the exposed polysilicon layer 104 in the pixel region P. For example, the ion implantation 107 can employ phosphor ions or other N-type elements with an implant dosage of 1×1011˜1×1013 ion/cm2. The lattice structure of the exposed polysilicon layer 104 is damaged due to the ion bombardment, thus a damage region 107a is formed in the exposed polysilicon layer 104 in the pixel region P, as shown in FIG. 1C. In the damage region 107a, defect density of the polysilicon layer 104 is increased to increase the grain-boundary capacitance thereof. Typically, the grain-boundary capacitance is proportional to the sub-threshold swing. Accordingly, a higher sub-threshold swing can result when the defect density in the polysilicon layer serving as an active layer for a thin film transistor (TFT) is increased.
Additionally, the difference between the number of electrons and holes in the damage region 107a may be increased due to performance of the ion implantation 107 of the first conductivity type. As a result, the threshold voltage of the TFT drifts which is undesirable for circuit design. In order to address this problem, in this embodiment, ion implantation 109 of a second conductivity type opposite to the first conductivity type is performed in the damage region 107a of the polysilicon layer 104 in the pixel region P. For example, the ion implantation 109 can employ boron ions or other P-type elements with an implant dosage of 1×1011˜1×1013 ion/cm2, as shown in FIG. 1C, such that the damage region 107a of the polysilicon layer 104 in the pixel region P comprises dopants with the first and second conductivity types, in which the dopants with the first conductivity type is provided by ion implantation 107. Here, the polysilicon layer comprising dopants with the first and second conductivity types is labeled 109a, as shown in FIG. 1D. The provision of dopants with the second conductivity type can compensate for drift of threshold voltage due to reduction of the difference between the number of electrons and holes in the polysilicon layer 109a. In some embodiments, the ion implantation 107 can be performed by P-type elements and the subsequent ion implantation 109 can be performed by N-type elements.
As shown in FIG. 1D, after completion of the on implantation 109, the masking layer 106 shown in FIG. 1C is removed. Next, a heat treatment 111 is performed on the polysilicon layer 104 and 109a. For example, the heat treatment 111 can be performed by conventional rapid thermal annealing (RTA) at a temperature of about 300° C. to 600° C., to activate the dopants and repair the lattice structure of the polysilicon layer 109a in the pixel region P. After completion of the heat treatment 111, dopants can be bonded with silicon atoms in the polysilicon layer 109a to increase the stability of the polysilicon layer 109a. Moreover, some lattice defects may still remain in the polysilicon layer 109a after repair of the lattice structure, thereby increasing sub-threshold swing. In some embodiments, the heat treatment 111 can be performed in subsequent TFT fabrication steps. For example, the heat treatment 111 can be performed after formation of the gate structure for the TFT.
As shown in FIG. 1E, the polysilicon layer 104 and 109a shown in FIG. 1D is subsequently patterned to respectively form polysilicon pattern layers 111a and 111b in the pixel region P and in the driving circuit region D. The polysilicon pattern layers 111a and 111b serve as active layers for TFTs in the pixel region P and in the driving circuit region D. Next, an insulating layer 112 and a conductive layer (not shown) are successively formed on the active layers 111a and 111b and the buffer layer 102. In this embodiment, the insulating layer 112 serves as a gate dielectric and may be a single layer or multiple layers. For example, the insulating layer 112 may comprise silicon oxide, silicon nitride, or a combination thereof. The insulating layer 112 can be formed by conventional deposition, such as chemical vapor deposition (CVD). The conductive layer may comprise metal, such as molybdenum (Mo) or Mo alloy. The conductive layer can be formed by CVD or sputtering. The conductive layer is etched to form gate layers 114 and 116 overlying the active layers 111a and 111b, respectively. Heavy-ion implantation 113 is subsequently performed in the active layers 111a and 111b using the gate layers 114 and 116 as implantation masks.
After completion of the heavy-ion implantation 113, a channel region 113a is formed in the active layer 111a under the gate layer 114 and a pair of source/drain regions 113b is formed in the active layer 111a and separated by the channel region 113a. Moreover, a channel region 113c is formed in the active layer 111b under the gate layer 116 and a pair of source/drain regions 113d is formed in the active layer 111b and separated by the channel region 113c, as shown in FIG. 1F. Thus, a thin film transistor device 200 of the invention is complete.
According to the invention, since some lattice defects remain in the active layer 111a in the pixel regions P, the pixel TFT can have a higher sub-threshold swing than the TFT in the driving circuit region D. Accordingly, the TFT device can have different electrical characteristics in driving circuit and pixel regions D and P. Moreover, a higher sub-threshold swing for the pixel TFT can increase gray scale inversion of display device, thereby providing high contrast ratio for display devices without degrading the electrical characteristics of the drive TFT. Additionally, because the channel region 113a in the active layer 111a in the pixel regions P comprises N and P-type dopants, the threshold voltage of the pixel TFT can be prevented from drifting.
FIG. 2 schematically shows another embodiment of a system for displaying images which, in this case, is implemented as a flat panel display (FPD) device 300 or an electronic device 500 such as a laptop computer, a mobile phone, a digital camera, a personal digital assistant (PDA), a desktop computer, a television, a car display or a portable DVD player. The described TFT device can be incorporated into the flat panel display device 300 that can be an LCD or OLED panel. As shown in FIG. 2, the FPD device 300 may comprise a TFT device, such as a TFT device 200 shown in FIG. 1F. In some embodiments, the TFT device 300 can be incorporated into the electronic device 500. As shown in FIG. 2, the electronic device 500 comprises the FPD device 300 and an input unit 400. Moreover, the input unit 400 is coupled to the FPD device 300 and operative to provide input signals (e.g. image signals) to the FPD device 300 to generate images.
While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.
Patent Application
20080035995
