Patent Application
20170090801
The present disclosure relates to a system for the protection of program codes stored in an external memory, for example of FLASH NOR type, that are to be executed by a computer processing module, and to a related method.
A computer processing module can have not only a microprocessor but also a cache memory allowing it to store recently used program code so as to access the program code more quickly in the event of possible reuse. If the program code is not present in the cache memory, it is transferred from a higher-level memory to the cache memory. During this transfer, the program code may be the target of attackers that have modified or replaced the program code with malicious code. It is therefore desirable, notably for critical applications, to check the integrity of the transferred program code.
Methods allowing the integrity of a program code to be checked are known that use message authentication codes, which are commonly denoted by the acronym “MAC”.
A message authentication code is a code that accompanies data with the aim of ensuring the integrity thereof by allowing a check to determine that they have not undergone any modification following a transmission from an external memory to a microprocessor, for example.
At present, the message authentication code can be stored either in an area of the external memory that is different from the one that contains the program code, in which case reading of the authentication code requires a second read access, or in the same memory location as the program code, subsequently thereto, but this case is not compatible with wraps.
One embodiment of the present disclosure provides a method for storing message authentication codes in split fashion in program code.
According to another aspect, the method includes protecting the program code that is intended to be executed by a central processing unit of a computer processing module. The central processing unit may be coupled to a cache memory containing cache lines that each have a data field that is intended to store instruction words that can be executed by the central processing unit. The method may include storing the program code in memory locations of an external memory with respect to the computer processing module, each memory location being capable of storing the instruction words of one cache line. The method may also include determining authentication codes that are respectively associated with the cache lines and, for each cache line, fragmenting the associated authentication code and storing this distributed fragmented authentication code in the corresponding memory location.
Thus, during a request by the computer processing module for a program code instruction line, the program code and the authentication code are read simultaneously. Moreover, this aspect is compatible with wraps.
According to another aspect, each memory location may contain memory words that respectively store the words of the corresponding cache line, each memory word has a storage capacity above that of the instruction word and contains an area that is not used for storing the instruction word, and the fragments of the authentication code that are associated with the instruction words of the cache line are stored in at least some of the unused areas.
The method may further include, during a request by the central processing unit for an instruction word that is not present in a cache line of the cache memory, extraction, from the external memory, of the instruction words of the corresponding cache line and of the associated fragmented authentication code, reconstruction of the authentication code from said fragments, computation of the authentication code from the extracted instruction words, and comparison of the computed authentication code with the reconstructed authentication code.
According to another aspect, each memory location contains memory words that respectively store the words of the corresponding cache line, each memory word has a storage capacity equal to that of the instruction word, and the storage of the program code includes compression of at least some of the instruction words of each cache line and storage of the compressed instruction words in the corresponding memory words. This storage provides for a free area to remain in the corresponding memory word, and the fragments of the authentication code that are associated with the compressed instruction words of the cache line are stored in the free areas.
Thus, this aspect may dispense with the use of memory words of a size above that of the instruction words, because the compression of the instruction words makes it possible to obtain free areas in the memory words and to store the authentication code therein.
The compression may be performed either by an algorithm making it possible to obtain compressed words of variable size or by an algorithm making it possible to obtain compressed words of fixed size.
The method may further include during a request by the central processing unit for an instruction word that is not present in a cache line of the cache memory, extraction, from the external memory, of the instruction words of the corresponding cache line and of the associated fragmented authentication code, reconstruction of the authentication code from the fragments, decompression of the compressed instruction words, computation of the authentication code from the decompressed instruction words, and comparison of the computed authentication code with the extracted authentication code.
According to another aspect, a system is disclosed that includes a computer processing module containing a central processing unit, and a cache memory containing cache lines that each have a data field that is intended to store instruction words that can be executed by the central processing unit of the computer processing module. The system may also include an external memory with respect to the computer processing module including memory locations corresponding to data fields of cache lines, each memory location being configured to store the instruction words of a cache line, and a controller that is configured to determine authentication codes that are respectively associated with the cache lines, to fragment the associated authentication code and to store this distributed fragmented authentication code in the corresponding memory location.
Each memory word of each memory location may have a storage capacity above that of the instruction word and contain an area that is not used for storing the instruction word, and at least some of said unused areas are capable of receiving the fragments of the authentication code that is associated with the instruction words of the cache line.
The controller is configured to, during a request by the central processing unit for an instruction word that is not present in a cache line of the cache memory, extract, from the external memory, the instruction words of the corresponding cache line and the associated fragmented authentication code, reconstruct the authentication code from the fragments, compute the authentication code from the extracted instruction words, and compare the computed authentication code with the reconstructed authentication code.
According to another aspect, each memory location contains memory words that respectively store the words of the corresponding cache line, each memory word has a storage capacity equal to that of the instruction word, and is capable of receiving compressed, or otherwise, instruction words to allow a free area to remain in the memory word that is capable of receiving a fragment of the authentication code that is associated with the compressed instruction words of the cache line.
The controller can advantageously be configured to compress the instruction words to form compressed words of equal size or to form compressed words of variable size.
Other advantages and features of the invention will emerge upon examining the detailed description of implementations and embodiments, which are in no way restrictive, and the appended drawings, in which:
The system SYS likewise comprises a controller 4 that is configured to perform decompression and/or concatenation operations on data that are interchanged between the processing module 1 and the external memory 2. These operations will be seen in more detail below.
In this example, the processing module 1 includes a microprocessor 5, a level-1 cache 6 having cache lines 60 that is intended to receive instruction words 83 of a program code and a cache controller 7. In this example, the cache comprises cache lines that may receive thirty-two words of 16 bits each.
The external memory includes memory locations 8 that are each configured to receive instruction words 83 of a program code corresponding to a cache line and a message authentication code that is associated with the cache line.
As illustrated in
In this case, for example, the memory words 81 of the external memory are words of 18 bits, 16 bits of which are intended to store the instruction words 83 and two bits of which are supplementary bits. Each memory location 8 is therefore capable of storing the 32 instruction words 83 of a cache line in the 32 memory words 81 of 18 bits by leaving a free space of 32×2 bits that is distributed over the 32 memory words 81.
In the example described here, these free areas 82 are situated at the end of the memory words 81. As a variant, they could be situated at the start of the memory words 81 or else at any known position for these patterns 81.
In step 11, a message authentication code MAC referenced MACref is computed from the program code that is present in the memory location 8. By way of example, a message authentication code is obtained conventionally by an algorithm using, as input, the message to be transmitted and a coding key in order to obtain, as output, the authentication code. This algorithm, which is similar to the hash functions that are well known to a person skilled in the art, does not need to be reversible. It makes it possible to ensure the integrity and authenticity of the transmitted data.
Step 12 includes fragmentation of the authentication code MACref associated with the 32 instruction words 83 so as to distribute it in this case in the free areas 82 of the 32 memory words 81. It might not be necessary to use the 32 free areas 82 for storing the fragments MACref, but just some of the free areas, for example.
It should be noted at this juncture that the computation of the codes MACref and the fragmentation thereof could be performed before storage of the instruction set and followed by simultaneous storage of the instruction set and fragmented codes MACref in the memory.
Next at step 13, if the central processing unit 5, in this case a microcontroller, makes a request for an instruction word 83, the cache controller 7 checks the presence of the instruction word 83 in a cache line of the cache 6 of the computer processing module 1.
If the instruction word is present in a cache line of the cache 6, then the instruction is executed, at step 14, by the microcontroller 6.
The opposite case, at step 15, is referred to as a cache miss. The cache controller then makes a request to the external memory 2 so that the content of the memory location 8 storing the cache line containing the required instruction word is transmitted to it.
It should be noted that a cache line is the smallest element that can be transferred between the cache memory 6 and the external memory 2. Upon each request for an instruction word 83, all of the words 81 in the memory location 8 are therefore transferred, rather than just the memory word 81 containing the instruction word 83.
By way of example, if the required instruction word is situated in position n in the memory location, then the words 81 from the n-th to the last word 81 of the line will be extracted, and then the words from the first in the line to word n−1 will be extracted, in accordance with the operation of a wrap.
Next, at step 16, the controller 4 uses concatenation to reconstruct the message authentication code MACref from the fractions distributed in the free areas 82 of each of the memory words 81 received from the memory location 8.
This concatenation is possible whatever the order of extraction of the instruction words.
The controller 4 likewise computes, at step 17, a message authentication code MACcalc from the content of the instruction words 83 received during the transfer, and then compares the computed code MACcalc with the reconstructed authentication code MACref.
If the two codes are not identical, at step 18, this indicates that the program code has been modified. The controller 4 then generates an error.
If the two codes are identical, at step 19, then this indicates that the integrity and authenticity of the program code is verified, and the program code can be executed in secure fashion by the microcontroller 5.
In this embodiment, the memory locations 8 include memory words 81 of identical size to the size of the instruction words 83, for example in this case memory locations having thirty-two words of 16 bits.
The first step 100 corresponds to compression of the instruction words 83 prior to step 10 of storage in the memory locations of the external memory.
This compression can be performed in accordance with a deterministic algorithm making it possible to obtain compressed instruction words 84 of fixed size (
The bits corresponding to the instruction words are compressed, and those corresponding to the authentication code are not.
Step 101, which follows the extraction of the content of the memory location 8, corresponds to decompression of the compressed instruction words 84.
In this case, for example, the controller 4 can include a hardware decompressor, which allows rapid decompression of the data.
It should be noted that the implementations and embodiments presented here are in no way restrictive. Notably, although a flash NOR memory has been involved in this case, the invention can likewise be applied to DRAM (Dynamic Random Access Memory) memories.
Furthermore, although a cache memory 6 situated in the computer processing module 1 has been described above, the cache memory could be situated outside the processing module. In particular, the cache memory could be formed by a buffer memory situated in the interface of the FLASH memory 8.
Moreover, whereas the description above concerned execution of the program code by the microprocessor 5 only if the reconstructed authentication code MACref is identical to the computed authentication code MACcalc, it is quite possible for the execution of the program code to start during the computation of the code MACcalc and the comparison of the two codes MACref and MACcalc, and to be interrupted in the event of the comparison indicating that the two codes MACref and MACcalc are not identical.
| Number | Date | Country | Kind |
|---|---|---|---|
| 1559009 | Sep 2015 | FR | national |
