Patent Application
20150076700
Embodiments of the present invention relate generally to microelectronic packaging and, more particularly, to System-in-Packages and methods for fabricating System-in-Packages including surface mount devices, which may be embedded within a molded package body or disposed between stacked package layers.
Fan Out Wafer Level Packaging (FO-WLP) processes are well-known within the semiconductor industry for producing microelectronic packages having peripheral fan-out areas, which enlarge the surface area of the package topside over which a contact array may be formed. In an example of one known FO-WLP approach, commonly referred to as a “Redistributed Chip Packaging” or “RCP” packaging approach, an array of singulated die is encapsulated in a molded panel over which a number of Redistribution Layers (RDL layers) and a Ball Grid Array (BGA) are formed. After formation of the RDL layers and the BGA, the panel is singulated to yield a number of RCP packages each containing a semiconductor die embedded within a molded body. The passive components may be one or more discrete resistors, capacitors, inductors, and/or diodes provided in the form of Surface Mount Devices (SMDs). When integrated into a System-in-Package (SiP) produced utilizing an RCP packaging approach, the SMDs may be positioned horizontally either within an upper portion of the molded package body or over the uppermost RDL layer (e.g., the solder mask layer) adjacent the BGA. It is not uncommon for a single SiP to include multiple die and several discrete resistors, capacitors, inductors, or other SMD devices, depending upon the particular application for which the SiP is designed.
At least one example of the present invention will hereinafter be described in conjunction with the following figures, wherein like numerals denote like elements, and:
For simplicity and clarity of illustration, the drawing figures illustrate the general manner of construction, and descriptions and details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the exemplary and non-limiting embodiments of the invention described in the subsequent Detailed Description. It should further be understood that features or elements appearing in the accompanying figures are not necessarily drawn to scale unless otherwise stated. For example, the dimensions of certain elements or regions in the figures may be exaggerated relative to other elements or regions to improve understanding of embodiments of the invention.
The following Detailed Description is merely exemplary in nature and is not intended to limit the invention or the application and uses of the invention. Any implementation described herein as exemplary is not necessarily to be construed as preferred or advantageous over other implementations. Furthermore, there is no intention to be bound by any theory presented in the preceding Background or the following Detailed Description.
Terms such as “first,” “second,” “third,” “fourth,” and the like, if appearing in the description and the subsequent claims, may be utilized to distinguish between similar elements and are not necessarily used to indicate a particular sequential or chronological order. Such terms may thus be used interchangeably and that embodiments of the invention are capable of operation in sequences other than those illustrated or otherwise described herein. Furthermore, terms such as “comprise,” “include,” “have,” and the like are intended to cover non-exclusive inclusions, such that a process, method, article, or apparatus that comprises a list of elements is not necessarily limited to those elements, but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. The term “coupled,” as appearing herein, is defined as directly or indirectly connected in an electrical or non-electrical manner. Furthermore, the terms “substantial” and “substantially” are utilized to indicate that a particular feature or condition is sufficient to accomplish a stated purpose in a practical manner and that minor imperfections or variations, if any, are not significant for the stated purpose.
As appearing herein, the term “microelectronic component” is utilized in a broad sense to refer to an electronic device, element, or structure produced on a relatively small scale and amenable to packaging in the below-described manner. Microelectronic components include, but are not limited to, integrated circuits formed on semiconductor die, Microelectromechanical Systems (MEMS) devices, passive electronic components (e.g., a discrete resistor, capacitor, inductor, or diode), optical devices, and other small scale electronic devices capable of providing processing, memory, sensing, radiofrequency, optical, and actuator functionalities, to list but a few examples. The term “System-in-Package” and the corresponding acronym “SiP” are further utilized herein to refer to a microelectronic package including at least one semiconductor die packaged with at least one passive microelectronic component, such as a surface mount device. The term “Surface Mount Device” and the corresponding acronym “SMD” are still further utilized herein to refer to a discrete microelectronic device directly mountable on the surface of a substrate, such as a printed circuit board, having electrical points-of-contact with which the SMD may be placed in ohmic contact. A non-exhaustive list of SMDs includes discrete resistors, capacitors, inductors, diodes, and the like. In this regard, the SMDs contained with the SiPs produced pursuant to the below-described fabrication method conveniently (but need not always) assume the form of two terminal packages having generally rectangular or square-shaped bodies, such as chip resistors, chip capacitors, and/or chip inductors having opposing end terminals. The term “terminal” may be utilized herein to refer to a node, lead, or other point-of-contact provided on a microelectronic device, such as an SMD. Finally, the term “about 0 ohm (Ω)” is defined herein as a resistance of less than 0.1Ω.
The following describes embodiments of a method for producing SiPs wherein SMDs, such as discrete resistors, capacitors, inductors, and/or diodes, are placed in ohmic contact with electrically-conductive members located on opposing sides of package body or located within different stacked package layers. In many cases, the SMDs are utilized to provide their traditional or intended function; e.g., the provision of a known resistance, capacitance, inductance, or the like. Additionally or alternatively, the embedded SMDs may also provide a new or heretofore unrealized function, namely, the provision of low (e.g., about 0Ω) resistance signal paths through the package body and/or between package layers. In this manner, the embedded SMDs may effectively replace other structures or features traditionally utilized to provide signal routing through the package body (e.g., through package vias) and/or between package layers (e.g., solder balls). In certain cases, a single SMD may be utilized to provide both of these functionalities; e.g., a single chip resistor, capacitor, or inductor may provide a known resistance, capacitance, or inductance, respectively, while also providing one or more low resistance signal paths through the package body or between stacked package layers. The SMDs embedded within a given SiP may be positioned in horizontal orientations, vertical orientations, or a combination thereof. Advantageously, by embedding multiple SMDs in a molded package body in a vertical orientation, a greater number of SMDs can be integrated into the SiP while reducing the planform dimensions or footprint of the SiP.
Referring initially to
Semiconductor die 22, SMD 28, and SMD 34 each include a number of contacts or terminals. In the case of semiconductor die 22, the contacts assume the form of bond pads 26 disposed on the upper or frontside surface of die 22. In the case of SMDs 28 and 34, the contacts may assume different forms and dispositions depending upon the particular type of SMD employed. In the illustrated example, SMDs 28 and 34 are two terminal devices each having a generally rectangular body, when viewed from the side, top, or bottom; and which is flanked by electrically-conductive end terminals extending beyond the body in at least one lateral direction. In this regard, SMD 28 may include opposing end terminals 30 and 32, while SMD 34 includes opposing end terminals 36 and 38. SMDs 28 and 34 may be discrete resistors, capacitors, inductors, or a combination thereof. In one embodiment, SMDs 28 and 34 may assume the form of discrete capacitors (commonly referred to as “chip capacitors” or, more simply, “chip caps”) each including an electrically-insulative (e.g., ceramic) body disposed between two electrically-conductive end pieces; i.e., terminals 30 and 32 in the case of SMD 28, and terminals 36 and 38 in the case of SMD 34. In other embodiments, one or both of SMDs 28 and 34 may assume the form of a two-terminal chip inductor or a two-terminal chip resistor having the generally rectangular form factor illustrated in
When placed onto temporary substrate 24, semiconductor die 22 is inverted and positioned facedown such that bond pads 26 of die 22 are placed in contact with the upper surface of substrate 24. By comparison, SMD 28 is positioned in a vertical orientation such that terminal 32 is placed in contact with the upper surface of substrate 24; while terminal 30 is located above substrate 24, as taken along an axis substantially orthogonal to the frontside or backside of the subsequently-produced package body (corresponding to the “Z-axis” identified in
Vertically-orientated SMD 28 and horizontally-orientated SMD 34 each have a thickness greater than that of semiconductor die 22, as taken through the package thickness or along an axis orthogonal to the package frontside or backside (corresponding to the “Z-axis” in
Temporary substrate 24 can be any body, structure, or platform suitable for supporting die 22, vertically-orientated SMD 28, horizontally-orientated SMD 34, and the other non-illustrated microelectronic devices during panel encapsulation (also commonly referred to as “panelization” or “overmolding”). In one embodiment, temporary substrate 24 is a taped molded frame, which includes a soft tape adhesive layer 46 on which semiconductor die 22, vertically-orientated SMD 28, and horizontally-orientated SMD 34 are placed. A non-illustrated mold frame, which has a central cavity or opening therein, is positioned over tape layer 46 and around the semiconductor die disposed thereon. An electrically-insulative encapsulant or mold compound, such as a silica-filled epoxy, is dispensed into the cavity of the mold frame. The encapsulant flows over and around die 22, SMD 28, and SMD 34 and the other devices placed on tape layer 46. The encapsulant may then solidified by thermal curing (e.g., heating in a partially-evacuated chamber) to yield a solid panel in which die 22, SMD 28, SMD 34, and the other non-illustrated microelectronic devices are embedded. The panel is conveniently produced as a relatively thin, disc-shaped body or mass having a generally circular planform geometry; however, the panel body can be fabricated to have any desired shape and dimensions. In other embodiments, the panel can be produced utilizing various other known fabrication techniques including, for example, compression molding and lamination processes.
Referring next to
Frontside interconnect lines 60 may comprise various metal traces, vias, metal plugs, and/or the like, which collectively provide electrically-conductive paths between the upper surface of frontside RDL layers 58 and semiconductor die 22, vertically-orientated SMD 28, and horizontally-orientated SMD 34 embedded within panel 48. In this regard, interconnect lines 60 may be formed in ohmic contact with terminal 32 of vertically-orientated SMD 28, bond pads 26 of die 22, and terminals 36 and 38 of horizontally-orientated SMD 34. After formation of frontside RDL layers 58, trenches or openings 64 may be formed in the uppermost RDL layer (e.g., a capping, passivation, or solder mask layer) by lithographical patterning to expose selected regions of frontside interconnect lines 60. A frontside contact array, such as a BGA, may then be produced over the frontside of partially-completed SiP 20 and in ohmic contact with the exposed regions of interconnect lines 60. Alternatively, a frontside contact array may not be produced until after build-up of one or more backside RDL layers, as described below in conjunction with
With reference to
Pursuant to the above-descried material removal process, molded panel 48 may be imparted with a final thickness between about 100 and about 1000 microns (m) and, preferably, between about 200 and about 700 μm. In further embodiments, the final thickness of panel 48 may be greater than or less than the aforementioned ranges. Furthermore, it is preferred, although by no means necessary, that the material removal process imparts backside 52 of panel 48 with a substantially planar topology; that is, a surface roughness of less than about 30 μm, preferably less than about 1 μm, and, still more preferably, less than about 0.5 μm. If desired, the backside material removal process can be carried-out in multiple steps or stages. For example, in one implementation of the fabrication process, an initial bulk removal grinding step may first be carried-out utilizing a pad or paper having a relatively coarse grit, and followed by a final grinding step performed utilizing a pad or paper having a relatively fine grit to impart molded panel 48 with a relatively planar surface finish. In embodiments wherein the material removal process imparts panel 48 with substantially planar backside surface (again, defined as a surface having a roughness or feature height less than about 30 μm), the material removal process may also be referred to as a “planarization process” herein.
A certain amount of material may be removed from the SMD terminals exposed through backside 52 of panel 48 during the above-described material removal process. However, a certain amount of material removal from the SMD terminals is permissible within controlled limits as terminals 30, 36, and 38 will typically be relatively thick (e.g., >20 μm), as taken along the longitudinal axes of SMDs 28 and 34 (identified in
As previously stated, SMD 28, 34, and the other non-illustrated SMDs embedded within molded panel 48 may be chosen such that their respective packaged heights are substantially equivalent to the desired final thickness of panel 48 and, therefore, the final thickness of the molded package bodies produced pursuant to singulation of panel 48 (described below in conjunction with
One or more backside RDL layers 70 may be formed over the newly-planarized backside 52 of molded panel 48 and, therefore, over semiconductor die 22, vertically-orientated SMD 28, horizontally-orientated SMD 34, and the microelectronic devices embedded within the other, non-illustrated regions of panel 48. Backside RDL layers 70 may be produced to include a dielectric body 72, which may be formed as one or more spun-on or otherwise deposited dielectric layers. Electrically-conductive paths or interconnect lines 74 are formed within dielectric body 72 utilizing, for example, lithographical patterning and conductive material deposition processes of the type described above. Backside interconnect lines 74 are formed in ohmic contact with terminal 32 of vertically-orientated SMD 28 and terminals 36 and 38 of horizontally-orientated SMD 34. Considering this, it will be appreciated that SMD 28 and SMD 34 are each electrically interconnected across the body 50 of molded panel 48, albeit in different manners as discussed below. After formation of the backside RDL layers 70, trenches or openings 76 may be created within the final or outermost dielectric layer of backside RDL layers 70 by lithographical patterning to expose selected regions of interconnect lines 74. The resultant structure is shown in
A frontside contact array and/or a backside contact array may now be formed over partially-completed SiP 20, as well as over the other partially-completed SiPs fabricated over the non-illustrated regions of molded panel 48. With respect to partially-completed SiP 20, specifically, a frontside contact array 78 and backside contact array 80 may be formed over frontside RDL layers 58 and backside RDL layers 70, respectively, as generally shown in
While frontside and backside contact arrays 78 and 80 assume the form of BGAs in the illustrated example, contact arrays 78 and 80 may assume other forms suitable for providing externally-accessible points-of-contact to the interconnect lines embedded within the frontside RDL layers 58 and backside RDL layers 70. For example, in further embodiments, the frontside and/or backside contact array may comprise externally-exposed bond pads in ohmic contact with the interconnect lines formed in the frontside and/or backside RDL layers; externally-exposed portions of the frontside and/or backside RDL interconnect lines; or electronically-conductive bodies formed in contact with the frontside and/or backside interconnect lines other than solder balls, such as plated pillars or bodies of electrically-conductive paste. Furthermore, while SiP 20 is produced to include backside RDL layers 70 and a backside contact array 80 in the illustrated example, this need not always be the case. Instead, in further embodiments, the fabrication method may conclude after the backside planarization process described above in conjunction with
Fabrication of SiP 20 and the other SiPs produced in parallel with SiP 20 concludes with the singulation of molded panel 48 into multiple discrete pieces. Singulation of panel 48 is conveniently preformed utilizing a dicing saw; however, any process suitable for separating panel 48 into multiple, discrete pieces can be utilized, such as laser cutting.
With continued reference to
As will be gathered from the foregoing description, SMDs 28 and 34 are embedded within package body 84 in different orientations such that the longitudinal axes of SMDs 28 and 34 (identified in
Horizontally-orientated SMD 34 extends through package body 84 such that the upper and lower surfaces of SMD 34 are substantially coplanar with frontside 86 and backside 88 of body 84, respectively. Such a positioning allows SMD 34 to provide a dual functionality. In particular, SMD 34 may provide its traditional or dedicated function (e.g., the provision of a known capacitance, resistance, or inductance) between contact points or nodes in frontside RDL layers 58 (represented in
There has thus been described multiple exemplary embodiments of a fabrication process suitable for producing one or more SiPs each including at least one embedded SMD, which extends through a molded package body produced in accordance with a molded panel packaging approach similar to an RCP packaging approach. In certain embodiments, the embedded SMD may be vertically oriented to reduce the X-Y footprint of the SMD and, more generally, the X-Y footprint of the SiP. The SMD may provide its typical functionality and/or may also provide one or more signal paths through the package body, as described above. In still further embodiments, SiPs can be produced wherein one or more embedded SMDs (whether positioned horizontally or vertically) provide electrical interconnectivity between stacked package layers. In this case, the SiP may assume the form of a “Package-on-Package” or “PoP” device having two or more package layers. The package layers may be produced utilizing various different manufacturing techniques, and a given SiP may include multiple package layers each produced utilizing a different packaging technique. Several examples of SiPs including embedded SMDs electrically coupled or bridged across stacked package layers will now be described in conjunction with
With continued reference to
During fabrication of SiP 100, and by way of non-limiting example only, RDL layers 112 and 122 may be built-up over molded panels utilizing standard processes of the type described above, openings may be formed in layers 114 and 122 exposing selected regions of interconnects lines 126 and 128 utilizing known lithographical patterning techniques, and electrically-conductive globs of paste 144 may be deposited into the openings formed in layers 114 and 112. SMDs 130 and 132 may then be positioned on package layer 104 in their desired locations utilizing, for example, a pick-and-place tool such that the SMD terminals are placed in ohmic contact with paste bodies 144. Package layer 102 may then be stacked on package layer 104 with proper alignment to ensure that SMDs 130 and 132 extend into the openings formed in RDL layers 114. In a preferred embodiment, package layers 102 and 104 are stacked prior to singulation of the respective molded panels in which layers 102 and 104 are contained. After stacking of the molded panels containing layers 102 and 104, BGA 114 may be produced utilizing a bumping process. The stacked molded panels may then be singulated to yield the completed PoP SiP 100 shown in
In view of its vertical orientation, SMD 130 may provide those functions described above in conjunction with SMD 28 (
In further embodiments wherein the SiP includes one or more SMDs disposed between stacked package layers, one or more the stacked package layers may be produced utilizing a non-molded panel fabrication process, such as a Wafer Level Chip-Scale Packaging (WL-CSP), a Molded Array Process Ball Grid Array (MAPBGA), a Flip-Chip Ball Grid Array (FCBGA), or a sawn Quad-Flat No-Lead (QFN) strip level stacking process, to list but a few examples. Further emphasizing this point,
Turning to
The foregoing has thus provided embodiments of a method for producing SiPs wherein SMDs, such as discrete resistors, capacitors, inductors, and/or diodes, are placed in ohmic contact with electrically-conductive members located on opposing sides of package body or located within different stacked package layers. The SMDs may be utilized to provide their traditional or intended function; e.g., the provision of a known resistance, capacitance, inductance, or the like. Additionally or alternatively, the embedded SMDs may also provide a new or heretofore unrealized function, namely, the provision of low (e.g., ˜0Ω) resistance signal paths through the package body and/or between package layers. In this manner, the embedded SMDs may effectively replace other structures or features traditionally utilized to provide signal routing through the package body (e.g., through package vias) and/or between package layers (e.g., solder balls). In certain cases, a single SMD may be utilized to provide both of these functionalities; e.g., a single chip resistor, capacitor, or inductor may provide a known resistance, capacitance, or inductance, respectively, while also providing one or more low resistance signal paths through the package body or between stacked package layers. The SMDs embedded within a given SiP may be positioned in horizontal orientations, vertical orientations, or a combination thereof. By embedding multiple SMDs in a molded package body in a vertical orientation, a greater number of SMDs can be integrated into the SiP while reducing the overall SiP footprint as compared to a similar SiP containing only horizontally-orientated SMDs.
In one embodiment of the above-described fabrication method, one or more frontside redistribution layers are produced over the frontside of a molded panel in which a semiconductor die and a first SMD embedded. The semiconductor die and the first SMD are exposed through the frontside of the molded panel. Material is removed from the backside of the molded panel to expose the first SMD therethrough. A contact array is formed over the frontside of the molded panel and electrically coupled to the semiconductor die and to the first SMD through the frontside redistribution layers. The molded panel is singulated to produce a SiP having a molded body in which the semiconductor die and the first SMD are embedded and through which the first SMD extends.
In another embodiment of the fabrication method, an SiP is produced that includes a first package layer and a second package layer. A first SMD is embedded between the first package layer and the second package layer substrate such that the first SMD electrically interconnects an electrically-conductive feature (e.g., a first RDL interconnect line, a trace provided on a substrate, a via provided through a substrate, etc.) included within the first package layer to an electrically-conductive feature (e.g., a second RDL interconnect line, a trace provided on a substrate, a via provided through a substrate, etc.) included within the second package layer. In certain embodiment, the first package layer may comprises a molded package body over which one or more redistribution layers has been formed. In such embodiments, the electrically-conductive feature included within the first package layer may be an interconnect line formed in the redistribution layers, and the first SMD may be positioned to extend into the redistribution layers and ohmically contact the interconnect line. In other embodiments, the first package layer may further include a second SMD embedded within and extending through the molded package body. In still further embodiments, the first package layer may be a first substrate, wherein the second package layer may be a second package substrate, and the first SMD may be positioned in ohmic contact with the first and second substrate. The first SMD may include opposing end terminals, and the method may include depositing bodies of electrically-conductive paste (e.g., a silver-filled or copper-filled epoxy) between the opposing end terminals of the first SMD, the electrically-conductive feature included within the first package layer, and the electrically-conductive feature included within the second package layer.
Embodiments of a SiP have also been provided. In one embodiment, the SiP includes a molded package body having a frontside and a backside. One or more frontside redistribution layers are disposed over the molded package body, and a frontside contact array is disposed over the frontside redistribution layers. A first SMD, such as a discrete resistor, capacitor, inductor, or diode, is embedded in the molded package body. The first SMD extends from the frontside to the backside of the molded package body and is electrically coupled to the frontside contact array through the frontside redistribution layers. In certain embodiments, the SiP may further include one or more backside redistribution layers disposed over the backside of the molded package body. In such cases, the SMD may include a first terminal exposed through the frontside of the molded package body and in ohmic contact with an interconnect line contained within the frontside redistribution layers, and a second terminal exposed through the backside of the molded package body and in ohmic contact with an interconnect line contained within the backside redistribution layers. In further implementations, the first SMD may be a discrete resistor, capacitor, inductor, or diode.
While at least one exemplary embodiment has been presented in the foregoing Detailed Description, it should be appreciated that a vast number of variations exist. It should also be appreciated that the exemplary embodiment or exemplary embodiments are only examples, and are not intended to limit the scope, applicability, or configuration of the invention in any way. Rather, the foregoing Detailed Description will provide those skilled in the art with a convenient road map for implementing an exemplary embodiment of the invention. It being understood that various changes may be made in the function and arrangement of elements described in an exemplary embodiment without departing from the scope of the invention as set-forth in the appended claims.
