Patent Grant
7274373
Graphics application program interfaces (API's) have been instrumental in allowing applications to be written to a standard interface and to be run on multiple platforms, i.e. operating systems. Examples of such graphics API's include Open Graphics Library (OpenGL®) and Direct 3D™ (D3D™) pipelines. OpenGL® is the computer industry's standard graphics API for defining 2-D and 3-D graphic images. With OpenGL®, an application can create the same effects in any operating system using any OpenGL®-adhering graphics adapter. OpenGL® specifies a set of commands or immediately executed functions. Each command directs a drawing action or causes special effects.
Thus, in any computer system which supports this OpenGL® standard, the operating system(s) and application software programs can make calls according to the standard, without knowing exactly any specifics regarding the hardware configuration of the system. This is accomplished by providing a complete library of low-level graphics manipulation commands, which can be used to implement graphics operations.
A significant benefit is afforded by providing a predefined set of commands in graphics API's such as OpenGL®. By restricting the allowable operations, such commands can be highly optimized in the driver and hardware implementing the graphics API. On the other hand, one major drawback of this approach is that changes to the graphics API are difficult and slow to be implemented. It may take years for a new feature to be broadly adopted across multiple vendors.
With the integration of transform operations into high speed graphics chips and the higher integration levels allowed by semiconductor manufacturing, it is now possible to make part of the pipeline accessible to the application writer. There is thus a need to exploit this trend in order to afford increased flexibility in visual effects. In particular, there is a need to provide a new computer graphics programming model and instruction set that allows convenient implementation of changes to the graphics API, while preserving the driver and hardware optimization afforded by currently established graphics API's.
A system, method and computer program product are provided for programmable pixel processing in a computer graphics pipeline. In one embodiment of the present invention, arbitrary texture filtering is applied via a programmable shader.
Specifically, the present programmable shader is employed to provide arbitrary texture filtering without the constraints of traditional texture filtering modules that have fixed parameters. This approach allows the shader to perform the filtering functions of high quality filters which are non-linear in nature, e.g., to perform operations like deinterlacing and noise reduction. Additionally, video images are often in a different color space (YUV vs RGB) and the amplitude values are gamma pre-compensated (instead of linear perceptual space). In one embodiment, the present invention is capable of using modified elements of a traditional graphics pipeline (like textures) and an programmable pixel shader to perform video filtering.
The foregoing and other aspects and advantages are better understood from the following detailed description of a preferred embodiment of the invention with reference to the drawings, in which:
As an option, each of the foregoing modules may be situated on a single semiconductor platform. In the present description, the single semiconductor platform may refer to a sole unitary semiconductor-based integrated circuit or chip. It should be noted that the term single semiconductor platform may also refer to multi-chip modules with increased connectivity which simulate on-chip operation, and make substantial improvements over utilizing a conventional CPU and bus implementation. Of course, the present invention may also be implemented on multiple semiconductor platforms and/or utilizing a conventional CPU and bus implementation.
During operation, the buffer 50 is included for gathering and maintaining a plurality of attributes. Completed vertices are processed by the transform module 52 and then sent to the lighting module 54. The transform module, 52 generates parameters for the lighting module 54 to light. The output of the lighting module 54 is screen space data suitable for the set-up module which, in turn, sets up primitives. Thereafter, rasterization module 56 carries out rasterization of the primitives. In particular, the rasterization module 56 passes on pixel data including, but not limited to a position, a pixel diffuse color, a specular color, a fog value, a plurality of texture coordinates, and/or any other information relating to the pixels involved with the processing in the graphics pipeline.
A pixel processing module 58 is coupled to the rasterization module 56 for processing the pixel data. The pixel processing module 58 begins by reading the pixel data generated by the rasterization module 56. In operation, the pixel processing module 58 outputs a color and a depth value. Pixel processing module 58 can be implemented in accordance with application specific requirements. For example, pixel processing module 58 can be implemented as disclosed in US patent application entitled “Programmable Pixel Shading Architecture”, filed on Jun. 19, 2001 with Ser. No. 09/885,242, which is also assigned to the assignee of the present application. This patent application is herein incorporated by reference.
Table 1 illustrates operations that may be done after the pixel processing module 58 is finished. A standard application program interface (API) state may be used as appropriate, as will soon become apparent.
When disabled, the present invention allows increased or exclusive control of the graphics pipeline by the standard graphics API, as indicated in operation 206. In one embodiment, states of the standard graphics API may not be overruled by invoking the programmable pixel mode of the present invention. In one embodiment, no graphics API state may be directly accessible by the present invention, with the exception of the bound texture state.
In one embodiment, the standard graphics API may include Open Graphics Library (OpenGL®) and/or D3D™ APIs. OpenGL®is the computer industry's standard API for defining 2-D and 3-D graphic images. With OpenGL®, an application can create the same effects in any operating system using any OpenGL®-adhering graphics adapter. OpenGL® specifies a set of commands or immediately executed functions. Each command directs a drawing action or causes special effects. OpenGL® and D3D™ APIs are commonly known to those of ordinary skill, and more information on the same may be had by reference to the OpenGL® specification Version 2.1, which is incorporated herein by reference in its entirety.
As is well known, OpenGL® mandates a certain set of configurable computations defining transformation, texture coordinate generation and transformation, and lighting. Several extensions have been developed to provide further computations to OpenGL®.
As shown in
The functional module 302 is capable of carrying out programmable operations and supporting multiple levels of precision. Such levels of precision may include full floating point (i.e. 32-bit), half floating point (i.e. 16-bit), and fixed point. More information regarding the programmable operations and the various levels of precision will be set forth hereinafter in greater detail.
Coupled to the output of the functional module 302 is an input of a register file 308 having three outputs. The register file 308 is also equipped with a vector component writemask module 309. The register file 308 has single write and triple read access. The contents of the register file 308 are initialized to (0,0,0,0) at the start of program execution.
Also included are a pixel source buffer 312 and a constant source buffer 314. The pixel source buffer 312 stores data in the form of pixel data, and may be equipped with write access and/or at least single read access. The constant source buffer 314 stores data in the form of constant data, and may also be equipped with write access and/or at least single read access. It may be read using an absolute address.
In one exemplary embodiment, the pixel source buffer 312 is twelve (12) quad-floats in size (12*128 bits). Operation of the pixel processor module 58 may be commenced when all pixel attributes are valid. The position contains x and y in integer (D3D™) and +0.5 (OpenGL®) window coordinates, z is normalized to the range (0,1), and 1/w is in homogeneous clip space. Such attributes may be mandatory in the current exemplary embodiment. The pixel attributes may also be perspective correct. The colors and fog value may be generated at a lower precision, while the texture coordinates may be generated in high precision, i.e. 32-bit floating point.
Each of the inputs of the functional module 302 is equipped with a multiplexer 316. This allows the outputs of the register file 308, pixel source buffer 312, and constant source buffer 314 to be fed to the inputs of the functional module 302. This is facilitated by buses 318.
While not shown, the functional module 302 may also be coupled to a texture fetch module (not shown) for fetching texture data. Such texture fetch module may also be coupled to the register file 308. It should be noted that frame buffer contents are only visible to the pixel processing module 58 via texture fetches.
There need not necessarily be an explicit connection between texture coordinates and the textures that they may access. It is possible to use the same coordinate, or generated coordinates, to access any of the active textures as many times as desired and in any sequence desired. Programs are allowed access to sixteen (16) active textures. If an accessed texture is not bound, the texture fetch may return (0,0,0,0). The texture fetch instruction specifies the texture identifier desired (i.e. between 0 and 15). In one embodiment, texture components that are in fixed point form may have a bias (0.0,−0.5) and a multiply operation (2x, 1x) applied to them before they are returned to the pixel processing module 58. This capability need not necessarily apply to floating point texture components. A texture fetch may return the data at the destination precision.
The pixel processing module 58 of
Thereafter, in operation 404, programmable operations, i.e. pixel processing 102, are performed on the data in order to generate output. The programmable operations are capable of generating output that may be stored in the register file 308 in operation 406. During operation 408, the output stored in the register file 308 is used in performing the programmable operations on the data. Thus, the register file 308 may include any type of memory capable of allowing the execution of the programmable operations on the output.
By this design, the present invention allows a user to program a portion of the graphics pipeline that handles pixel processing. This results in an increased flexibility in generating visual effects. Further, the programmable pixel processing of the present invention allows remaining portions of the graphics pipeline to be controlled by the standard API for the purpose of preserving hardware optimizations.
During operation, only one pixel is processed at a time in the functional module 302 that performs the programmable operations. As such, the pixels may be processed independently. Further, the various foregoing operations may be processed for multiple pixels in parallel.
In one embodiment of the present invention, a constant may be received, and the programmable operations may be performed based on the constant. During operation, the constant may be stored in and received from the constant source buffer 314. Further, the constant may be accessed in the constant source buffer 314 using an absolute or relative address. As an option, there may be one or more address registers for use during reads from the constant source buffer 314. It may be initialized to “0” at the start of program execution in operation 204 of
The register file 308 may be equipped with single write and triple read access. Register contents may be initialized to (0,0,0,0) at the start of program execution in operation 204 of
An exemplary assembly language will now be set forth in the context of which the foregoing operations may be executed. Such language refers to a plurality of resources delineated in Table 2. Note the correspondence with the various components of the model 300 of
The data registers and memory locations include four component floating point precision. Further, the registers may be accessed as full floating point precision (fp32:R0-R7), half floating point precision (fp16:H0-H15), or signed 12-bit fixed point precision (s12:I0-I7). These overlap as follows: R0/H0-H1/I0-I1, R1/H2-H3/I2-I3, R2/H4-H5/I4-I5, etc.
Vector components may be swizzled before use via four subscripts (xyzw). An arbitrary component re-mapping may be done. Some examples are shown in Table 3.
All source operands (except condition codes) may be negated by putting a ‘−’ sign in front. The condition codes can be changed whenever data is written (by adding a ‘c’ to the op-code) and sharing the writemask with the destination. If there is no other destination, RC or HC or IC may be used as a dummy write register. When data is written, each component may compared to 0.0 and its status recorded if the writemask for that component is enabled.
The condition codes are sourced as EQ(equal), NE(not equal), LT(less), GE(greater or equal), LE(less or equal), GT(greater), FL(false), and TR(true), which generates four (4) bits of condition code by applying the specified comparison. As a source (for KIL and writemask modification), the condition codes may be swizzled.
Writes to the register, condition codes, and RC are maskable. Each component is written only if it appears as a destination subscript (from xyzw). Specifying no writemask is the same as a writemask of xyzw. No swizzling may be possible for writemask, and subscripts may be ordered (x before y before z before w). It is also possible to modify the write mask by the condition codes (at the beginning of the instruction) by an ‘AND’ operation as set forth in Table 4. It should be noted that condition codes here have swizzle control.
An exemplary assembler format is set forth in Table 5.
Valid sources are the pixel source, constants, and registers. Valid destinations are registers, RC, HC, and IC. Output data is taken from the register file 308. It should be noted that vertex programs use the functional module 302 for output. A particular API mode allows selection of an output format for the color and depth values, and whether the program will generate a new depth value.
A blend function and alpha testing may or may not be available based on the color output format. For example, a blend function and alpha testing may be available if the selected color format is four (4) unsigned bytes. The final color is taken from register R0, H0, or I0. The final color vector, regardless of the precision format, may be stored into a frame buffer assuming a similarly sized color buffer.
If a depth value is to be generated, the final value of R1.x, H1.x, or I1.x holds the new depth value. If depth is not to be generated, the standard pipeline depth is used. Depth is normalized to a (0,1) range which is clamped and scaled by hardware to fit the final depth buffer test format. The depth writemask may apply.
As mentioned earlier, three formats are supported for vector components. More information regarding precision will now be set forth in the context of an exemplary embodiment. Table 6 illustrates each of the various formats.
It may not necessarily be possible to mix formats inside a vector. Further, in one embodiment, no floating point exceptions or interrupts may be supported. Denorms may be flushed to zero, and NaN may be treated as infinity. Negative 0.0 may also be treated as positive 0.0 in comparisons.
In 32-bit floating point mode, the RCP and RSQ instructions may deliver mantissa results accurate to 1.0/(2**22). Moreover, the approximate output (.z) in the EXP and LOG instructions only have to be accurate to 1.0/(2**11). The LIT instruction output (.z) allows error equivalent to the combination of the EXP and LOG combination implementing a power function.
In 16-bit floating point mode, the RCP, RSQ, LOG, and EXP instructions deliver results accurate to within one least significant bit of the correct answer. LIT has at least the accuracy of a LOG, multiply, and EXP sequence in 16-bit floating point mode. In fixed point mode, all calculations are performed and then clamped into the valid range.
Since distance is calculated as (d*d)*(1/sqrt(d*d)), 0.0 multiplied by infinity may be 0.0. Since if/then/else evaluation is done by multiplying by 1.0/0.0 and adding the values set forth in Table 7.
In one embodiment, the registers may be grouped into 128-bit chunks, each of which may be used as a single 4*fp32 quad-float, two 4*fp16 quad-floats, or two 4*s12 quad-fixed point. There are eight (8) such chunks allowing a maximum of eight (8) registers in fp32 mode and sixteen (16) registers in fp16. It should be noted that there are only eight (8) s12 registers.
The present invention is allowed to use mixed precision registers as sources and destination to an instruction. In this case, conversion to destination precision is done before the instruction is executed. The instruction itself is performed at the destination precision.
If a 128-bit chunk is read in a different format from which it was last written, 0.0 is returned. Pixel source and constants may be in 32-bit floating point precision, but may be reduced to lower precision by the destination.
More information will now be set forth regarding each of the programmable operations 600 of
No Operation (NOP)
Format:
Description:
Examples:
Format:
Description:
The contents of the source vector are used as a texture coordinate indexing into the specified (via tid:0-15) texture map. The filtered vector resulting is placed into the destination as a quad-float. TEX generates a texture fetch of (x,y,z) while TXP generates a texture fetch of (x/w,y/w,z/w). TXD allows specification of the derivative in x (S1) and y (S2). These may be used for LOD/anisotropic calculations. TXD generates a texture fetch of (x,y,z).
Operation:
Table 8 sets forth an example of operation associated with the TEX, TXP, and TXD instructions.
Examples:
Format:
Description:
DDX operates to ensure that the rate of change of the components of the source with respect to the horizontal axis ‘X’ are placed into the destination.
Operation:
Table 9 sets forth an example of operation associated with the DDX instruction.
Examples:
Format:
Description:
DDY operates to ensure that the rate of change of the components of the source with respect to the vertical axis ‘Y’ is placed into the destination.
Operation:
Table 10 sets forth an example of operation associated with the DDY instruction.
Examples:
Format:
Description:
MOV operates to move the contents of the source into a destination.
Operation:
Table 11 sets forth an example of operation associated with the MOV instruction.
Examples:
Format:
Description:
MUL operates to multiply sources into a destination. It should be noted that 0.0 times anything is 0.0.
Operation:
Table 12 sets forth an example of operation associated with the MUL instruction.
Examples:
Format:
Description:
ADD serves to add sources into a destination.
Operation:
Table 13 sets forth an example of operation associated with the ADD instruction.
Examples:
Format:
Description:
MAD serves to multiply and add sources into a destination. It should be noted that 0.0 times anything is 0.0.
Operation:
Table 14 sets forth an example of operation associated with the MAD instruction.
Examples:
Format:
Description:
RCP inverts source scalar into a destination. The source may have one subscript. Output may be exactly 1.0 if the input is exactly 1.0.
RCP(−Inf) gives (−0.0,−0.0,−0.0,−0.0)
RCP(−0.0) gives (−Inf,−Inf,−Inf,−Inf)
RCP(+0.0) gives (+Inf,+Inf,+Inf,+Inf)
RCP(+Inf) gives (0.0,0.0,0.0,0.0)
Operation:
Table 15 sets forth an example of operation associated with the RCP instruction.
Examples:
Format:
Description:
RSQ performs an inverse square root of absolute value of source scalar into a destination. The source may have one subscript. Output may be exactly 1.0 if the input is exactly 1.0.
RSQ(0.0) gives (+Inf,+Inf,+Inf,+Inf)
RSQ(Inf) gives (0.0,0.0,0.0,0.0)
Operation:
Table 16 sets forth an example of operation associated with the RSQ instruction.
Examples:
Format:
Description:
DP3 performs a three component dot product of the sources into a destination. It should be noted that 0.0 times anything is 0.0.
Operation:
Table 17 sets forth an example of operation associated with the DP3 instruction.
Examples:
Format:
Description:
DP4 performs a four component dot product of the sources into a destination. It should be noted that 0.0 times anything is 0.0.
Operation:
Table 18 sets forth an example of operation associated with the DP4 instruction.
Examples:
Format:
Description:
DST calculates a distance vector. A first source vector is assumed to be (NA,d*d,d*d,NA) and second source vector is assumed to be (NA,1/d,NA,1/d). A destination vector is then (1,d,d*d,1/d). It should be noted that 0.0 times anything is 0.0.
Operation:
Table 19 sets forth an example of operation associated with the DST instruction.
Examples:
Format:
Description:
MIN serves to move a minimum of sources into a destination.
Operation:
Table 20 sets forth an example of operation associated with the MIN
Examples:
Format:
Description:
MAX moves a maximum of sources into a destination.
Operation:
Table 21 sets forth an example of operation associated with the MAX instruction.
Examples:
Format:
Description:
PK2 packs two source components (.xy after swizzle) into a destination. The destination may be a fp32 “R” register. The source components are converted into fp16 format and packed into a destination.
Operation:
Table 22 sets forth an example of operation associated with the PK2 instruction.
Examples:
PK2 R0.z,R3 //pack x,y components of R3 into R0.z
Pack4 (PK4)
Format:
Description:
PK4 packs four source components into a destination. The destination may be a fp32 “R” register. The source components are clamped to the range (−1.008,1.0) before being packed into a destination as unsigned 8 bit bytes.
Operation:
Table 23 sets forth an example of operation associated with the PK4 instruction.
Examples:
Format:
Description:
UP2 unpacks source component into a destination. The source may be a fp32 “R” register scalar. The source component is assumed to be a packed fp16 pair.
Operation:
Table 24 sets forth an example of operation associated with the UP2 instruction.
Examples:
UP2 R0.xy,R3.y //unpack two components of R3.y into R0.xy
Unpack4 (UP4)
Format:
Description:
UP4 unpacks source component into a destination. The source may be a fp32 “R” register scalar. The source component is assumed to be a packed unsigned 8-bit quartet and all are biased and scaled back into the range (−1.008,1.0) before assignment to destination.
Operation:
Table 25 sets forth an example of operation associated with the UP4 instruction.
Examples:
Format:
Description:
SLT sets the destination to 1.0/0.0 if source0 is less_than/greater_or_equal to source1. The following relationships should be noted:
Operation:
Table 26 sets forth an example of operation associated with the SLT instruction.
Examples:
Format:
Description:
SGE sets the destination to 1.0/0.0 if source0 is greater_or_equal/less_than source1.
Operation:
Table 27 sets forth an example of operation associated with the SGE instruction.
Examples:
Format:
Description:
FLR set the destination to floor of source.
Operation:
Table 28 sets forth an example of operation associated with the FLR instruction.
Examples:
Format:
Description:
FRC sets a destination to a fractional part of a source. The fraction is 0.0 <=fraction <1.0.
Operation:
Table 29 sets forth an example of operation associated with the FRC instruction.
Examples:
Format:
Description:
KIL kills the pixel based on any of the RC bits (post swizzle) being TRUE. KIL cannot set the condition codes.
Operation: Table 30 sets forth an example of operation associated with the KIL instruction.
Examples:
Format:
Description:
EXP generates an approximate answer in dest.z and allows for a more accurate answer of dest.x*FUNC(dest.y) where FUNC is some user approximation to 2**dest.y (0.0<=dest.y<1.0). EXP accepts a scalar sourceO. Reduced precision arithmetic is acceptable in evaluating dest.z.
EXP(−Inf) or underflow gives (0.0,0.0,0.0,1.0)
EXP(+Inf) or overflow gives (+Inf,0.0,+Inf,1.0)
Operation:
Table 31 sets forth an example of operation associated with the EXP instruction.
Examples:
Format:
Description:
LOG generates an approximate answer in dest.z and allows for a more accurate answer of dest.x+FUNC(dest.y) where FUNC is some user approximation of log2 (dest.y) (1.0<=dest.y<2.0). LOG accepts a scalar source0 of which the sign bit is ignored. LOG provides reduced precision arithmetic is acceptable in evaluating dest.z.
LOG(0.0) gives (−Inf,1.0,−Inf,1.0)
LOG(Inf) gives (Inf,1.0,Inf,1.0)
Operation:
Table 32 sets forth an example of operation associated with the LOG instruction.
Examples:
Format:
Description:
LIT provides lighting partial support. LIT calculates lighting coefficients from two dot products and a power. Source vector is:
Reduced precision arithmetic is acceptable in evaluating dest.z. Allowed error is equivalent to a power function combining the LOG and EXP instructions (EXP(w*LOG(y))). An implementation may support at least 8 fraction bits in the power. It should be noted that since 0.0 times anything may be 0.0, taking any base to the power of 0.0 yields 1.0.
Operation:
Table 33 sets forth an example of operation associated with the LIT instruction.
Examples:
Appendix A sets forth a plurality of programming examples.
Although the above description discloses a plurality of predefined instruction sets, e.g., as shown in
However, the present invention can be more broadly applied. Namely, the present invention allows any instructions that employ an arbitrary computed quantity or parameter as texture address. To state in another manner, the hardware that implements the shader is not limited to a predefined set of instruction sets. Instead, the shader can be implemented to be fully programmable such that any arbitrary computed quantity can be employed as texture address. The arbitrary quantity or parameter can be any parameters (e.g. per-pixel depth, depth, order, identifier, matte, intensity, etc.).
In step 710, method 700 fetches an instruction stream, e.g., a program for texture lookup. The instruction stream can be stored in a storage that can be accessed by pixel processor 58. In fact, the instruction stream can be written at a later time and loaded into a storage to be fetched by the pixel processor 58, thereby allowing pixel processor 58 to be fully programmable. This novel approach addresses the criticality where texture coordinates are limited to a small set of possible inputs, e.g., interpolated values and predefined simple functions. Removal of the restriction increases by a very large quantity the number of interesting pixel shader programs (instruction sets) that can be written. Additionally, this programmable approach will allow such programs to be written in a more efficient and flexible manner to produce a particular effect.
In step 720, the pertinent data is read, e.g., from a register. The pertinent data is defined by the fetched instruction stream.
In step 730, method 700 computes or performs a texture address calculation in accordance with a function defined by the fetched instruction stream. The calculation produces an arbitrary quantity that is stored in a storage, e.g., in a register or memory. It should be noted that step 730 can execute any functions, including one of the plurality of instructions as disclosed above. For example, the functions may include the result from one or more previous texture lookups, any mathematical function computable by a shader program including pseudorandom noise, solutions of partial differential and integral equations, and so on.
In step 740, method 700 queries whether a texture fetch operation or a texture look-up operation is performed. If the query is positively answered, then method 700 proceeds to step 745, where the computed arbitrary quantity is applied as texture address, i.e., texture information is retrieved during a texture look-up operation using the computed arbitrary quantity. If the query is negatively answered, then method 700 proceeds to step 750.
In step 750, method 700 queries whether another calculation is to be performed, e.g., whether additional shading operation 730 is to be performed. If the query is positively answered, then method 700 proceeds to step 730, where another iteration (steps 730-745) is executed. If the query is negatively answered, then method 700 proceeds to step 760.
In step 760, method 700 queries whether another or new instruction set is to be fetched. If the query is positively answered, then method 700 proceeds to step 710, and the steps 710-750 are repeated in accordance with the new instruction set. If the query is negatively answered, then method 700 ends in step 765.
In one embodiment of the present invention, the above pixel processor 58 implementing the present programmable methods can be perceived as a programmable “shader”. This programmable shader can be applied in a manner such that arbitrary texture filtering is achieved.
Specifically, many texture filtering modules are extremely limited in the type of filtering operations that can be performed. For example, many texture filtering modules are implemented to provide fixed bilinear filtering or trilinear filtering of a texture. When implemented in hardware, these texture filtering modules are rigidly limited in the predefined filtering functions, the shape of the filtering kernel, the size of the filtering kernel and so on. This criticality severely limits the benefits and flexibility of applying texture filtering. Thus, such texture filters are not directly applicable to high quality video, audio, photo, image, or any other type of data filtering.
To address this criticality, the present programmable shader is employed to provide arbitrary texture filtering without the constraints of traditional texture filtering modules that have fixed parameters. This approach allows the shader to perform the filtering functions of high quality filters which are non-linear in nature, e.g., to perform operations like deinterlacing and noise reduction. Additionally, video images are often in a different color space (YUV vs RGB) and the amplitude values are gamma pre-compensated (instead of linear perceptual space). In one embodiment, the present invention is capable of using modified elements of a traditional graphics pipeline (like textures) and a programmable pixel shader to perform video filtering.
More specifically, one novel aspect of the present invention is that the shader is programmable, has texture-fetch instructions e.g., tex, txp, txd and the like as discussed above and is capable of computing arbitrary filtering weights and functions. This programmability allows the present invention to compute arbitrary non-linear filters.
Specifically,
In step 810, method 800 performs a well known graphics processing step, generally referred to as geometry processing, where an object to be rendered is covered with a plurality of polygons, e.g., triangles. The geometry processing step produces position information pertaining to the triangles.
In step 820, an interpolation process is applied to the position information, e.g., applying projection so that the triangle is “perspective correct”. Generally, the interpolation processing step is a linear function. For example, the interpolation processing step generally produces interpolated values (pretexture data), e.g., texture coordinates.
In step 830, the programmable shader is able to optionally select and apply an arbitrary function, e.g., a linear or a nonlinear function, to the interpolated values to produce modified or arbitrary interpolated values. These arbitrary interpolated values are then provided to the texture unit in step 840 where texture information is derived from the arbitrary interpolated values, instead of using the traditional texture coordinates from the interpolation step 820.
Another way to view the present shader is that since the shader is programmable, it has the ability to execute texture-fetch instructions and to compute arbitrary filtering weights and functions. In doing so, the overall system is capable of effecting arbitrary non-linear filtering. Thus, in one instance, the programmable shader may actually implement a filtering function and in another instance, the shader may simply execute some programming steps or functions that when combined with a first texture filtering function results in the desired arbitrary texture filtering function. This ability to leverage existing texture filtering functions to effect arbitrary texture filtering functions is one advantage of the present invention.
In step 850, method 800 queries whether additional processing is desired or required. If the query is positively answered, then method 800 returns to step 830 where the same function or another function is selected and applied. It should be noted that depending on the arbitrary function that is currently being applied, method 800 may proceed to step 840 to effect another texture fetch or to simply bypass the texture step 840 and proceeds directly to step 850. If the query is negatively answered, then method 800 proceeds to step 860.
In step 860, method 800 queries whether there is a next pixel. If the query is positively answered, then method 800 returns to step 830 where the same function or another function is selected and applied. If the query is negatively answered, then method 800 ends in step 865 (e.g., where other image processing steps are continued). An important aspect of the present invention is that the application of the arbitrary function(s) can be applied on a pixel by pixel basis. Generally, traditional texture filtering is uniformly applied to all pixels which is a significant constraint.
To illustrate the benefits of the above arbitrary texture filtering method, an example is provided in the context of deinterlacing. Deinterlacing is the process of modifying an image sequence that is generated with odd frames (only odd lines are shown) and even frames (only even lines are shown), i.e., an odd frame is followed by an even frame, which is followed by another odd frame and so on. Such image sequence must be modified when displayed on a progressive display. Numerous interpolation processes can be applied with each interpolation process having some disadvantages depending on the content of the image sequence. Namely, one can interpolate between sequential odd frames, between sequence even frames or between sequential odd and even frames. Each of these three separate interpolation processes may exhibit artifacts, e.g., motion artifacts or blurriness. Depending on the content of the image sequence, one of these interpolation processes may be superior for a particular frame or even for a particular pixel.
In traditional texture filtering, generally one of these processes is selected and is applied to all the pixels. In contrast, the present invention can now evaluate the results of all three processes on a pixel by pixel basis to select the best result. In operation, the arbitrary function in step 830 can be selectively changed, i.e., to implement all three processes via three passes or iterations and then decide which result is best for a particular pixel. It should be noted that functions performed by the texture unit in step 840 can remain the same, but modified or arbitrary interpolated values are provided as inputs to the texture unit by the programmable shader in step 830. Thus, the present approach provides for backward compatibility where existing texture unit can still be used in conjunction with the present programmable shader. Thus, the present invention provides an extremely flexible method where any addresses for textures can be generated to produce any texture samples, which, in turn, can be combined in any manner as desired by the programmable shader. In fact, the various texture filtering functions can be adjusted, e.g., they can be adjusted for said each pixel of a primitive.
Another example of the flexibility of the present approach is that it can be implemented to provide spatially-variant filtering. That is, texture filtering where the kernel shape and kernel size are selected per pixel based on any arbitrary function (e.g. the fragment Z). Namely, traditional texture filtering may select a 2×2 block of texels to perform interpolation. However, using the present invention, the selected texels do not have to be adjacent texels and, in fact, the 2×2 block. can be modified into an arbitrary n×n block of texels, i.e., the term spatially-variant.
In one embodiment, the programmable shader is able to read several texture samples per fragment and compute a filtered (weighted) average of those samples to become the filtered texel result for the fragment. For example, the texture unit can only do linear filtering of a texture, but aided by the programmable shader, the present invention can apply bicubic or gaussian filtering and any other linear and non-linear filtering of texture data.
In fact, it is observed that the present invention can be implemented to provide several novel texture filtering functions. For example, the following functions can be achieved:
In other words, tap[i,j] in the above equation is replaced by f(tap[i,j]), where f( ) converts from a non-linear (gamma-precompensated) color space to a linear color space, and the result of the summation is replaced by f(result) to convert back to gamma-precompensated space from linear space.
It should be noted that methods 700 and 800 and/or some of the steps of methods 700 and 800 may be represented by one or more software applications (or even a combination of software and hardware, e.g., using application specific integrated circuits (ASICS)), where the software is loaded from a storage medium, (e.g., a magnetic or optical drive, a diskette or a ROM) and operated by the CPU in the memory of a computing device. As such, the methods (including associated steps and data structures) of the present invention can be stored on a computer readable medium, e.g., RAM memory, ROM, magnetic or optical drive or diskette and the like.
While various embodiments have been described above, it should be understood that they have been presented by way of example only, and not limitation. Thus, the breadth and scope of a preferred embodiment should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.
The #define statements are meant for a cpp run.
1)
; Absolute Value H4=abs(R0)
MAX H4,R0,−R0;
2)
;Cross Product |ijk| into R2
;|R0.x R0.y R0.z|
;|R1.x R1.y R1.z|
MUL R2,R0.zxyw,R1.yzxw;
MAD R2,R0.yzxw,R1.zxyw,−R2;
4)
; reduce R1 to fundamental period
#define PERIOD 70; location PERIOD is 1.0/(2*PI),2*PI,0.0,0.0
MUL R0,R1,c[PERIOD].x; //divide by period
FRC R2,R0;
MUL R2,R2,c[PERIOD].y; //multiply by period
5)
; H4=p→weight.x*H2+(1.0-p→weight.x)*H3
#define IWGT 8; source weight
ADD H4,H2,−H3; //LERP
MAD H4,p[IWGT].x,H4,H3;
6)
;R0=(GT.x∥LT.y) ? R1:R2;
MOV R0,R2;
MOV R0(GT.x),R1;
MOV R0(LT.y),R1;
7)
;R0.y=(EQ.xzw&<.y) ? R1.z:R2.w;
MOV R0.y,R1.z;
MOV R0.y(NE.xzww),R2.w;
MOV R0.y(GE.y),R2.w;
This application is a continuation-in-part of U.S. application Ser. No. 09/885,382, filed Jun. 19, 2001 now U.S. Pat. No. 6,870,540, which is a continuation-in-part of an application entitled “SYSTEM, METHOD AND ARTICLE OF MANUFACTURE FOR A PROGRAMMABLE VERTEX PROCESSING MODEL WITH INSTRUCTION SET” filed May 31, 2000 under Ser. No. 09/586,249 now U.S. Pat. No. 7,209,140, and an application entitled “METHOD, APPARATUS AND ARTICLE OF MANUFACTURE FOR TRANSFORMING, LIGHTING AND RASTERIZATION ON A SINGLE SEMICONDUCTOR PLATFORM” filed Dec. 6, 1999 under Ser. No. 09/454,516 now U.S. Pat. No. 6,198,488. These applications are herein incorporated by reference. The present invention relates to computer graphics, and more particularly to providing programmability in a computer graphics processing pipeline.
| Number | Name | Date | Kind |
|---|---|---|---|
| 5805782 | Foran | Sep 1998 | A |
| 5812141 | Kamen et al. | Sep 1998 | A |
| 6292193 | Perry et al. | Sep 2001 | B1 |
| 6690427 | Swan | Feb 2004 | B2 |
| 6825850 | Wang et al. | Nov 2004 | B2 |
| 20020003541 | Boyd et al. | Jan 2002 | A1 |
| 20020171656 | Lavelle et al. | Nov 2002 | A1 |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 09885382 | Jun 2001 | US |
| Child | 10449646 | US | |
| Parent | 09586249 | May 2000 | US |
| Child | 09885382 | US | |
| Parent | 09454516 | Dec 1999 | US |
| Child | 09586249 | US |
