Patent Application
20130094817
This application claims priority to foreign French patent application No. FR 1103141, filed on Oct. 14, 2011, the disclosure of which is incorporated by reference in its entirety.
The present invention pertains to a system of at least one assembly comprising at least one integrated circuit, the said integrated circuits being interconnected according to a matrix architecture of N rows and M columns of integrated circuits.
Systems of at least one assembly of at least one integrated circuit are known, the said integrated circuits being interconnected according to a matrix architecture of integrated circuits, in which the integrated circuits are linked together by electrical connections, some being of high-throughput fast serial interface type, of frequency considerably greater than 100 MHz.
The expression integrated circuit is intended to mean an electronic component carrying out a more or less complex electronic function, and often integrating several types of elementary electronic components in a package of reduced volume. Logic gates are the simplest digital integrated circuits, microprocessors and memories figure among the most complex. There are integrated circuits dedicated to specific applications such as application specific integrated circuits or ASICs, notably for signal processing; one then speaks of digital signal processor or DSP. An important family of integrated circuits is that of the programmable logic component or FPGA for “Field Programmable Gate Array”.
The expression hybrid module is intended to mean a component integrating into one and the same package an assembly of interconnected circuits, optionally embodied in various technologies, and being able to process signals of various natures (analogue, radio-frequency, digital, optical).
The processing tasks are farmed out to a plurality of operators, which may be integrated circuits, hybrid modules or circuits, which are assembled on electronic cards within items of equipment. In what follows, the term integrated circuit is used also for hybrid modules.
In what follows, the organization in rows or in columns results from an arbitrary choice, the role of the rows and columns being freely permutable.
Considering processing tasks carried out on an assembly of circuits organized column-wise, the primary source inputs of a row of the system are transmitted to the whole assembly of columns, therefore to the whole assembly of integrated circuits of the same row. With electrical interfaces of point-to-point fast serial type, a known technique consists in propagating the source data gradually over one and the same row, an integrated circuit transmits the data received on its source inputs to the following integrated circuit of the same row, and carries out processing tasks whose results are transmitted to the following circuit of the same column.
The main benefit of such a system resides in its functional simplicity and its modularity. In particular, the numbers of inputs and outputs of the system may be adjusted by adding rows or columns. On the other hand, for complex requirements, this type of system calls upon a large number of integrated circuits and electronic cards, and a large number of interconnections and interfaces. This type of system consumes a great deal of energy, and requires significant area and significant mass, a large share of which is due to the interfaces themselves.
American patent application US 2005/0256969 A1 pertains to the electrical interconnection of digital circuits with fast serial links, integrating a packet switch within each circuit. Thus, it discloses a reconfigurable architecture based on programmable gate arrays or FPGAs.
Document U.S. Pat. No. 4,811,210 is aimed at implementing various functions and various types of algorithms, on one and the same computer, using a reconfigurable and parallel architecture. The proposed solution comprises groups of processors integrating respectively an optical switch to configure and modify the interconnections within the group and optical switches for exchanges between the groups.
This mode of hardware organization is not very appropriate for a matrix architecture with hard-wired logic specific for an application, and does not make it possible notably to reduce the complexity and energy consumption thereof.
Document U.S. Pat. No. 4,696,059 is aimed at implanting functions for fast signal processing (programmable filter, word generator, programmable delay line), whereas the elementary delay functions are either insufficiently fast, or not adjustable. The proposed solution comprises an optoelectronic switch and groups of delay functions, either electrical or optical. The elements, in optical technology, make it possible to achieve the speed requirement of the elementary delay function. The switch makes it possible to dynamically configure the connectivity between the primary inputs and the inputs/outputs of the delay functions, so as to synthesize various delay values, to construct filters or word generators.
This architecture does not make it possible to construct a complex matrix system comprising a large number of operators and of integrated circuits and carrying out complex processing tasks.
An aim of the invention is to alleviate the problems cited above.
There is proposed, according to one aspect of the invention, a system of at least one assembly of at least one integrated circuit, the said integrated circuits being interconnected according to a matrix architecture of N rows and M columns of integrated circuits. A row receives at least one input for signals, and a column provides at least one output for signals. The interconnections between two integrated circuits of a row of one and the same assembly and the interconnections between two integrated circuits of a column of one and the same assembly are electrical. An assembly of at least one integrated circuit comprises at least one input integrated circuit comprising at least one input of the said assembly and at least one output integrated circuit comprising at least one output of the said assembly, an input integrated circuit being able also to be an output integrated circuit. Furthermore, the system comprises at least one optical interconnection for connecting an input of a row of the system to a respective input of the input integrated circuits of the assemblies belonging to the said row, or for connecting a respective output of the output integrated circuits of the assemblies belonging to a column of the system to the system output of the said column.
Such a system makes it possible to significantly reduce the requirement as regards fast serial interfaces within the integrated circuits, and as a consequence the energy consumption and complexity of implantation, in terms of quantity of circuits and of electronic cards. With a requirement reduced by up to half as regards the number of fast serial interfaces in the integrated circuits, this system allows better use of the resources and the input and output ports of the integrated circuits, and reduces the complexity of the equipment.
The use of optical links makes it possible generally to increase the bandwidth, and to drastically reduce the mass and bulkiness of the links and connectors.
In one embodiment, an assembly of at least one integrated circuit is implanted in a single electronic card.
Thus, the production of such a system may be carried out on the basis of a plurality of copies of one and the same card, thereby facilitating the production of the system and lowering its production cost.
According to one embodiment, an optical interconnection comprises an optical coupler and/or active optoelectronic coupling means and an optical link per input of input integrated circuit of the assemblies of a row or per output of output integrated circuit of the assemblies of a column.
Thus, the optical links make it possible to carry out simply the distributing of the signals at high-throughput from a point to a plurality of points, and/or to combine an assembly of outputs originating from several integrated circuits, without appreciably affecting the throughput and the quality of the signals at the interfaces.
Advantageously, at least one row optical interconnection comprises, furthermore, a test optical link.
Thus, it is possible to put in place non-intrusive test/monitoring means, to observe the signals without disturbing the operation of the system, or inject test signals into the system.
For example, an optical link comprises optical fibre.
The use of optical fibre makes it possible among other things to increase the bandwidth or the distance of transmission, to guarantee good isolation between the various links, or to facilitate the physical implantation of the links.
According to one embodiment, at least one row optical interconnection comprises, furthermore, an optical amplifier.
Thus, the power of the optical signal to be apportioned by the outputs of an optical coupler may be matched to suit the apportionment requirement, so as to guarantee the transmission performance of the links.
In one embodiment, several row optical interconnections may be linked at input by at least one optical switch, and/or several column optical interconnections may be linked at output by at least one optical switch.
It is thus possible to implement redundancy management, notably for onboard systems, for example embedded aboard satellites, by configuring optical switches, whose dissipation is independent of the throughputs processed.
According to one embodiment, at least one optical link is adapted for carrying out a wavelength division multiplexing.
In one embodiment, the system comprises at least one assembly of integrated circuits as redundancy, featuring optical links.
For example, the system such as described above may be adapted for carrying out a function of digital beam forming of phased array antenna, and/or for carrying out a switching function.
There is also proposed, according to another aspect of the invention, a processor comprising at least one system such as described above.
There is also proposed, according to another aspect of the invention, a satellite comprising at least one processor such as described above embedded aboard.
There is also proposed, according to another aspect of the invention, a method for interconnecting at least one assembly of at least one integrated circuit, according to a matrix architecture of n1 rows and n2 columns of integrated circuits, a row receiving at least one input for signals, and a column providing at least one output for signals, the interconnections between two integrated circuits of a row of one and the same assembly and the interconnections between two integrated circuits of a column of one and the same assembly being carried out electrically, and an assembly of at least one integrated circuit comprising at least one input integrated circuit comprising at least one input of the said assembly and at least one output integrated circuit comprising at least one output of the said assembly, an input integrated circuit being able optionally to be also an output integrated circuit. Furthermore, at least one input of a row of the system is interconnected optically to a respective input of the input integrated circuits of the assemblies, belonging to the said row, or at least one output of a column of the system is interconnected optically to a respective output of the output integrated circuits of the assemblies, belonging to the said column.
The invention will be better understood on studying a few embodiments described by way of wholly non-limiting examples and illustrated by the appended drawings in which:
In all the figures, elements having identical references are similar.
and b integer varying from 1 to
the said integrated circuits CIi,ja,b (i integer varying from 1 to 2 and j integer varying from 1 to 2) being interconnected according to a matrix architecture of n1 rows and n2 columns of integrated circuits CIi,ja,b. Of course, this example of four integrated circuits per assembly Ea,b is wholly non-limiting, and the variations of the indices a and b of the assemblies Ea,b depend on the number of integrated circuits per assembly Ea,b.
A row k of integrated circuits (k integer varying from 1 to n1) receives at least one input for signals, in this instance three inputs, and a column I of integrated circuits (I integer varying from 1 to n2) provides at least one output for signals, in this instance four outputs.
The interconnections between two integrated circuits of a row k of one and the same assembly Ea,b, when this assembly comprises more than one integrated circuit per row, and the interconnections between two integrated circuits of a column I, when this assembly comprises more than one integrated circuit per column, are electrical.
An assembly Ea,b of at least one integrated circuit CIi,ja,b comprises at least one input integrated circuit, i.e. receiving input signals from outside the assembly, and at least one output integrated circuit, i.e. delivering output signals outside the assembly. An input integrated circuit can optionally be simultaneously an output integrated circuit. In this instance, in the example of
The system comprises at least one optical interconnection IO, in this instance 3×n1+4×n2 optical interconnections, for connecting an input of a row of the system to a respective input of the input integrated circuits of the assemblies belonging to this row (3×n1 optical interconnections since in this example the integrated circuits all have three inputs belonging to optical interconnections), or for connecting an output of a column of the system to a respective output of the output integrated circuits of the assemblies belonging to this column (4×n2 optical interconnections since in this example the integrated circuits all have four outputs belonging to optical interconnections).
The optical interconnections IO each comprise an optical coupler CO and an optical link LO per input of input integrated circuit of the assemblies of a row (in this instance
optical links per coupler) or per output of output integrated circuit of the assemblies of a column (in this instance
optical links per coupler).
The expression optical coupler is intended to mean a passive optical device comprising one or more optical input ports and one or more optical output ports, apportioning each of the input signals over the whole assembly of output ports.
As a variant, it is possible to use, on emission, an active optoelectronic coupling device comprising an electrical input port and several optical emitters, each being connected to an optical output port, and apportioning the electrical input signal over the whole assembly of optical output ports.
As a variant, it is possible to use, on reception, an active optoelectronic coupling device, comprising several optical input ports each being connected to an optical detector and an electrical output port, and collecting the optical input signals towards the electrical output port.
In all the examples, the optical links LO can comprise optical fibre.
The optical apportionment of the signals lends itself to the switching of redundant operators, by using the capacity for distributing with the aid of optical couplers CO, and through the implementation of optical switches COM. The switching of the redundancies may be carried out in various ways: by entire column, by processing pathway, by electronic card or circuit, by row, or by data pathway, it being possible for the redundancies to be mutualized at various levels.
In
Within a row of operators, the r redundant operators receive by optical distribution the data to be processed, like the Y nominal operators. In this configuration, the vertical processing pathways also comprise optical links.
Optical couplers CO with two inputs and two outputs are associated with the nominal operators so as to distribute the processed partial terms arising from the row upstream either of the nominal operator (of the same column), or of a redundant operator, destined for the nominal operator and the redundancy group associated with the row. For each row, the redundancy group is switched with the aid of two optical switches COM, so as to switch the processing pathways at input and at output. These optical switches carry out the switching between the assembly of the processing pathways for the nominal operators and the assembly of the processing pathways for the redundant operators.
This configuration makes it possible to substitute an available redundant operator for any failed nominal operator, and to do so within each row. The use of redundancy is more effective than in the case of the redundancy switching per entire column (or function).
The per-row redundancy capacity is exhausted when at least r+1 failed operators are concentrated in one and the same row. This system can therefore tolerate up to r×n1 failures of operators.
This variant is more regular than the system of
At the output of the last row of operators, only Y physical outputs are retained. With half as many switches COM, this variant is simpler than the previous one, the propagation of Y+r pathways instead of Y (useful) pathways not being penalizing (r<<Y). On the other hand, the complexity of the optical switches COM is slightly increased, without posing any difficulties in practice, on account of the symmetry of the numbers of input and output ports and since Y+r is hardly different from Y.
Starting from the third variant, the redundancy capacity is increased by adding u redundant rows to the T rows of operators. This makes it possible to replace up to u rows of operators whose redundancy capacity has been exhausted (i.e. more than r failed operators).
An optical switch COM at the data side input carries out the switching of the T rows of inputs to the assembly of T+u rows of operators. An operator row may be unused, either when dealing with an inactive redundancy, or when the redundancy capacity of this row is exhausted by an excess of failures. In this case, the (vertical) flows of partial terms arising from the upstream rows must pass through the inactive row in a transparent manner. A solution consists in locally distributing each upstream partial term flow via a coupler to an input and two outputs distributing to each operator as well as to a so-called bypass pathway. A switch COM with two inputs and an output downstream of the operator makes it possible to select either the operator's processing output, or the bypass pathway, at input of the output switch Y+r:Y+r.
This solution offers better redundancies usage effectiveness than the variant managing the redundancy per row, at the price of increased complexity. Indeed, on top of the capacity to support up to any r failures per row, the addition of u redundant rows makes it possible furthermore to support up to u rows with more than r failures.
The optical interfaces of
A known variant for multiplexing data flows on an optical pathway is wavelength division multiplexing (WDM), each data flow being carried by a specific wavelength.
The use of WDM wavelength multiplexing on the proposed schemes is particularly effective since it makes it possible to directly reduce the density of optical interconnections, and as a consequence the complexity of the optical switches COM. Multiplexing relates to data flows apportioned according to one and the same topology, this being the case for the matrix digital architectures such as defined, both for the distributing of the data pathways and for the apportioning of the processing pathways (partial terms).
| Number | Date | Country | Kind |
|---|---|---|---|
| 11 03141 | Oct 2011 | FR | national |
