System on chip (SoC) builder

Description

BACKGROUND
Field

Methods and example implementations described herein are generally directed to an interconnect architecture, and more specifically, to System on Chip (SoC) design and verification system and method that constructs SoC from functional building blocks circuits while concurrently taking into account numerous chip level design aspects along with the generation of a simulation environment for design verification.

Related Art

The number of components on a chip is rapidly growing due to increasing levels of integration, system complexity and shrinking transistor geometry. Complex System-on-Chips (SoCs) may involve a variety of components e.g., processor cores, DSPs, hardware accelerators, memory and I/O, while Chip Multi-Processors (CMPs) may involve a large number of homogenous processor cores, memory and I/O subsystems. In both SoC and CMP systems, the on-chip interconnect plays a role in providing high-performance communication between the various components. Due to scalability limitations of traditional buses and crossbar based interconnects, Network-on-Chip (NoC) has emerged as a paradigm to interconnect a large number of components on the chip. NoC is a global shared communication infrastructure made up of several routing nodes interconnected with each other using point-to-point physical links.

Messages are injected by the source and are routed from the source node to the destination over multiple intermediate nodes and physical links. The destination node then ejects the message and provides the message to the destination. For the remainder of this application, the terms ‘components’, ‘blocks’, ‘hosts’ or ‘cores’ will be used interchangeably to refer to the various system components which are interconnected using a NoC. Terms ‘routers’ and ‘nodes’ will also be used interchangeably. Without loss of generalization, the system with multiple interconnected components will itself be referred to as a ‘multi-core system’.

There are several topologies in which the routers can connect to one another to create the system network. Bi-directional rings (as shown in FIG. 1A, 2-D (two dimensional) mesh (as shown in FIG. 1B), and 2-D Torus (as shown in FIG. 1C) are examples of topologies in the related art. Mesh and Torus can also be extended to 2.5-D (two and half dimensional) or 3-D (three dimensional) organizations. FIG. 1D shows a 3D mesh NoC, where there are three layers of 3×3 2D mesh NoC shown over each other. The NoC routers have up to two additional ports, one connecting to a router in the higher layer, and another connecting to a router in the lower layer. Router 111 in the middle layer of the example has its ports used, one connecting to the router 112 at the top layer and another connecting to the router 110 at the bottom layer. Routers 110 and 112 are at the bottom and top mesh layers respectively and therefore have only the upper facing port 113 and the lower facing port 114 respectively connected.

Packets are message transport units for intercommunication between various components. Routing involves identifying a path that is a set of routers and physical links of the network over which packets are sent from a source to a destination. Components are connected to one or multiple ports of one or multiple routers; with each such port having a unique identification (ID). Packets can carry the destination's router and port ID for use by the intermediate routers to route the packet to the destination component.

Examples of routing techniques include deterministic routing, which involves choosing the same path from A to B for every packet. This form of routing is independent from the state of the network and does not load balance across path diversities, which might exist in the underlying network. However, such deterministic routing may implemented in hardware, maintains packet ordering and may be rendered free of network level deadlocks. Shortest path routing may minimize the latency as such routing reduces the number of hops from the source to the destination. For this reason, the shortest path may also be the lowest power path for communication between the two components. Dimension-order routing is a form of deterministic shortest path routing in 2-D, 2.5-D, and 3-D mesh networks. In this routing scheme, messages are routed along each coordinates in a particular sequence until the message reaches the final destination. For example in a 3-D mesh network, one may first route along the X dimension until it reaches a router whose X-coordinate is equal to the X-coordinate of the destination router. Next, the message takes a turn and is routed in along Y dimension and finally takes another turn and moves along the Z dimension until the message reaches the final destination router. Dimension ordered routing may be minimal turn and shortest path routing.

FIG. 2A pictorially illustrates an example of XY routing in a two dimensional mesh. More specifically, FIG. 2A illustrates XY routing from node ‘34’ to node ‘00’. In the example of FIG. 2A, each component is connected to only one port of one router. A packet is first routed over the X-axis till the packet reaches node ‘04’ where the X-coordinate of the node is the same as the X-coordinate of the destination node. The packet is next routed over the Y-axis until the packet reaches the destination node.

In heterogeneous mesh topology in which one or more routers or one or more links are absent, dimension order routing may not be feasible between certain source and destination nodes, and alternative paths may have to be taken. The alternative paths may not be shortest or minimum turn.

Source routing and routing using tables are other routing options used in NoC. Adaptive routing can dynamically change the path taken between two points on the network based on the state of the network. This form of routing may be complex to analyze and implement.

A NoC interconnect may contain multiple physical networks. Over each physical network, there exist multiple virtual networks, wherein different message types are transmitted over different virtual networks. In this case, at each physical link or channel, there are multiple virtual channels; each virtual channel may have dedicated buffers at both end points. In any given clock cycle, only one virtual channel can transmit data on the physical channel.

NoC interconnects may employ wormhole routing, wherein, a large message or packet is broken into small pieces known as flits (also referred to as flow control digits). The first flit is a header flit, which holds information about this packet's route and key message level info along with payload data and sets up the routing behavior for all subsequent flits associated with the message. Optionally, one or more body flits follows the header flit, containing remaining payload of data. The final flit is a tail flit, which, in addition to containing last payload, also performs some bookkeeping to close the connection for the message. In wormhole flow control, virtual channels are often implemented.

The physical channels are time sliced into a number of independent logical channels called virtual channels (VCs). VCs provide multiple independent paths to route packets, however they are time-multiplexed on the physical channels. A virtual channel holds the state needed to coordinate the handling of the flits of a packet over a channel. At a minimum, this state identifies the output channel of the current node for the next hop of the route and the state of the virtual channel (idle, waiting for resources, or active). The virtual channel may also include pointers to the flits of the packet that are buffered on the current node and the number of flit buffers available on the next node.

The term “wormhole” plays on the way messages are transmitted over the channels: the output port at the next router can be so short that received data can be translated in the head flit before the full message arrives. This allows the router to quickly set up the route upon arrival of the head flit and then opt out from the rest of the conversation. Since a message is transmitted flit by flit, the message may occupy several flit buffers along its path at different routers, creating a worm-like image.

Based upon the traffic between various end points, and the routes and physical networks that are used for various messages, different physical channels of the NoC interconnect may experience different levels of load and congestion. The capacity of various physical channels of a NoC interconnect is determined by the width of the channel (number of physical wires) and the clock frequency at which it is operating. Various channels of the NoC may operate at different clock frequencies, and various channels may have different widths based on the bandwidth requirement at the channel. The bandwidth requirement at a channel is determined by the flows that traverse over the channel and their bandwidth values. Flows traversing over various NoC channels are affected by the routes taken by various flows. In a mesh or Torus NoC, there exist multiple route paths of equal length or number of hops between any pair of source and destination nodes. For example, in FIG. 2B, in addition to the standard XY route between nodes 34 and 00, there are additional routes available, such as YX route 203 or a multi-turn route 202 that makes more than one turn from source to destination.

In a NoC with statically allocated routes for various traffic slows, the load at various channels may be controlled by intelligently selecting the routes for various flows. When a large number of traffic flows and substantial path diversity is present, routes can be chosen such that the load on all NoC channels is balanced nearly uniformly, thus avoiding a single point of bottleneck. Once routed, the NoC channel widths can be determined based on the bandwidth demands of flows on the channels. Unfortunately, channel widths cannot be arbitrarily large due to physical hardware design restrictions, such as timing or wiring congestion. There may be a limit on the maximum channel width, thereby putting a limit on the maximum bandwidth of any single NoC channel.

Additionally, wider physical channels may not help in achieving higher bandwidth if messages are short. For example, if a packet is a single flit packet with a 64-bit width, then no matter how wide a channel is, the channel will only be able to carry 64 bits per cycle of data if all packets over the channel are similar. Thus, a channel width is also limited by the message size in the NoC. Due to these limitations on the maximum NoC channel width, a channel may not have enough bandwidth in spite of balancing the routes.

To address the above bandwidth concern, multiple parallel physical NoCs may be used. Each NoC may be called a layer, thus creating a multi-layer NoC architecture. Hosts inject a message on a NoC layer; the message is then routed to the destination on the NoC layer, where it is delivered from the NoC layer to the host. Thus, each layer operates more or less independently from each other, and interactions between layers may only occur during the injection and ejection times. FIG. 3A illustrates a two layer NoC. Here the two NoC layers are shown adjacent to each other on the left and right, with the hosts connected to the NoC replicated in both left and right diagrams. A host is connected to two routers in this example—a router in the first layer shown as R1, and a router is the second layer shown as R2. In this example, the multi-layer NoC is different from the 3D NoC, i.e. multiple layers are on a single silicon die and are used to meet the high bandwidth demands of the communication between hosts on the same silicon die. Messages do not go from one layer to another. For purposes of clarity, the present application will utilize such a horizontal left and right illustration for multi-layer NoC to differentiate from the 3D NoCs, which are illustrated by drawing the NoCs vertically over each other.

In FIG. 3B, a host connected to a router from each layer, R1 and R2 respectively, is illustrated. Each router is connected to other routers in its layer using directional ports 301, and is connected to the host using injection and ejection ports 302. A bridge-logic 303 may sit between the host and the two NoC layers to determine the NoC layer for an outgoing message and sends the message from host to the NoC layer, and also perform the arbitration and multiplexing between incoming messages from the two NoC layers and delivers them to the host.

In a multi-layer NoC, the number of layers needed may depend upon a number of factors such as the aggregate bandwidth requirement of all traffic flows in the system, the routes that are used by various flows, message size distribution, maximum channel width, etc. Once the number of NoC layers in NoC interconnect is determined in a design, different messages and traffic flows may be routed over different NoC layers. Additionally, one may design NoC interconnects such that different layers have different topologies in number of routers, channels and connectivity. The channels in different layers may have different widths based on the flows that traverse over the channel and their bandwidth requirements. With such a large variety of design choices, determining the right design point for a given system remains challenging and remains a time consuming manual process, and often the resulting designs remains sub-optimal and inefficient. A number of innovations to address these problems are described in U.S. patent application Ser. Nos. 13/658,663, 13/752,226, 13/647,557, 13/856,835, 13/723,732, the contents of which are hereby incorporated by reference in their entirety.

System on Chips (SoCs) are becoming increasingly sophisticated, feature rich, and high performance by integrating a growing number of standard processor cores, memory and I/O subsystems, and specialized acceleration IPs. To address this complexity, NoC approach of connecting SoC components is gaining popularity. A NoC can provide connectivity to a plethora of components and interfaces and simultaneously enable rapid design closure by being automatically generated from a high level specification. The specification describes interconnect requirements of SoC in terms of connectivity, bandwidth, and latency. In addition to this, information such as position of various components such as bridges or ports on boundary of hosts, traffic information, chip size information, etc. may be supplied. A NoC compiler (topology generation engine) can then use this specification to automatically design a NoC for the SoC. A number of NoC compilers were introduced in the related art that automatically synthesize a NoC to fit a traffic specification. In such design flows, the synthesized NoC is simulated to evaluate the performance under various operating conditions and to determine whether the specifications are met. This may be necessary because NoC-style interconnects are distributed systems and their dynamic performance characteristics under load are difficult to predict statically and can be very sensitive to a wide variety of parameters. Specifications can also be in the form of power specifications to define power domains, voltage domains, clock domains, and so on, depending on the desired implementation.

Placing hosts/IP cores in a SoC floorplan to optimize the interconnect performance can be important. For example, if two hosts communicate with each other frequently and require higher bandwidth than other interconnects, it may be better to place them closer to each other so that the transactions between these hosts can go over fewer router hops and links and the overall latency and the NoC cost can be reduced.

Assuming that two hosts with certain shapes and sizes cannot spatially overlap with each other on a 2D SoC plane, tradeoffs may need to be made. Moving certain hosts closer to improve inter-communication between them, may force certain other hosts to be further apart, thereby penalizing inter-communication between those other hosts. To make tradeoffs that improve system performance, certain performance metrics such as average global communication latency may be used as an objective function to optimize the SoC architecture with the hosts being placed in a NoC topology. Determining substantially optimal host positions that maximizes the system performance metric may involve analyzing the connectivity and inter-communication properties between all hosts and judiciously placing them onto the 2D NoC topology. In case if inter-communicating hosts are placed far from each other, this can leads to high average and peak structural latencies in number of hops. Such long paths not only increase latency but also adversely affect the interconnect bandwidth, as messages stay in the NoC for longer periods and consume bandwidth of a large number of links.

In large-scale networks, efficiency and performance/area tradeoff is of main concern. Mechanisms such as machine learning approach, simulated annealing, among others, provide optimized topology for a system. However, such complex mechanisms have substantial limitations as they involve certain algorithms to automate optimization of layout network, which may violate previously mapped flow's latency constraint or the latency constraint of current flow. Further, it is also to be considered that each user has their own requirements and/or need for SoCs and/or NoCs depending on a diverse applicability of the same. Therefore, there is a need for systems and methods that significantly improve system efficiency by accurately indicating the best possible positions and configurations for hosts and ports within the hosts, along with indicating system level routes to be taken for traffic flows using the NoC interconnect architecture. Systems and methods are also required for automatically generating an optimized topology for a given SoC floor plan and traffic specification with an efficient layout. Further, systems and methods are also required that allows users to specify their requirements for a particular SoC and/or NoC, provides various options for satisfying their requirements and based on this automatically generating an optimized topology for a given SoC floor plan and traffic specification with an efficient layout.

Furthermore, a system and method is required that facilitates efficient creation of SoC designs utilizing existing circuit block information. The system and method should assist a designer to design SoC in a convenient manner and facilitate incorporation of building block circuits previously tested in silicon. The system and method should reduce the amount of data a user has to enter manually to adequately describe features of the circuit being designed or analyzed

Therefore, there exists a need for methods, systems, and computer readable mediums for overcoming the above-mentioned issues with existing implementations of generating topology for a given NoC/SoC.

SUMMARY

Aspects of the present disclosure relate to methods, systems, and computer readable mediums for overcoming the above-mentioned issues with existing implementations of generating topology for a given SoC by significantly improving system efficiency by facilitating efficient creation of SoC designs utilizing existing or new circuit block information. The system and method assist a designer to design SoC in a convenient manner and facilitate incorporation of building block circuits previously tested in silicon. The system and method reduces the amount of data a user has to enter manually to adequately describe features of the circuit being designed or analyzed

Further, methods, systems, and computer readable mediums are provided that facilitates efficient and effective creation, modification and verification of electrical circuit designs utilizing a new or existing circuit block designs. The System on Chip (SoC) builder and verification system and method of the present invention assists a designer to design a System on Chip (SoC) in a convenient manner and facilitates incorporation of building block circuits that have been previously verified and tested in silicon. The SoC builder and verification system and method minimizes the amount of data a user has to enter manually to adequately describe features of the circuit being designed or verified. The present invention system and method automatically provides a chip level description, a test bench, clock descriptions, test logic descriptions, simulation models, and simulation environments.

An aspect of the present disclosure relates to a method for generating a System on Chip (SoC) from a floor plan having one or more integration descriptions. The method includes the steps of generating one or more connections between the integration descriptions of the floor plan based at least on a traffic specification, and conducting a design check process on the floor plan. If the design check process on the floor plan is indicative of passing the design check process, then the method generates the SoC according to the one or more connections generated between the integration descriptions. If the design check process on the floor plan is indicative of not passing the design check process, then the method generates a report indicative of not passing.

In an aspect, the integration descriptions include information derived from the hardware IP to construct at least a NoC for integration into at least one SoC. In another aspect, the at least one integration description is selected from said one or more integration descriptions of the hardware IP based at least on an input received from one or more users. In an aspect, the input is in a form of a file selected from any or combination of an XML file, an IP XACT file, a verilog file, a meta-data file or a file in a prescribed or pre-defined format.

In an aspect, the report includes any or combination of at least an error, a warning, and information associated with the design check process for not passing

In an aspect, the method is implemented in a computing device or a cloud server.

In an aspect, the method can generate connections associated with any or combination of a NoC, an crossbar, and direct connections.

In an aspect, the method can generate one or more connection bundles. In another aspect, the one or more connection bundles are generated by determining information associated with one or more ports associated with the one or more connections, performing protocol based template discovery to obtain one or more sets of pins associated with a particular protocol, and performing manual override on said sets of pins based at least on a bandwidth constraint, or a native connection, or a NoC based connection, or any combination thereof.

In an aspect, the method can generate one or more groups associated with one or more connection bundles.

In an aspect, the method can connect said one or more connection bundles based on pre-determined criteria. In another aspect, at least one connection selected from said one or more connection bundles include a label.

In an aspect, the method can generate one or more domain regions for the floor plan. In another aspect, the method can generate the SoC using one or more domain regions generated for the floor plan.

In an aspect, the method can generate any or combination of SoC connections, NoC IP, RTL hierarchy, XML file/IP XACT file, one or more collaterals such as lists, design rules check report, register descriptions, system address mapping, verification checkers, drivers for simulations, and performance reports.

In an aspect, the design check process can include a pre-defined set of checklist or rules associated with any or combination of a sanity of ports, clock compatibility, power compatibility, voltage compatibility, timing checks, internal port connections checks, a traffic check, a bandwidth check, and a protocol check.

In an aspect, the integration description comprises any or combination of performance goals/characteristics, pin information, port information, addressing/address information, clocking/clock information, protocol characteristics, buffer requirements, data width information, physical size information, tracing and debugging properties, domain crossing requirements, power information, and voltage information.

In an aspect, the method can display dependencies of the at least one integration description selected on the other integration descriptions selected from said one or more integration descriptions.

An aspect of the present disclosure relates to a system to generate a System on Chip (SoC) from a floor plan having one or more integration descriptions. The system includes a generation module to generate one or more connections between the integration descriptions of the floor plan based at least on a traffic specification, and to conduct a design check process on the floor plan. If the design check process on the floor plan is indicative of passing the design check process, then the method generates the SoC according to the one or more connections generated between the integration descriptions. If the design check process on the floor plan is indicative of not passing the design check process, then the method generates a report indicative of not passing.

In an aspect, the integration descriptions include information derived from the hardware IP to construct at least a NoC for integration into at least one SoC. In another aspect, the at least one integration description is selected from said one or more integration descriptions of the hardware IP based at least on an input received from one or more users. In an aspect, the input is in a form of a file selected from any or combination of an XML file, a verilog file, a meta-data file or a file in a prescribed or pre-defined format.

In an aspect, the report includes any or combination of at least an error, a warning, and information associated with the design check process for not passing

In an aspect, the system is a computing device or a cloud server.

In an aspect, the system can generate connections associated with any or combination of a NoC, an crossbar, and direct connections.

In an aspect, the system can generate one or more connection bundles. In another aspect, the one or more connection bundles are generated by determining information associated with one or more ports associated with the one or more connections, performing protocol based template discovery to obtain one or more sets of pins associated with a particular protocol, and performing manual override on said sets of pins based at least on a bandwidth constraint, or a native connection, or a NoC based connection, or any combination thereof.

In an aspect, the system can generate one or more groups associated with one or more connection bundles.

In an aspect, the system can connect said one or more connection bundles based on pre-determined criteria. In another aspect, at least one connection selected from said one or more connection bundles include a label.

In an aspect, the system can generate one or more domain regions for the floor plan. In another aspect, the method can generate the SoC using one or more domain regions generated for the floor plan.

In an aspect, the system can generate any or combination of SoC connections, NoC IP, RTL hierarchy, XML file/IP XACT file, one or more collaterals such as lists, design rules check report, register descriptions, system address mapping, verification checkers, drivers for simulations, and performance reports.

In an aspect, the system can display dependencies of the at least one integration description selected on the other integration descriptions selected from said one or more integration descriptions.

An aspect of the present disclosure relates to a non-transitory computer readable storage medium storing instructions for executing a process. The instructions include the steps of generating one or more connections between the integration descriptions of the floor plan based at least on a traffic specification, and conducting a design check process on the floor plan. If the design check process on the floor plan is indicative of passing the design check process, then the method generates the SoC according to the one or more connections generated between the integration descriptions. If the design check process on the floor plan is indicative of not passing the design check process, then the method generates a report indicative of not passing.

The foregoing and other objects, features and advantages of the example implementations will be apparent and the following more particular descriptions of example implementations as illustrated in the accompanying drawings wherein like reference numbers generally represent like parts of example implementations of the application.

BRIEF DESCRIPTION OF DRAWINGS

FIGS. 1A, 1B, 1C, and 1D illustrate examples of Bidirectional ring, 2D Mesh, 2D Torus, and 3D Mesh NoC Topologies.

FIG. 2A illustrates an example of XY routing in a related art two dimensional mesh.

FIG. 2B illustrates three different routes between a source and destination nodes.

FIG. 3A illustrates an example of a related art two layer NoC interconnect.

FIG. 3B illustrates the related art bridge logic between host and multiple NoC layers.

FIG. 4A-B illustrates a SoC connections and factors that determine a need of a NoC.

FIG. 5A illustrates a flow diagram for generating a System on Chip (SoC) from a floor plan having one or more integration descriptions.

FIGS. 5B-5D illustrates an input, design rule checks (DRCs), and an output generated, respectively, while generating a System on Chip (SoC) from a floor plan.

FIG. 6A illustrates a working of connection bundles.

FIG. 6B illustrates connection bundles formation.

FIG. 7A illustrates various types of SoC connections,

FIG. 7B illustrates example placement of various SoC connections.

FIG. 7C illustrates various example usage of domain regions generated for a particular floor plan for generation of SoC.

FIG. 8 illustrates an example flow diagram for generating a System on Chip (SoC) from a floor plan having one or more integration descriptions.

FIG. 9 illustrates an example computer system on which example embodiments may be implemented.

DETAILED DESCRIPTION

The following detailed description provides further details of the figures and example implementations of the present application. Reference numerals and descriptions of redundant elements between figures are omitted for clarity. Terms used throughout the description are provided as examples and are not intended to be limiting. For example, the use of the term “automatic” may involve fully automatic or semi-automatic implementations involving user or administrator control over certain aspects of the implementation, depending on the desired implementation of one of ordinary skill in the art practicing implementations of the present application.

Network-on-Chip (NoC) has emerged as a paradigm to interconnect a large number of components on the chip. NoC is a global shared communication infrastructure made up of several routing nodes interconnected with each other using point-to-point physical links. In example implementations, a NoC interconnect is generated from a specification by utilizing design tools. The specification can include constraints such as bandwidth/Quality of Service (QoS)/latency attributes that is to be met by the NoC, and can be in various software formats depending on the design tools utilized. Once the NoC is generated through the use of design tools on the specification to meet the specification requirements, the physical architecture can be implemented either by manufacturing a chip layout to facilitate the NoC or by generation of a register transfer level (RTL) for execution on a chip to emulate the generated NoC, depending on the desired implementation. Specifications may be in common power format (CPF), Unified Power Format (UPF), or others according to the desired specification. Specifications can be in the form of traffic specifications indicating the traffic, bandwidth requirements, latency requirements, interconnections, etc. depending on the desired implementation. Specifications can also be in the form of power specifications to define power domains, voltage domains, clock domains, and so on, depending on the desired implementation.

In an aspect, the integration descriptions include information derived from the hardware IP to construct at least a NoC for integration into at least one SoC. In another aspect, the at least one integration description is selected from said one or more integration descriptions of the hardware IP based at least on an input received from one or more users. In an aspect, the input is in a form of a file selected from any or combination of an XML file, a verilog file, a meta-data file or a file in a prescribed format.