Patent Application
20150317263
None.
Modern computers include processors and memory (e.g., random access memory (RAM)) that may operate at different voltage and/or frequency levels, or “performance points.” Power consumption of these devices is related to the performance point at which they operate; that is, a processor or memory device operating at a higher performance point consumes more power while a processor or memory device operating at a lower performance point consumes less power. Thus, power consumption may be reduced by allowing both the processor and memory device to operate at the lowest performance point permitted for a given computing load.
For a detailed description of exemplary embodiments of the invention, reference will now be made to the accompanying drawings in which:
a shows a block diagram of a computing system in accordance with various embodiments of the present disclosure;
b shows a block diagram of an alternate embodiment of a computing system in accordance with various embodiments of the present disclosure;
Certain terms are used throughout the following description and claims to refer to particular system components. As one skilled in the art will appreciate, companies may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not function. In the following discussion and in the claims, the terms “including” and “comprising” are used in an open-ended fashion, and thus should be interpreted to mean “including, but not limited to . . . .” Also, the term “couple” or “couples” is intended to mean either an indirect or direct electrical connection. Thus, if a first device couples to a second device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections.
The following discussion is directed to various embodiments of the invention. Although one or more of these embodiments may be preferred, the embodiments disclosed should not be interpreted, or otherwise used, as limiting the scope of the disclosure, including the claims. In addition, one skilled in the art will understand that the following description has broad application, and the discussion of any embodiment is meant only to be exemplary of that embodiment, and not intended to intimate that the scope of the disclosure, including the claims, is limited to that embodiment.
In computing systems, processors such as central processing units (CPUs) are configured to operate at multiple combinations of clock frequency and power supply voltage, or performance points. For example, in a time period where processing requirements on a CPU are high, the CPU may operate at a higher frequency-voltage combination, whereas in a time period where processing requirements on the CPU are minimal, the CPU may operate at a lower frequency-voltage combination, which conserves power. In this way, power consumption of the CPU is reduced when processing requirements on that CPU are lessened.
Similarly, memory such as random access memory (RAM) may be configured to operate at multiple performance points as well. The performance point of the memory is, in some cases, based on the requirements of the CPU. For example, when the CPU is operating at a higher performance point, the memory may also be caused to operate at a correspondingly higher performance point. However, in other cases, the performance point of the memory does not necessarily correspond to the performance point of the CPU. For example, where multiple CPUs are using memory, even where the CPUs are operating at a lower performance point, the memory may be caused to operate at a higher performance point to ensure adequate performance for all CPUs. Thus, in these cases, when the CPU is able to operate at a lower performance point, the memory does not necessarily transition to a lower performance point, and thus consumes more power than is necessary for a given CPU performance point. Further, in certain other cases, the CPU may be at a higher performance point but actually does not require memory to be at a correspondingly high performance point, for example because the CPU is accessing cache rather than memory. It is thus desirable to provide a system and method that allow and cause the memory to operate at a lower performance point when system processing requirements do not necessitate the memory operate at a higher performance point to provide acceptable system performance, in particular to decrease excess power consumption when not necessary.
Turning to
In accordance with various embodiments, monitoring hardware 110 is coupled to the interconnect 103 and detects a usage level of the interconnect 103. In some embodiments, the usage level may be expressed as a utilization percentage, while in other embodiments the usage level may be expressed as a bandwidth (e.g., MB/sec). The monitoring hardware 110 generates and transmits an indication of the detected usage level to control logic 112, which in
The control logic 112 causes the memory 104 to operate at a particular performance level based on the detected usage level or the indication of the detected usage level generated by the monitoring hardware 110. In accordance with various embodiments, if the detected usage level is above a first threshold, then the control logic 112 causes the memory 104 to operate at a first, higher performance point. However, if the detected usage level is below a second threshold, then the control logic 112 causes the memory 104 to operate at a second, lower performance point.
The particular values of the first and second threshold may be selected to optimize overall system 100 performance. For example, in some embodiments the first and second thresholds may be equal (e.g., 50% interconnect 103 utilization), such that if interconnect 103 utilization is greater than 50%, the control logic 112 causes the memory 104 to operate at the first performance point and if interconnect 103 utilization is less than 50%, the control logic 112 causes the memory 104 to operate at the second performance point. However, in other embodiments, the second threshold may be less than the first threshold (e.g., the first threshold is 70% interconnect 103 utilization and the second threshold is 30% interconnect 103 utilization), to allow for some hysteresis in the system 100. For example, if the control logic 112 causes the memory 104 to operate at the first performance point and the interconnect 103 utilization falls below 70%, but not below 30%, the control logic 112 continues to cause the memory 104 to operate at the first performance point.
The frequency of the clock signal generated by clock circuit 108 may be altered by modifying registers internal to the clock circuit 108, which in turn modifies the DPLL or an external divider on the output of the DPLL. The voltage supplied by the power supply 106 may be altered based on communications received through an interface, for example a serial peripheral interface (SPI) or an inter-integrated circuit (I2C) interface. The control logic 112 causes the clock circuit 108 to generate a clock signal for the memory 104 having a frequency value that is based on the detected usage level, for example by modifying registers of the clock circuit 108. Similarly, the control logic 112 also causes the power supply 106 to supply an operating voltage to the memory 104 having a voltage value that is based on the detected usage level, for example through communications via a SPI or I2C interface.
In some embodiments, the control logic 112 causes the memory 104 to operate at a higher or lower performance point based on the detected usage level being above the first threshold or below the second threshold, respectively, for at least a predetermined time. For example, if the memory 104 is operating at the lower performance point and the detected usage level rises above the first threshold, but for less than the predetermined threshold amount of time, and then falls below the first threshold, the control logic 112 would not cause the memory 104 to operate at the higher performance point. Conversely, if the memory 104 is operating at the lower performance point and the usage level rises above the first threshold and remains there for at least the predetermined threshold amount of time, the control logic 112 causes the memory 104 to operate at the higher performance point.
In certain embodiments, the various parameters described above with respect to the control logic 112 may be configurable, either at the time of system 100 design, by a user of the system 100, or both. For example, the various usage level thresholds may be configured, the predetermined threshold amounts of time may be configured, and other such parameters may be similarly configured. Additionally, although described generally with respect to a higher and lower performance point, one of ordinary skill in the art will appreciate that the present disclosure may be similarly applied to three or more performance points.
Turning now to
Control logic 112, which may be software executed by one of the CPUs 102 or hardware logic such as a microcontroller, implements this control of the performance point of the memory 104 by interfacing with a clock circuit 108 to vary the frequency of a clock signal provided to the memory 104 and by interfacing with a power supply 106 to vary the voltage level being supplied to the memory 104. In some cases the first and second thresholds are equal, while in others the second threshold is less than the first threshold to introduce an amount of hysteresis to the performance point control. Additionally, in certain embodiments, the method 200 includes causing the memory 104 to operate at the first performance point only when the detected usage is above the first threshold for at least a predetermined amount of time. Similarly, the method 200 may include causing the memory 104 to operate at the second performance point only when the detected usage is below the second threshold for at least a predetermined amount of time.
Turning now to
The monitoring engine 302 monitors transactions occurring on the interconnect 103 and, based on these transactions, detects a usage level of the interconnect 103. The monitoring engine transmits an indication of the usage level to the control engine 304. The control engine 304 causes the memory 104 to operate at a first, higher performance point based on the detected usage level being above a first threshold and causes the memory 104 to operate at a second, lower performance point based on the detected usage level being below a second threshold. As explained above, the second threshold is less than or equal to the first threshold.
Each module 406, 408 represents instructions that, when executed by the processing resource 404, implements an associated engine. For example, when the monitoring module 406 is executed by the processing resource 404, the above-described monitoring engine 302 functionality is implemented. Similarly, when the control module 408 is executed by the processing resource 404, the above-described control engine 304 functionality is implemented. The modules 406, 408 may also be implemented as an installation package or packages stored on the storage resource 402, which may be a CD/DVD or a server from which the installation package may be downloaded.
The above discussion is meant to be illustrative of the principles and various embodiments of the present invention. Numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the following claims be interpreted to embrace all such variations and modifications.
