Systems and Methods for Data Processing Control

Abstract

The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for performing data encoding.

Description

FIELD OF THE INVENTION

The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for performing data encoding.

BACKGROUND

Various data processing systems have been developed including storage systems, cellular telephone systems, and radio transmission systems. In such systems data is transferred from a sender to a receiver via some medium. For example, in a storage system, data is sent from a sender (i.e., a write function) to a receiver (i.e., a read function) via a storage medium. As information is stored and transmitted in the form of digital data, errors are introduced that, if not corrected, can corrupt the data and render the information unusable. In some cases, data decoding fails to properly decode.

Hence, for at least the aforementioned reasons, there exists a need in the art for advanced systems and methods for data decoding.

BRIEF SUMMARY

The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for performing data encoding.

Some embodiments of the present invention provide data processing systems that include a data encoder circuit. The data encoder circuit is operable to: receive N data sets; apply a data encoding algorithm to each of N−1 of the N data sets to yield respective N−1 encoded outputs using a predefined encoding value; calculate a syndrome value for each of the N−1 encoded outputs to yield N−1 syndrome values; aggregate the N−1 syndrome values to yield an aggregate syndrome value; and apply the data encoding algorithm to the Nth of the N data sets to yield an Nth encoded output using the aggregate syndrome value in place of the predefined encoding value.

This summary provides only a general outline of some embodiments of the invention. The phrases “in one embodiment,” “according to one embodiment,” in various embodiments“, in one or more embodiments”, “in particular embodiments” and the like generally mean the particular feature, structure, or characteristic following the phrase is included in at least one embodiment of the present invention, and may be included in more than one embodiment of the present invention. Importantly, such phases do not necessarily refer to the same embodiment. Many other embodiments of the invention will become more fully apparent from the following detailed description, the appended claims and the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

A further understanding of the various embodiments of the present invention may be realized by reference to the figures which are described in remaining portions of the specification. In the figures, like reference numerals are used throughout several figures to refer to similar components. In some instances, a sub-label consisting of a lower case letter is associated with a reference numeral to denote one of multiple similar components. When reference is made to a reference numeral without specification to an existing sub-label, it is intended to refer to all such multiple similar components.

FIG. 1 shows a data processing circuit including hybrid layer encoding and decoding circuitry in accordance with one or more embodiments of the present invention;

FIG. 2 a depicts a data processing system including hybrid layer encoding and decoding circuitry in accordance with various embodiments of the present invention;

FIG. 2 b depicts the encoding circuit of FIG. 2a;

FIG. 2 c graphically depicts an example hybrid layer encoding matrix comprising two component codewords that may be used in relation to one or more embodiments of the present invention;

FIG. 2 d graphically depicts a hybrid layer codeword resulting from application of the hybrid layer encoding matrix of FIG. 2c;

FIG. 3 shows a data processing circuit including a hybrid layer data decoding circuit in accordance with one or more embodiments of the present invention;

FIG. 4 is a flow diagram showing a method in accordance with some embodiments of the present invention for applying hybrid layer data decoding;

FIGS. 5 a-5b shows an encoding circuit that may be used in relation to the various embodiments of the present invention; and

FIG. 6 shows another data processing circuit including a hybrid layer data decoding circuit in accordance with other embodiments of the present invention; and

FIG. 7 is a flow diagram showing a method in accordance with some embodiments of the present invention for applying hybrid layer decoding to data encoded by the encoding circuit of FIG. 5.

DETAILED DESCRIPTION OF THE INVENTION

The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for performing data encoding.

Some embodiments of the present invention provide data processing systems that include a data encoder circuit. The data encoder circuit is operable to: receive N data sets; apply a data encoding algorithm to each of N−1 of the N data sets to yield respective N−1 encoded outputs using a predefined encoding value; calculate a syndrome value for each of the N−1 encoded outputs to yield N−1 syndrome values; aggregate the N−1 syndrome values to yield an aggregate syndrome value; and apply the data encoding algorithm to the Nth of the N data sets to yield an Nth encoded output using the aggregate syndrome value in place of the predefined encoding value. In particular cases, the data encoding algorithm is a low density parity check encoding algorithms.

In some instances of the aforementioned embodiments, the aggregate syndrome value plus a syndrome value corresponding to the Nth encoded output is equal to the predefined encoding value. In some cases, the predefined encoding value is ‘0’. In various cases, the encoding algorithm includes XORing an interim value of the Nth encoded output with the aggregate syndrome value as part of generating the Nth encoded output; and encoding algorithm includes XORing an interim value of a processing data set with the predefined encoding value during encoding of each of the N−1 of the N data sets.

In various instances of the aforementioned embodiments, the encoder circuit includes a selector circuit and an XOR circuit. The selector circuit is operable to provide the predefined encoding value during encoding of each of N−1 of the N data sets; and to provide the aggregate syndrome value during application of the data encoding algorithm to the Nth of the N data sets. The XOR circuit is operable to receive an interim value corresponding to one of the N data sets, and to XOR the interim value with the selection output. In some instances of the aforementioned embodiments, the difference between applying the data encoding algorithm to the N−1 of the N data sets and applying the data encoding algorithm to the Nth of the N data sets is a difference between the source of the selection output. In some cases, the selection output is the aggregate syndrome value during application of the second data encoding algorithm to the Nth of the N data sets, and wherein the selection input is a predefined value during application of the first data encoding algorithm to the N−1 of the N data sets. In particular instances of the aforementioned embodiments, the difference between applying the data encoding algorithm to the N−1 of the N data sets and applying the data encoding algorithm to the Nth of the N data sets is limited to use of the predefined encoding value during encoding of the N−1 of the N data sets and to use of the aggregate syndrome value during encoding of the Nth of the N data sets.

In some instances of the aforementioned embodiments, the data encoder circuit includes a concatenation circuit operable to combine the N−1 encoded outputs and the N-th encoded output to yield a transfer codeword. In some cases, the predefined encoding value is not included with the transfer codeword. In various cases, the data processing system is part of a data storage device including a storage medium, and the storage information derived from the transfer codeword is stored to the storage medium. In other cases, the data processing system is part of a communication device operable to transfer information derived from the transfer codeword via a transfer medium.

Other embodiments of the present invention provide methods for data processing that include: receiving N data sets; applying a data encoding algorithm to each of N−1 of the N data sets to yield respective N−1 encoded outputs using a predefined encoding value; calculating a syndrome value for each of the N−1 encoded outputs to yield N−1 syndrome values; aggregating the N−1 syndrome values to yield an aggregate syndrome value; and applying the data encoding algorithm to the Nth of the N data sets to yield an Nth encoded output using the aggregate syndrome value in place of the predefined encoding value. In some instances of the aforementioned embodiments, the aggregate syndrome value plus the Nth syndrome value is equal to the predefined encoding value. In particular cases, the predefined encoding value is ‘0’. In various instances of the aforementioned embodiments, the predefined encoding value is XORed with a first interim encoding value during application of the data encoding algorithm to the N−1 of the N data sets, and the aggregate syndrome value is XORed with a second interim encoding value during application of the data encoding algorithm to the Nth of the N data sets.

Some embodiments of the present invention provide data processing systems that include both a data detector circuit and a data decoding circuit. Processing a data set through both the data detector circuit and the data decoder circuit is referred to herein as a global iteration. In some cases, multiple passes through the data decoder circuit may be made during a single global iteration. Such passes through the data decoder circuit are referred to herein as a local iteration. When all of the errors in a data set have been corrected through application for the data detection algorithm applied by the data detector circuit and the data decoding algorithm applied by the data decoder circuit, the processing is said to have converged.

Various embodiments of the present invention provide data processing systems that include a data decoder circuit. The data decoder circuit is operable to: select a combination of a first portion of a received codeword and a second portion of the received codeword as a first codeword layer; apply a data decode algorithm to the first codeword layer to yield a first decoded output; where the first decoded output converged, set soft data in the first decoded output to a value indicating a high probability of being correctly decoded; select a combination of a third portion of a received codeword and the second portion of the received codeword as a second codeword layer; and apply the data decode algorithm to the second codeword layer guided by the first decoded output to yield a second decoded output. In some cases, the data decode algorithm is a low density parity check algorithm. In some cases, the data processing system is implemented as part of an integrated circuit.

In various instances of the aforementioned embodiments, the data processing system further includes a data detector circuit operable to apply a data detection algorithm to a data input to yield a detected output where the received codeword is derived from the detected output. The data detection algorithm may be, but is not limited to, a maximum a posteriori data detection algorithm, or a Viterbi data detection algorithm. In some cases, the data processing system is part of a data storage device including a storage medium, and the data input is derived from the storage medium. In other cases the data processing system is part of a communication device operable to receive information from a data transfer medium, and the data input is derived from the information.

In various instances of the aforementioned embodiments, the data decoder circuit is further operable to set soft data in the second decoded output to a value indicating a high probability of being correctly decoded when the second decoded output converged. In some such instances, the data decoder circuit is further operable to provide a data output including a combination of the first decoded output and the second decoded output when both the first decoded output and the second decoded output converged.

In particular instances of the aforementioned embodiments, the data processing system further includes a data encoder circuit operable to encode a user data set to yield the received codeword. The first portion of the received codeword corresponds to a first component codeword and the third portion of the received codeword corresponds to a second component codeword.

Turning to FIG. 1, a storage system 100 including a read channel circuit 110 that includes hybrid layer encoding and decoding circuitry in accordance with one or more embodiments of the present invention. Storage system 100 may be, for example, a hard disk drive. Storage system 100 also includes a preamplifier 170, an interface controller 120, a hard disk controller 166, a motor controller 168, a spindle motor 172, a disk platter 178, and a read/write head assembly 176. Interface controller 120 controls addressing and timing of data to/from disk platter 178. The data on disk platter 178 consists of groups of magnetic signals that may be detected by read/write head assembly 176 when the assembly is properly positioned over disk platter 178. In one embodiment, disk platter 178 includes magnetic signals recorded in accordance with a perpendicular recording scheme. For example, the magnetic signals may be recorded as either longitudinal or perpendicular recorded signals.

In a typical read operation, read/write head assembly 176 is accurately positioned by motor controller 168 over a desired data track on disk platter 178. The appropriate data track is defined by an address received via interface controller 120. Motor controller 168 both positions read/write head assembly 176 in relation to disk platter 178 and drives spindle motor 172 by moving read/write head assembly to the proper data track on disk platter 178 under the direction of hard disk controller 166. Spindle motor 172 spins disk platter 178 at a determined spin rate (RPMs). Once read/write head assembly 176 is positioned adjacent the proper data track, magnetic signals representing data on disk platter 178 are sensed by read/write head assembly 176 as disk platter 178 is rotated by spindle motor 172. The sensed magnetic signals are provided as a continuous, minute analog signal representative of the magnetic data on disk platter 178. This minute analog signal is transferred from read/write head assembly 176 to read channel circuit 110 via preamplifier 170. Preamplifier 170 is operable to amplify the minute analog signals accessed from disk platter 178. In turn, read channel circuit 110 decodes and digitizes the received analog signal to recreate the information originally written to disk platter 178. The read data is provided as read data 103. A write operation is substantially the opposite of the preceding read operation with write data 101 being provided to read channel circuit 110. This data is then encoded and written to disk platter 178.

Writing data to disk platter 178 includes applying hybrid layer encoding to generate a hybrid layer codeword that is transferred to disk platter 178 via read/write head assembly. Such hybrid layer encoding may be done, for example, similar to that discussed below in relation to FIGS. 2a-2d, and may be done using an encoding circuit similar to that discussed in FIG. 5 below. The hybrid layer encoding applies encoding that is used in relation to individual component codewords, and additional encoding that enhances the performance of encoded component codewords. This additional encoding is referred to generally herein as a hybrid encoding portion and is included with the component codewords to make up the hybrid layer codeword.

Reading data from disk platter may include applying both data detection and data decoding algorithms to the hybrid layer codeword to obtain the original user data. During the data decoding algorithm, hybrid layers including an individual component codeword and the hybrid portion are decoded over a number of local iterations. Where the individual component codeword converges, the soft data corresponding to the individual component codeword and the hybrid portion is set to a maximum value. In this way, the values in the hybrid portion are effectively frozen while the other hybrid layer formed of another individual component codeword and the hybrid portion is decoded. In this way, the added hybrid portion not only provides additional encoding that may be used to aid the data processing of a given component codeword, convergence of any of the component codewords will yield a known hybrid portion that further enhances the ability to correctly decode other component codewords within the hybrid layer codeword. Such decoding may be done using a circuit similar to that discussed below in relation to FIG. 3 or FIG. 6, and/or a process similar to that discussed below in relation to FIG. 4 or FIG. 7. discussed below in relation to FIG. 3 or FIG. 6, and/or a process similar to that discussed below in relation to FIG. 4 or FIG. 7.

It should be noted that storage system 100 may be integrated into a larger storage system such as, for example, a RAID (redundant array of inexpensive disks or redundant array of independent disks) based storage system. Such a RAID storage system increases stability and reliability through redundancy, combining multiple disks as a logical unit. Data may be spread across a number of disks included in the RAID storage system according to a variety of algorithms and accessed by an operating system as if it were a single disk. For example, data may be mirrored to multiple disks in the RAID storage system, or may be sliced and distributed across multiple disks in a number of techniques. If a small number of disks in the RAID storage system fail or become unavailable, error correction techniques may be used to recreate the missing data based on the remaining portions of the data from the other disks in the RAID storage system. The disks in the RAID storage system may be, but are not limited to, individual storage systems such as storage system 100, and may be located in close proximity to each other or distributed more widely for increased security. In a write operation, write data is provided to a controller, which stores the write data across the disks, for example by mirroring or by striping the write data. In a read operation, the controller retrieves the data from the disks. The controller then yields the resulting read data as if the RAID storage system were a single disk.

A data decoder circuit used in relation to read channel circuit 110 may be, but is not limited to, a low density parity check (LDPC) decoder circuit as are known in the art. Such low density parity check technology is applicable to transmission of information over virtually any channel or storage of information on virtually any media. Transmission applications include, but are not limited to, optical fiber, radio frequency channels, wired or wireless local area networks, digital subscriber line technologies, wireless cellular, Ethernet over any medium such as copper or optical fiber, cable channels such as cable television, and Earth-satellite communications. Storage applications include, but are not limited to, hard disk drives, compact disks, digital video disks, magnetic tapes and memory devices such as DRAM, NAND flash, NOR flash, other non-volatile memories and solid state drives.

In addition, it should be noted that storage system 100 may be modified to include solid state memory that is used to store data in addition to the storage offered by disk platter 178. This solid state memory may be used in parallel to disk platter 178 to provide additional storage. In such a case, the solid state memory receives and provides information directly to read channel circuit 110. Alternatively, the solid state memory may be used as a cache where it offers faster access time than that offered by disk platted 178. In such a case, the solid state memory may be disposed between interface controller 120 and read channel circuit 110 where it operates as a pass through to disk platter 178 when requested data is not available in the solid state memory or when the solid state memory does not have sufficient storage to hold a newly written data set. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of storage systems including both disk platter 178 and a solid state memory.

Turning to FIG. 2a, a data processing system 200 is shown that includes hybrid layer encoding and decoding circuitry in accordance with various embodiments of the present invention. Data processing system 200 includes a hybrid layer encoding circuit 220 that generates a hybrid layer codeword. The encoding is applied to an original data input 205 that includes multiple segments of data that are encoded together such that the resulting hybrid layer codeword includes two or more component codewords and a corresponding hybrid encoding portion that is the same across multiple component codewords. Original data input 205 may be any set of input data. For example, where data processing system 200 is a hard disk drive, original input 205 may be a data set that is destined for storage on a storage medium. In such cases, a medium 240 of data processing system 200 is a storage medium. As another example, where data processing system 200 is a communication system, original input 205 may be a data set that is destined to be transferred to a receiver via a transfer medium. Such transfer mediums may be, but are not limited to, wired or wireless transfer mediums. In such cases, a medium 240 of data processing system 200 is a transfer medium.

Turning to FIG. 2b, a graphical depiction 290 of hybrid layer encoding circuit 220 is shown. As shown, original data input 205 is provided to an encoder circuit 212 where it is multiplied by a hybrid layer encoding matrix 232 to yield a hybrid layer codeword 234. FIG. 2c graphically depicts an example hybrid layer encoding matrix 232 comprising two component codewords that may be used in relation to one or more embodiments of the present invention. As shown hybrid layer encoding matrix 232 includes H-matrices 295 that when multiplied by a portion of original data input 205 yield a respective component codeword (i.e., a component codeword corresponding to H-matrix 295a and 0-fill matrix 297a of rows 272, and a component codeword corresponding to H-matrix 295b and 0-fill matrix 297b of rows 274), and hybrid matrices 296 that when multiplied by the portions of original data 205 yield respective hybrid portions (i.e., a hybrid portion corresponding to hybrid-matrix 296a and a hybrid portion corresponding to hybrid matrix 296b, with the combination of the hybrid portions from rows 276 yielding a hybrid encoding portion). As the name suggests, the 0-file matrices are matrices of all zeros. It should be noted that while FIG. 2c shows a hybrid layer encoding matrix for generating a hybrid layer codeword having two component codewords, other embodiments of the present invention may utilize an encoding matrix capable of generating a hybrid layer codeword having three or more component codewords. In one particular embodiment of the present invention, the portions of original data input 205 corresponding to each component codeword is 2K bits. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize other portion sizes that may be used in relation to different embodiments of the present invention.

FIG. 2 d graphically depicts a hybrid layer codeword 280 resulting from application of hybrid layer encoding matrix 232 to original data input 205. As shown, hybrid layer codeword 280 includes: a first component codeword (i.e., component codeword A) corresponding to row 272 of hybrid encoding matrix 232, a second component codeword (i.e., component codeword B) corresponding to row 274 of hybrid encoding matrix 232, and a hybrid encoding portion corresponding to row 276 of hybrid encoding matrix 232.

Returning to FIG. 2a, encoding circuit 220 provides the resulting hybrid layer codeword to a transmission circuit 230. Transmission circuit 230 may be any circuit known in the art that is capable of transferring the received codeword 225 via medium 240. Thus, for example, where data processing circuit 200 is part of a hard disk drive, transmission circuit 230 may include a read/write head assembly that converts an electrical signal into a series of magnetic signals appropriate for writing to a storage medium. Alternatively, where data processing circuit 200 is part of a wireless communication system, transmission circuit 230 may include a wireless transmitter that converts an electrical signal into a radio frequency signal appropriate for transmission via a wireless transmission medium. Transmission circuit 230 provides a transmission output to medium 240. Medium 240 provides a transmitted input that is the transmission output augmented with one or more errors introduced by the transference across medium 240.

Data processing circuit 200 includes a pre-processing circuit 250 that applies one or more analog functions to the transmitted input. Such analog functions may include, but are not limited to, amplification and filtering. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of pre-processing circuitry that may be used in relation to different embodiments of the present invention. Pre-processing circuit 250 provides a pre-processed output to a hybrid layer based decoding circuit 260. Hybrid layer based decoding circuit 260 applies a decoding algorithm to hybrid layers of the received hybrid layer codeword sequentially. When a component codeword of a given hybrid layer converges, the soft data associated with that the hybrid layer is set to a maximum value. In this way, the values in the hybrid encoding portion of hybrid layer codeword are effectively frozen (in addition to the values of the converged component codeword) while another hybrid layer formed of another individual component codeword and the hybrid portion is decoded. As such, the added hybrid portion not only provides additional encoding that may be used to aid the data processing of a given component codeword, convergence of any of the component codewords will yield a known hybrid portion that further enhances the ability to correctly decode other component codewords within the hybrid layer codeword. The result of the decoding process is provided as a data output 265.

Turning to FIG. 3, a data processing circuit 300 is shown that includes a hybrid layer data decoding circuit 370 in accordance with one or more embodiments of the present invention. Data processing circuit 300 includes an analog front end circuit 310 that receives an analog signal 305. Analog front end circuit 310 processes analog signal 305 and provides a processed analog signal 312 to an analog to digital converter circuit 314. Analog front end circuit 310 may include, but is not limited to, an analog filter and an amplifier circuit as are known in the art. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of circuitry that may be included as part of analog front end circuit 310. Analog signal 305 represents hybrid layer codewords that may be similar to that discussed above in relation to FIG. 2d where a number of component codewords are combined with hybrid encoding portions. In some cases, where data processing circuit 300 is implemented as part of a storage device, analog signal 305 is derived from a read/write head assembly (not shown) that is disposed in relation to a storage medium (not shown). In other cases, analog signal 305 is derived from a receiver circuit (not shown) that is operable to receive a signal from a transmission medium (not shown). The transmission medium may be wired or wireless. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of source from which analog input 305 may be derived.

Analog to digital converter circuit 314 converts processed analog signal 312 into a corresponding series of digital samples 316. Analog to digital converter circuit 314 may be any circuit known in the art that is capable of producing digital samples corresponding to an analog input signal. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of analog to digital converter circuits that may be used in relation to different embodiments of the present invention. Digital samples 316 are provided to an equalizer circuit 320. Equalizer circuit 320 applies an equalization algorithm to digital samples 316 to yield an equalized output 325. In some embodiments of the present invention, equalizer circuit 320 is a digital finite impulse response filter (DFIR) circuit as are known in the art. It may be possible that equalized output 325 may be received directly from a storage device in, for example, a solid state storage system. In such cases, analog front end circuit 310, analog to digital converter circuit 314 and equalizer circuit 320 may be eliminated where the data is received as a digital data input. Equalized output 325 is stored to an input buffer 353 that includes sufficient memory to maintain one or more codewords until processing of that codeword is completed through a data detector circuit 330 and a hybrid layer data decoding circuit 370 including, where warranted, multiple global iterations (passes through both data detector circuit 330 and hybrid layer data decoding circuit 370) and/or local iterations (passes through hybrid layer data decoding circuit 370 during a given global iteration). An output 357 is provided to data detector circuit 330.

Data detector circuit 330 may be a single data detector circuit or may be two or more data detector circuits operating in parallel on different hybrid layer codewords. Whether it is a single data detector circuit or a number of data detector circuits operating in parallel, data detector circuit 330 is operable to apply a data detection algorithm to a received codeword or data set. In some embodiments of the present invention, data detector circuit 330 is a Viterbi algorithm data detector circuit as are known in the art. In other embodiments of the present invention, data detector circuit 330 is a maximum a posteriori data detector circuit as are known in the art. Of note, the general phrases “Viterbi data detection algorithm” or “Viterbi algorithm data detector circuit” are used in their broadest sense to mean any Viterbi detection algorithm or Viterbi algorithm detector circuit or variations thereof including, but not limited to, bi-direction Viterbi detection algorithm or bi-direction Viterbi algorithm detector circuit. Also, the general phrases “maximum a posteriori data detection algorithm” or “maximum a posteriori data detector circuit” are used in their broadest sense to mean any maximum a posteriori detection algorithm or detector circuit or variations thereof including, but not limited to, simplified maximum a posteriori data detection algorithm and a max-log maximum a posteriori data detection algorithm, or corresponding detector circuits. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of data detector circuits that may be used in relation to different embodiments of the present invention. In some cases, one data detector circuit included in data detector circuit 330 is used to apply the data detection algorithm to the received codeword for a first global iteration applied to the received codeword, and another data detector circuit included in data detector circuit 330 is operable apply the data detection algorithm to the received codeword guided by a decoded output accessed from a central memory circuit 350 on subsequent global iterations.

Upon completion of application of the data detection algorithm to the received hybrid layer codeword on the first global iteration, data detector circuit 330 provides a detector output 333. Each instance of detector output 333 corresponds to a respective one of the hybrid layer received as analog input 305.

Detector output 333 includes soft data. As used herein, the phrase “soft data” is used in its broadest sense to mean reliability data with each instance of the reliability data indicating a likelihood that a corresponding bit position or group of bit positions has been correctly detected. In some embodiments of the present invention, the soft data or reliability data is log likelihood ratio data as is known in the art. In cases where a higher value of soft data indicates a greater likelihood that a corresponding bit or symbol of the hybrid layer codeword has been correctly determined, setting the soft data to a maximum value makes it very unlikely that the corresponding bit will be modified during subsequent decoding or detection processes. As such, the bit or symbol is effectively frozen. Similarly, in cases where a lower value of soft data indicates a greater likelihood that a corresponding bit or symbol of the hybrid layer codeword has been correctly determined, setting the soft data to a minimum value makes it very unlikely that the corresponding bit will be modified during subsequent decoding or detection processes. Detected output 333 is provided to a local interleaver circuit 342. Local interleaver circuit 342 is operable to shuffle sub-portions (i.e., local chunks) of the data set included as detected output and provides an interleaved codeword 346 that is stored to central memory circuit 350. Interleaver circuit 342 may be any circuit known in the art that is capable of shuffling data sets to yield a re-arranged data set. Interleaved codeword 346 is stored to central memory circuit 350.

Once hybrid layer data decoding circuit 370 is available, a previously stored interleaved codeword 346 is accessed from central memory circuit 350 as a stored codeword 386 and globally interleaved by a global interleaver/de-interleaver circuit 384. Global interleaver/De-interleaver circuit 384 may be any circuit known in the art that is capable of globally rearranging codewords. Global interleaver/De-interleaver circuit 384 provides a decoder input 352 into hybrid layer data decoding circuit 370. Decoder input 352 may be a hybrid layer codeword similar to that discussed above in relation to FIG. 2d where a number of component codewords are combined with hybrid encoding portions. In some embodiments of the present invention, the data decode algorithm is a layered low density parity check algorithm as are known in the art. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize other decode algorithms that may be used in relation to different embodiments of the present invention. Hybrid layer data decoding circuit 370 applies to data decode algorithm to decoder input 352 to yield a decoded output 371.

In operation, hybrid layer data decoding circuit 370 selects a first component codeword and the hybrid encoding portion as a first decoding layer. Using the example of FIG. 2c, hybrid layer data decoding circuit 370 selects, for example, the data in hybrid layer codeword corresponding to rows 272 and rows 276 is selected. As an example, rows 272 may include eight rows, and rows 276 may include two rows. Hybrid layer data decoding circuit 370 then applies the data decoding algorithm to the first decoding layer to yield a decoded output. This process of applying the data decode algorithm to the first decoding layer is repeated for a number of local iterations until either the component codeword associated with the first decoding layer converges, or until a maximum number of local iterations is exceeded. Where the first decoding layer converges, the soft data associated with the first decoding layer is set to values representing the highest likelihood that data associated with the first decoding layer is correctly determined. In this way, the values in the hybrid encoding portion are effectively frozen while another decoding layer formed of another individual component codeword and the hybrid encoding portion is decoded. This provides additional guidance to the decoding process applied to subsequent layers. Alternatively, where the first decoding layer fails to converge before the maximum number of local iterations has been exceeded, the soft data is left as it existed after the last local iteration. At this point, decoding of the first decoding layer is complete.

With the decoding of the first decoding layer completed, hybrid layer data decoding circuit 370 selects a second component codeword and the hybrid encoding portion as a second decoding layer. Using the example of FIG. 2c, hybrid layer data decoding circuit 370 selects, for example, the data in hybrid layer codeword corresponding to rows 274 and rows 276 is selected. As an example, rows 274 may include eight rows, and rows 276 may include two rows. Hybrid layer data decoding circuit 370 then applies the data decoding algorithm to the second decoding layer to yield a decoded output. This process of applying the data decode algorithm to the second decoding layer is repeated for a number of local iterations until either the component codeword associated with the second decoding layer converges, or until a maximum number of local iterations is exceeded. Where the second decoding layer converges, the soft data associated with the second decoding layer is set to values representing the highest likelihood that data associated with the second decoding layer is correctly determined. Again, in this way, the values in the hybrid encoding portion are effectively frozen while another decoding layer formed of another individual component codeword and the hybrid encoding portion is decoded. This provides additional guidance to the decoding process applied to subsequent layers.

This process of applying the data decode algorithm sequentially to decoding layers continues until all of hybrid codewords corresponding to individual component codewords are decoded. Thus, while the example in FIG. 2c implies a hybrid layer codeword comprised of two component codewords, data processing circuit 300 may operate on hybrid layer codewords exhibiting three or more component codewords. Where less than all of the individual component codewords converge, decoding of the hybrid layer codeword fails to converge. In such a case, the resulting decoded output is provided as a decoded output 354 back to central memory circuit 350 where it is stored awaiting another global iteration through a data detector circuit included in data detector circuit 330. Prior to storage of decoded output 354 to central memory circuit 350, decoded output 354 is globally de-interleaved to yield a globally de-interleaved output 388 that is stored to central memory circuit 350. The global de-interleaving reverses the global interleaving earlier applied to stored codeword 386 to yield decoder input 352. When a data detector circuit included in data detector circuit 330 becomes available, a previously stored de-interleaved output 388 accessed from central memory circuit 350 and locally de-interleaved by a de-interleaver circuit 344. De-interleaver circuit 344 re-arranges decoder output 348 to reverse the shuffling originally performed by interleaver circuit 342. A resulting de-interleaved output 397 is provided to data detector circuit 330 where it is used to guide subsequent detection of a corresponding data set previously received as equalized output 325.

Alternatively, where all of the individual component codewords converge, decoding of the hybrid layer codeword to converges (i.e., yields the originally written data set), the resulting decoded output is provided as an output codeword 372 to a de-interleaver circuit 380. De-interleaver circuit 380 rearranges the data to reverse both the global and local interleaving applied to the data to yield a de-interleaved output 382. De-interleaved output 382 is provided to a hard decision output circuit 390. Hard decision output circuit 390 is operable to re-order data sets that may complete out of order back into their original order. The originally ordered data sets are then provided as a hard decision output 392.

Turning to FIG. 4, a flow diagram 400 showing a method in accordance with some embodiments of the present invention for applying hybrid layer data decoding. Following flow diagram 400, a data set is received from the central memory (block 405). The data set is a hybrid layer codeword comprising two or more component codewords. As an example, such a hybrid layer codeword may be similar to that discussed above in relation to FIG. 2d. It should be noted that the process of flow diagram 400 is discussed in relation to a hybrid layer codeword that has two component codewords, but it should be noted that the process may be expanded to handle hybrid layer codewords comprising three or more component codewords.

A combination of a first component codeword and a hybrid encoding portion of the hybrid layer codeword is selected as a first decoding layer (block 410). A data decoding algorithm is applied to the first decoding layer to yield a decoding output (block 415). Where it is the second or later local iteration, a prior decoding output is used to guide application of the data decoding algorithm. It is determined whether application of the decoding algorithm resulted in convergence of the first decoding layer (bock 420). Where the first decoding layer converged (block 420), the soft data corresponding to the first decoding layer is set equal to a maximum value (i.e., a value indicating the highest likelihood that the data was properly decoded) (block 425). This effectively freezes the first decoding layer.

Alternatively, where the first decoding layer failed to converge (block 420), it is determined whether another local iteration through the data decoder circuit is allowed (block 430). As an example, in some cases each decoding layer is allowed ten (10) local iterations through the data decoder circuit. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize other numbers of local iterations that may be allowed in accordance with different embodiments of the present invention. Where more local iterations are allowed (block 430), the processes of blocks 415-430 are reapplied to the first decoding layer guided by the previous decoding output.

Where either the first decoding layer converged (block 420) or the maximum number of local iterations have been surpassed (block 430), a combination of a second component codeword and the hybrid encoding portion of the hybrid layer codeword is selected as a second decoding layer (block 435). The data decoding algorithm is applied to the second decoding layer to yield a decoding output (block 440). The decoding output resulting from applying the data decoding algorithm to the first decoding layer is used to guide the first local iteration of the second decoding layer. This includes defacto frozen values for the hybrid encoding portion where the first decoding layer converged. Such frozen values improve the accuracy of the decoding algorithm applied to the second decoding layer. Where it is the second or later local iteration of the second decoding layer, a prior decoding output corresponding to the second decoding layer is used to guide application of the data decoding algorithm. It is determined whether application of the decoding algorithm resulted in convergence of the second decoding layer (bock 445). Where the second decoding layer converged (block 445), it is determined whether the first decoding layer converged (block 460). Where the first decoding layer converged (block 460), all of the decoding layers in the hybrid layer codeword have converged, and thus the converged output is provided to a requestor (block 465).

Alternatively, where the first decoding layer failed to converge (block 460), less than all of the decoding layers of the hybrid layer codeword have converged, and thus additional processing may be desired. In such a case, the soft data corresponding to the second decoding layer is set equal to a maximum value (i.e., a value indicating the highest likelihood that the data was properly decoded) (block 470). This effectively freezes the second decoding layer. At this point, the resulting decoded output is sent back to the central memory to await a subsequent global iteration (block 475).

Where the second decoding layer failed to converge (block 445), it is determined whether another local iteration through the data decoder circuit is allowed (block 450). As an example, in some cases each decoding layer is allowed ten (10) local iterations through the data decoder circuit. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize other numbers of local iterations that may be allowed in accordance with different embodiments of the present invention. Where more local iterations are allowed (block 450), the processes of blocks 440-470 are reapplied to the second decoding layer guided by the previous decoding output. Where another local iteration is not allowed (block 450), the resulting decoded output is sent back to the central memory to await a subsequent global iteration (block 475).

Turning to FIG. 5a, an encoding circuit 500 is shown in accordance with various embodiments of the present invention. In some cases, encoding circuit 500 may be used in place of encoding circuit 220 of FIG. 2. Encoding circuit 500 utilizes an encoding matrix 599 as shown in FIG. 5b. Encoding circuit 500 includes a sparse matrix multiplication circuit 505 that multiplies a user data input 502 (u) by a portion of an encoding matrix, Hu₁ matrix 507 (Hu₁), to yield a product 509 in accordance with the following equation:

Product 509=u×Hu₁

In addition, encoding circuit 500 includes a sparse matrix multiplication circuit 540 that multiplies a user data input 502 (u) by a portion of an encoding matrix, Hu₂ matrix 542 (Hu₂), to yield a product 544 in accordance with the following equation:

Product 544=u×Hu₂.

Another sparse matrix multiplication circuit 510 multiplies product 509 by an inverse portion of the encoding matrix, Hp₂₁ matrix 512 (Hp₂₁), to yield a product 514 in accordance with the following equation:

Product 514=[u×Hu₁]×Hp₂₁.

Product 544 is XORed with product 514 by a vector based XOR circuit 515 to yield a product 517 in accordance with the following equation:

Product 517=([u×Hu₁]×Hp₂₁){circle around (×)}(u×Hu₂).

Product 517 is then XORed by a selected input 579 by a vector based XOR circuit 520 to yield a product 5524 in accordance with the following equation:

Product 524=[([u×Hu₁]×Hp₂₁){circle around (×)}(u×Hu₂)]{circle around (×)}Selected Input 579.

Selected input 579 is selected to be a ‘0’ for the first N−1 sectors included in a codeword set using corresponding syndrome based hybrid layers similar to those shown in FIG. 5b, and is selected as an accumulated syndrome value 574 for the Nth sector included in the codeword set. Selection is done by a selector circuit 575 under control of an encoding controller circuit 580. In particular, encoding controller circuit 580 asserts a control signal 582 to select the ‘0’ value during encoding of the first N−1 sectors, and asserts control signal 582 to select accumulated syndrome value 574 during encoding of the Nth sector. As such, encoding controller circuit 580 includes a counter that tracks the number of sectors processed.

Product 524 is provided to a dense matrix multiplication circuit 525 where it is multiplied by an inverse portion of the encoding matrix, inverse Hp₂₂ matrix 527 (Inverse Hp₂₂), to yield a product 529 in accordance with the following equation:

Product 529=Product 524×Inverse Hp₂₂

Product 529 is a parity output (P2) included as part of the transmitted codeword. P2 may be represented by the following equation:

P2=Inverse Hp₂₂×(S_L−Hu₂×u),

where S_L, is selected input 579.

Product 529 is provided to another sparse matrix multiplication circuit 525 where it is multiplied by an inverse portion of the encoding matrix, inverse Hp₂₂ matrix 527 (Inverse Hp₂₂), to yield a product 534 in accordance with the following equation:

Product 534=Product 529×Inverse Hp₂₂.

Product 534 is XORed with product 509 by a vector based XOR circuit 550 to yield a product 554 in accordance with the following equation:

Product 554=(Product 529×Inverse Hp₂₂){circle around (×)}(u×Hu₁).

Product 554 is provided to another sparse matrix multiplication circuit 555 where it is multiplied by an inverse portion of the encoding matrix, inverse Hp₁₁ matrix 557 (Inverse Hp₁₁), to yield a product 559 in accordance with the following equation:

Product 559=[(Product 529×Inverse Hp₂₂){circle around (×)}(u×Hu₁)]×Inverse Hp₁₁.

Product 559 is a parity output (P1) included as part of the transmitted codeword. P1 may be represented by the following equation:

P1=Inverse Hp₁₁×(Hp₁₂×P2+Hu₁×u).

As each sector is encoded, a syndrome (Si) of the currently processing sector is calculated by a syndrome calculator and accumulator circuit 570 in accordance with the following equation:

$\mathrm{Si}=\left[\begin{array}{ccc}{\mathrm{Hp}}_{22}& \left({\mathrm{Hp}}_{21}\times {\mathrm{Hu}}_1\right)& {\mathrm{Hu}}_2\end{array}\right]\times \left[\begin{array}{c}P2\\ u\end{array}\right].$

In addition, the calculated syndrome is accumulated with the syndromes calculated for each of the N−1 sectors to yield accumulated syndrome value 574 in accordance with the following equation:

$\mathrm{Accumulated}\mathrm{Syndrome}\mathrm{Value}574=\sum _{i=1}^{N-1}S_i.$

By using accumulated syndrome value 574 in place of a ‘0’ value for encoding the Nth sector, the overall syndrome from the N sectors will be a ‘0’ (i.e., XORing to equal values results in a zero). Where the overall syndrome value is always ‘0’ (or any other predefined encoding value), it does not need to be transmitted, but can be assumed by a data decoding circuit receiving the encoded data. As such, a concatenation circuit (not shown) that assembles all of the encoded codewords into one set of transfer information does not include the predefined encoding value (in this case ‘0’). Said another way, the resulting codeword is similar to that discussed above in relation to FIG. 2d, except hybrid encoding portion 289 is not included, but is only implied.

Turning to FIG. 6, another data processing circuit 600 is shown that includes a hybrid layer data decoding circuit 670 in accordance with other embodiments of the present invention. Data processing circuit 600 includes an analog front end circuit 610 that receives an analog signal 605. Analog front end circuit 610 processes analog signal 605 and provides a processed analog signal 612 to an analog to digital converter circuit 614. Analog front end circuit 610 may include, but is not limited to, an analog filter and an amplifier circuit as are known in the art. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of circuitry that may be included as part of analog front end circuit 610. Analog signal 605 represents hybrid layer codewords that may be similar to that discussed above in relation to FIG. 2d where a number of component codewords are combined with hybrid encoding portions. In a case such as that described above in relation to FIG. 5, hybrid encoding portion 289 is implied as is corresponds to a predefined encoding value. In some cases, where data processing circuit 600 is implemented as part of a storage device, analog signal 605 is derived from a read/write head assembly (not shown) that is disposed in relation to a storage medium (not shown). In other cases, analog signal 605 is derived from a receiver circuit (not shown) that is operable to receive a signal from a transmission medium (not shown). The transmission medium may be wired or wireless. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of source from which analog input 605 may be derived.

Analog to digital converter circuit 614 converts processed analog signal 612 into a corresponding series of digital samples 616. Analog to digital converter circuit 614 may be any circuit known in the art that is capable of producing digital samples corresponding to an analog input signal. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of analog to digital converter circuits that may be used in relation to different embodiments of the present invention. Digital samples 616 are provided to an equalizer circuit 620. Equalizer circuit 620 applies an equalization algorithm to digital samples 616 to yield an equalized output 625. In some embodiments of the present invention, equalizer circuit 620 is a digital finite impulse response filter (DFIR) circuit as are known in the art. It may be possible that equalized output 625 may be received directly from a storage device in, for example, a solid state storage system. In such cases, analog front end circuit 610, analog to digital converter circuit 614 and equalizer circuit 620 may be eliminated where the data is received as a digital data input.

Equalized output 625 represents multiple sectors of data that were interleaved such that portions of each of the individual sector is intermixed with portions of other individual sectors. To reverse this interleaving, equalized output 625 is provided to a spread sector control and buffer circuit 628 that rearranges the received data such that the portions of individual sectors are aligned such that each of the individual sectors of data are arranged contiguously to yield de-interleaved multiple sector data block 629. Portions of de-interleaved multiple sector data block 629 is provided on a sector by sector basis to an input buffer 653 as space becomes available in input buffer 653.

Input buffer 653 includes sufficient memory to maintain one or more codewords until processing of that codeword is completed through a data detector circuit 630 and a hybrid layer data decoding circuit 670 including, where warranted, multiple global iterations (passes through both data detector circuit 630 and hybrid layer data decoding circuit 670) and/or local iterations (passes through hybrid layer data decoding circuit 670 during a given global iteration). An output 657 is provided to data detector circuit 630.

Data detector circuit 630 may be a single data detector circuit or may be two or more data detector circuits operating in parallel on different hybrid layer codewords. Whether it is a single data detector circuit or a number of data detector circuits operating in parallel, data detector circuit 630 is operable to apply a data detection algorithm to a received codeword or data set. In some embodiments of the present invention, data detector circuit 630 is a Viterbi algorithm data detector circuit as are known in the art. In other embodiments of the present invention, data detector circuit 630 is a maximum a posteriori data detector circuit as are known in the art. Of note, the general phrases “Viterbi data detection algorithm” or “Viterbi algorithm data detector circuit” are used in their broadest sense to mean any Viterbi detection algorithm or Viterbi algorithm detector circuit or variations thereof including, but not limited to, bi-direction Viterbi detection algorithm or bi-direction Viterbi algorithm detector circuit. Also, the general phrases “maximum a posteriori data detection algorithm” or “maximum a posteriori data detector circuit” are used in their broadest sense to mean any maximum a posteriori detection algorithm or detector circuit or variations thereof including, but not limited to, simplified maximum a posteriori data detection algorithm and a max-log maximum a posteriori data detection algorithm, or corresponding detector circuits. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of data detector circuits that may be used in relation to different embodiments of the present invention. In some cases, one data detector circuit included in data detector circuit 630 is used to apply the data detection algorithm to the received codeword for a first global iteration applied to the received codeword, and another data detector circuit included in data detector circuit 630 is operable apply the data detection algorithm to the received codeword guided by a decoded output accessed from a central memory circuit 650 on subsequent global iterations.

Upon completion of application of the data detection algorithm to the received hybrid layer codeword on the first global iteration, data detector circuit 630 provides a detector output 633. Each instance of detector output 633 corresponds to a respective one of the hybrid layer received as analog input 605.

Detector output 633 includes soft data. As used herein, the phrase “soft data” is used in its broadest sense to mean reliability data with each instance of the reliability data indicating a likelihood that a corresponding bit position or group of bit positions has been correctly detected. In some embodiments of the present invention, the soft data or reliability data is log likelihood ratio data as is known in the art. In cases where a higher value of soft data indicates a greater likelihood that a corresponding bit or symbol of the hybrid layer codeword has been correctly determined, setting the soft data to a maximum value makes it very unlikely that the corresponding bit will be modified during subsequent decoding or detection processes. As such, the bit or symbol is effectively frozen. Similarly, in cases where a lower value of soft data indicates a greater likelihood that a corresponding bit or symbol of the hybrid layer codeword has been correctly determined, setting the soft data to a minimum value makes it very unlikely that the corresponding bit will be modified during subsequent decoding or detection processes. Detected output 633 is provided to a local interleaver circuit 642. Local interleaver circuit 642 is operable to shuffle sub-portions (i.e., local chunks) of the data set included as detected output and provides an interleaved codeword 646 that is stored to central memory circuit 650. Interleaver circuit 642 may be any circuit known in the art that is capable of shuffling data sets to yield a re-arranged data set. Interleaved codeword 646 is stored to central memory circuit 650.

Once hybrid layer data decoding circuit 670 is available, a previously stored interleaved codeword 646 is accessed from central memory circuit 650 as a stored codeword 686 and globally interleaved by a global interleaver/de-interleaver circuit 684. Global interleaver/De-interleaver circuit 684 may be any circuit known in the art that is capable of globally rearranging codewords. Global interleaver/De-interleaver circuit 684 provides a decoder input 652 into hybrid layer data decoding circuit 670. Decoder input 652 may be a hybrid layer codeword similar to that discussed above in relation to FIG. 2d where a number of component codewords are combined with hybrid encoding portions. In some embodiments of the present invention, the data decode algorithm is a layered low density parity check algorithm as are known in the art. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize other decode algorithms that may be used in relation to different embodiments of the present invention. Hybrid layer data decoding circuit 670 applies to data decode algorithm to decoder input 652 to yield a decoded output 671.

In operation, hybrid layer data decoding circuit 670 selects a first component codeword and the hybrid encoding portion as a first decoding layer. Using the example of FIG. 2c, hybrid layer data decoding circuit 670 selects, for example, the data in hybrid layer codeword corresponding to rows 272 and rows 276 is selected. As an example, rows 272 may include eight rows, and rows 276 may include two rows. Hybrid layer data decoding circuit 670 then applies the data decoding algorithm to the first decoding layer to yield a decoded output. This process of applying the data decode algorithm to the first decoding layer is repeated for a number of local iterations until either the component codeword associated with the first decoding layer converges, or until a maximum number of local iterations is exceeded. Where the first decoding layer converges, the soft data associated with the first decoding layer is set to values representing the highest likelihood that data associated with the first decoding layer is correctly determined. In this way, the values in the hybrid encoding portion are effectively frozen while another decoding layer formed of another individual component codeword and the hybrid encoding portion is decoded. This provides additional guidance to the decoding process applied to subsequent layers. Alternatively, where the first decoding layer fails to converge before the maximum number of local iterations has been exceeded, the soft data is left as it existed after the last local iteration. At this point, decoding of the first decoding layer is complete.

With the decoding of the first decoding layer completed, hybrid layer data decoding circuit 670 selects a second component codeword and the hybrid encoding portion as a second decoding layer. Using the example of FIG. 2c, hybrid layer data decoding circuit 670 selects, for example, the data in hybrid layer codeword corresponding to rows 274 and rows 276 is selected. As an example, rows 274 may include eight rows, and rows 276 may include two rows. Hybrid layer data decoding circuit 670 then applies the data decoding algorithm to the second decoding layer to yield a decoded output. This process of applying the data decode algorithm to the second decoding layer is repeated for a number of local iterations until either the component codeword associated with the second decoding layer converges, or until a maximum number of local iterations is exceeded. Where the second decoding layer converges, the soft data associated with the second decoding layer is set to values representing the highest likelihood that data associated with the second decoding layer is correctly determined. Again, in this way, the values in the hybrid encoding portion are effectively frozen while another decoding layer formed of another individual component codeword and the hybrid encoding portion is decoded. This provides additional guidance to the decoding process applied to subsequent layers.

This process of applying the data decode algorithm sequentially to decoding layers continues until all of hybrid codewords corresponding to individual component codewords are decoded. Thus, while the example in FIG. 2c implies a hybrid layer codeword comprised of two component codewords, data processing circuit 600 may operate on hybrid layer codewords exhibiting three or more component codewords. Where less than all of the individual component codewords converge, decoding of the hybrid layer codeword fails to converge. In such a case, the resulting decoded output is provided as a decoded output 654 back to central memory circuit 650 where it is stored awaiting another global iteration through a data detector circuit included in data detector circuit 630. Prior to storage of decoded output 654 to central memory circuit 650, decoded output 654 is globally de-interleaved to yield a globally de-interleaved output 688 that is stored to central memory circuit 650. The global de-interleaving reverses the global interleaving earlier applied to stored codeword 686 to yield decoder input 652. When a data detector circuit included in data detector circuit 630 becomes available, a previously stored de-interleaved output 688 accessed from central memory circuit 650 and locally de-interleaved by a de-interleaver circuit 644. De-interleaver circuit 644 re-arranges decoder output 648 to reverse the shuffling originally performed by interleaver circuit 642. A resulting de-interleaved output 697 is provided to data detector circuit 630 where it is used to guide subsequent detection of a corresponding data set previously received as equalized output 625.

Alternatively, where all of the individual component codewords converge, decoding of the hybrid layer codeword to converges (i.e., yields the originally written data set), the resulting decoded output is provided as an output codeword 672 to a de-interleaver circuit 680. De-interleaver circuit 680 rearranges the data to reverse both the global and local interleaving applied to the data to yield a de-interleaved output 682. De-interleaved output 682 is provided to a hard decision output circuit 690. Hard decision output circuit 690 is operable to re-order data sets that may complete out of order back into their original order. The originally ordered data sets are then provided as a hard decision output 692.

Turning to FIG. 7, a flow diagram 700 shows a method in accordance with some embodiments of the present invention for applying hybrid layer decoding to data encoded by the encoding circuit of FIG. 5. Following flow diagram 700, N sectors of data are received as spread sector interleaved data (block 705). The spread sector interleaved data includes portions of different individual sectors of data interleaved or shuffled to limit the effect of localized noise. Analog processing is applied to the received data to yield an equalized output corresponding to the N sectors of spread sector data (block 710). The equalized output is de-interleaved to combine the portions of each respective sector of data to yield N de-interleaved sectors (block 715). The de-interleaving reverses the spread sector interleaving originally applied to limit the effect of localized noise.

One of the N de-interleaved sectors is selected (block 720). Data detection/data decoding is applied to the selected sector to yield a decoded output (block 725). This data detection/data decoding may be performed similar to that discussed above in relation to FIG. 6. It is determined whether the decoding converged (i.e., yielded the correct result) (block 730). Where the data decoding failed to converge (block 730), a failure of the currently processing selected sector of data is indicated (block 745). Alternatively, where the data decoding did converge (block 730), the syndrome for the sector is calculated and stored in relation to the selected sector (block 735). This syndrome is calculated similar to the syndrome calculation of the encoding process discussed above in relation to FIG. 5. In addition, the decoded output is provided as a converged output (block 740).

It is determined whether another of the N-de-interleaved sectors remains to be detected/decoded (block 750). Where another sector remains to be detected/decode (block 750), the next one of the N de-interleaved sectors is selected (block 720) and the processing proceeds for the selected sector. Alternatively, where no additional sectors remain to be detected/decoded (block 750), it is determined whether only one of the N de-interleaved sectors failed to converge (block 755). Where only one sector failed to converge it is possible to use the syndrome information calculated for each of the N−1 sectors that did converge to calculate a sector for the failed sector, and to re-apply the data detection and the data decoding using the syndrome expected for the failed sector to yield a corrected output (block 760). As the overall syndrome is expected to be ‘0’ (or another predefined value) as described above in relation to FIG. 5, the syndrome for the sector that is failed to converge is calculated in accordance with the following equation:

$\mathrm{Expected}\mathrm{Syndrome}=\sum _{i=1}^{N-1}S_i,$

where Si represents the syndrome values calculated from the other N−1 sectors that did not fail to converge. This expected syndrome is used to correct one or more errors in the failed sector. As such, hybrid layer decoding is applied using an implied value for the overall syndrome value.

It should be noted that the various blocks discussed in the above application may be implemented in integrated circuits along with other functionality. Such integrated circuits may include all of the functions of a given block, system or circuit, or a subset of the block, system or circuit. Further, elements of the blocks, systems or circuits may be implemented across multiple integrated circuits. Such integrated circuits may be any type of integrated circuit known in the art including, but are not limited to, a monolithic integrated circuit, a flip chip integrated circuit, a multichip module integrated circuit, and/or a mixed signal integrated circuit. It should also be noted that various functions of the blocks, systems or circuits discussed herein may be implemented in either software or firmware. In some such cases, the entire system, block or circuit may be implemented using its software or firmware equivalent. In other cases, the one part of a given system, block or circuit may be implemented in software or firmware, while other parts are implemented in hardware.

In conclusion, the invention provides novel systems, devices, methods and arrangements for data processing. While detailed descriptions of one or more embodiments of the invention have been given above, various alternatives, modifications, and equivalents will be apparent to those skilled in the art without varying from the spirit of the invention. Therefore, the above description should not be taken as limiting the scope of the invention, which is defined by the appended claims.

Claims

1. A data processing system, the data processing system comprising: a data encoder circuit operable to: receive N data sets;apply a data encoding algorithm to each of N−1 of the N data sets to yield respective N−1 encoded outputs using a predefined encoding value;calculate a syndrome value for each of the N−1 encoded outputs to yield N−1 syndrome values;aggregate the N−1 syndrome values to yield an aggregate syndrome value; andapply the data encoding algorithm to the Nth of the N data sets to yield an Nth encoded output using the aggregate syndrome value in place of the predefined encoding value.

2. The data processing system of claim 1, wherein the aggregate syndrome value plus a syndrome value corresponding to the Nth encoded output is equal to the predefined encoding value.

3. The data processing system of claim 2, wherein the predefined encoding value is ‘0’.

4. The data processing system of claim 2, wherein the encoding algorithm includes XORing an interim value of the Nth encoded output with the aggregate syndrome value as part of generating the Nth encoded output.

5. The data processing system of claim 4, wherein the encoding algorithm includes XORing an interim value of a processing data set with the predefined encoding value during encoding of each of the N−1 of the N data sets.

6. The data processing system of claim 1, wherein the encoder circuit comprises: a selector circuit operable to provided a selection output, wherein the selection output is selected from a group consisting of: the predefined encoding value during application of the data encoding algorithm to each of the N−1 of the N data sets; and the aggregate syndrome value during application of the data encoding algorithm to the Nth of the N data sets; andan XOR circuit operable to receive an interim value corresponding to one of the N data sets, and to XOR the interim value with the selection output.

7. The data processing system of claim 6, wherein the difference between applying the data encoding algorithm to the N−1 of the N data sets and applying the data encoding algorithm to the Nth of the N data sets is a difference between the source of the selection output.

8. The data processing system of claim 7, wherein the selection output is the aggregate syndrome value during application of the second data encoding algorithm to the Nth of the N data sets, and wherein the selection input is a predefined value during application of the first data encoding algorithm to the N−1 of the N data sets.

9. The data processing system of claim 8, wherein the predefined encoding value is ‘0’.

10. The data processing circuit of claim 1, wherein the difference between applying the data encoding algorithm to the N−1 of the N data sets and applying the data encoding algorithm to the Nth of the N data sets is limited to use of the predefined encoding value during encoding of the N−1 of the N data sets and to use of the aggregate syndrome value during encoding of the Nth of the N data sets.

11. The data processing system of claim 1, wherein data encoding algorithm is a low density parity check encoding algorithms.

12. The data processing system of claim 1, wherein the data encoder circuit includes: a concatenation circuit operable to combine the N−1 encoded outputs and the N-th encoded output to yield a transfer codeword.

13. The data processing system of claim 12, wherein the predefined encoding value is only implicit in the transfer codeword.

14. The data processing system of claim 12, wherein the data processing system is part of a data storage device including a storage medium, and wherein storage information derived from the transfer codeword is stored to the storage medium.

15. The data processing system of claim 12, wherein the data processing system is part of a communication device operable to transfer information derived from the transfer codeword via a transfer medium.

16. The data processing system of claim 1, wherein the data processing system is implemented as part of an integrated circuit.

17. A method for data processing, the method comprising: receiving N data sets;applying a data encoding algorithm to each of N−1 of the N data sets to yield respective N−1 encoded outputs using a predefined encoding value;calculating a syndrome value for each of the N−1 encoded outputs to yield N−1 syndrome values;aggregating the N−1 syndrome values to yield an aggregate syndrome value; andapplying the data encoding algorithm to the Nth of the N data sets to yield an Nth encoded output using the aggregate syndrome value in place of the predefined encoding value.

18. The method of claim 17, wherein the aggregate syndrome value plus the Nth syndrome value is equal to the predefined encoding value.

19. The method of claim 18, wherein the predefined encoding value is ‘0’.

20. The method of claim 18, wherein the predefined encoding value is XORed with a first interim encoding value during application of the data encoding algorithm to the N−1 of the N data sets; and wherein the aggregate syndrome value is XORed with a second interim encoding value during application of the data encoding algorithm to the Nth of the N data sets.