BACKGROUND OF THE INVENTION
In Micro-Electro Mechanical Systems (MEMS) device fabrication, silicon epitaxy layer thickness must meet very tight tolerances in order to attain desired performance criteria. Presently, analysis of epitaxy layer thickness is performed in a destructive manner. A wafer is cut and stained then analyzed under a microscope in order to determine the thickness of the epitaxy layer. Thus, a wafer is destroyed and sometimes multiple wafers are destroyed in a batch of wafers in order to accurately analyze the results of the epitaxy layer manufacturing process.
Therefore, there exists a need for analyzing the epitaxy layer thickness without destroying product.
SUMMARY OF THE INVENTION
The present invention provides systems and methods for measuring thickness of an epitaxial layer grown on a silicon wafer. In one embodiment an oxide layer is generated on a side of the silicon wafer. One or more posts of oxide are created from the oxide layer by masking and removing unwanted oxide. An epitaxial layer is grown on the side of the silicon wafer over the one or more oxide posts. The epitaxial layer is removed in an area that includes at least the epitaxial layer grown on the one or more oxide posts. Then, the one or more oxide posts are removed. The thickness of the epitaxial layer is determined by measuring a difference between distance in height of a surface of the silicon wafer previously attached to one of the one or more oxide posts and a top surface of the epitaxial layer.
BRIEF DESCRIPTION OF THE DRAWINGS
The preferred and alternative embodiments of the present invention are described in detail below with reference to the following drawings.
FIGS. 1A-1G illustrate partial cross-sectional images of stages in a process for manufacturing a wafer in order to analyze epitaxy thickness;
FIG. 2 illustrates a top-down view of a wafer having epitaxy thickness test regions formed in accordance with an embodiment of the present invention;
FIG. 3 is a blocked diagram of a system used to measure epitaxy thickness after the process shown in FIGS. 1A-1G is performed; and
FIG. 4 illustrates an example process for acting upon the results of the measurements performed by the measuring system shown in FIG. 3.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
FIGS. 1A-1G illustrate partial cross-sectional views of a wafer through various stages of a process that allows for the highly accurate method for preparing an epitaxial layer for measurement.
FIG. 1A illustrates a wafer 20 that is formed of silicon substrate. At FIG. 1B, a layer of silicon oxide (SiO2) 22 is applied to the silicon substrate. At FIG. 1C, a mask, such as a photoresist, has been applied to the oxide layer 22 and the exposed oxide is etched according to the mask. The photoresist is then removed and what remains is the silicon substrate with the oxide posts 24. The oxide posts 24 may be distributed at various locations about the wafer 20.
At a FIG. 1D, an epitaxial layer 26 is grown on top of the substrate and the oxide posts 24. The epitaxial layer 26 is grown to a pre-specified height specification. At a FIG. 1E, a pattern/mask is applied over the epitaxial layer 26 in order to mask off everything but a region around the oxide posts 24. Then, the epitaxy layer in the exposed regions is removed by silicon DRIE (Deep Reactive Ion Etch).
As shown in FIG. 1F, the exposed epitaxial layer has been removed as well as some of the silicon substrate from the wafer 26. The pattern/mask is then removed and at FIG. 1G, the oxide posts 24 are removed by an etching process, such as Buffered Oxide Etch (BOE) or other oxide etching techniques. At this point, the thickness of the epitaxial layer 26 can be accurately measured by a profilometer or other measuring device by measuring the difference between the exposed top surface of the epitaxial layer 30 and a surface 32 that is exposed after removal of the oxide post 24. The exposed surface 32 is the original surface of the wafer 20.
FIG. 2 illustrates a top view of a wafer 40 that includes four epitaxial thickness layer test regions 42 that are distributed about the wafer 40. In this embodiment, each of the test areas 42 include one or more of the measurement regions (FIG. 1G). This allows a user to analyze a plurality of locations on a silicon wafer in a nondestructive manner without taking up very much space at all.
FIG. 3 illustrates an epitaxial thickness measuring device 60 that includes a profilometer 62 that is in data communication with a controller 64. The profilometer 62 measures the height of the surface of the epitaxial layer (surface 30, FIG. 1G) and compares that to the height of the exposed surface of the silicon substrate that was exposed after removal of the oxide posts 24 (surface 32, FIG. 1G). The device 60 quickly and accurately measures the epitaxial layer at each of the test locations 42 and at multiple locations within each of the test locations 42. In one embodiment, the controller 64 takes the average of the measured height values from multiple locations and determines if the epitaxial layer 26 meets predefined thickness standards.
FIG. 4 illustrates a flow diagram of a process 100 that is performed using the processes and systems described above. First, at a decision block 104, an operator determines based on the information outputted by the device 60 if the thickness of the epitaxial layer is less than or greater than a predefined threshold value. In this example, the predefined threshold value is an epitaxial thickness range associated with a particular device layer mask(s). If at the decision block 104, the thickness of the epitaxial layer is not less than or greater than the threshold value, then at a block 106, the epitaxial layer is acceptable for use with the device layer mask that is associated with the threshold value. If the thickness of the epitaxial thickness is either less than or greater than the threshold value then, at a decision block 110, the operator determines if the thickness is outside of acceptable limits. Acceptable limits would be an epitaxial layer thickness that is outside of specifications for any device layer masks that are presently used. If at the decision block 110, the thickness of the epitaxial layer is not outside the acceptable limits, then at a block 112, the operator selects a proper device layer mask that would be acceptable for use with the measured thickness of the epitaxial layer. If, however, at the decision block 110, the thickness is outside of acceptable limits, the manufacturer who grew the epitaxial layer on the wafers informed of a failure at a block 114. At this stage, the epitaxy manufacturer may re-tool in order to adjust their system in order to get the epitaxial layer growth to fall within acceptable limits. After the steps performed at blocks 106, 112, and 114, the entire process is repeated for all wafers, see block 116.
While the preferred embodiment of the invention has been illustrated and described, as noted above, many changes can be made without departing from the spirit and scope of the invention. Accordingly, the scope of the invention is not limited by the disclosure of the preferred embodiment. Instead, the invention should be determined entirely by reference to the claims that follow.
Patent Application
20070004056
