Patent Application
20210263720
The technology of the disclosure relates generally to memory and more particularly, to FLASH memory and still more particularly, to conflict avoidance in Not-AND (NAND) FLASH memory.
Computers and computing devices have become common in modern society. The proliferation of computing devices is attributable in part to their increasing power provided in ever smaller packages. As the size of computing devices has shrunk, it has become practical to have mobile computing devices. Both mobile computing devices and traditional desktop style computing devices rely on memory elements to store applications, data, operating systems, and the like.
One popular type of memory for mobile computing devices is FLASH memory, which may be made from electronically erasable program read only memory (EEPROM) which in turn may be formed from Not-AND (NAND) gate structures. Such NAND-based FLASH memory is sometimes referred to as NAND FLASH. NAND FLASH degrades as a function of time and use and various techniques have been developed to extend FLASH lifetimes. One such technique is known as scrubbing, by which information in one partition of the memory element is written to a new partition and individual memory cells are evaluated for age and reliability. After verifying the reliability of the memory cells in the first partition, those memory cells may be reused (e.g., by the original information or by new information). Unreliable memory cells are no longer used. In a typical computing device, NAND FLASH may be scrubbed about once every three months.
NAND FLASH may also store firmware, which may periodically be updated to provide new functionality, fix bugs, or in response to some other demand. For mobile computing devices, a process termed firmware over the air (FOTA) has been developed which allows information to be downloaded to the mobile computing device wirelessly (i.e., over the air) and then written into the memory cells where the older version of the firmware resides. It should be appreciated that there may be occasions when scrubbing takes place concurrently with a FOTA update. This concurrent use of the memory cells may create conflicts and may cause the information to become corrupted to the extent that the computing device is non-operational. Accordingly, a technique for conflict avoidance may be of benefit to avoid “bricking” the computing device.
Aspects disclosed in the detailed description include systems and methods for flash memory conflict avoidance. In an exemplary aspect, a firmware over the air (FOTA) update is given priority over a scrubbing operation unless the memory element meets or exceeds a predefined health degradation parameter. When the memory element meets or exceeds the predefined health degradation parameter, the scrubbing operation is given priority over the FOTA update. By enforcing these priorities, scrubbing and FOTA updates do not occur at the same time and conflicts are thereby avoided. Since conflicts are avoided, the chance of memory corruption is decreased and the chance of “bricking” the computing device is likewise decreased.
In this regard, in one aspect, a method for managing conflicts in memory use is disclosed. The method includes receiving a FOTA update request for a memory partition. The method also includes suspending a scrubbing operation for the memory partition for a predetermined amount of time while completing the FOTA update request. The method also includes resuming the scrubbing operation when the FOTA update request is completed.
In another aspect, an integrated circuit (IC) is disclosed. The IC includes an interface configured to be coupled to a memory circuit comprising a plurality of memory partitions over a bus. The IC also includes a control circuit coupled to the interface. The control circuit is configured to receive a FOTA update request for a memory partition in the memory circuit. The control circuit is also configured to suspend a scrubbing operation for the memory partition for a predetermined amount of time while completing the FOTA update request. The control circuit is also configured to resume the scrubbing operation when the FOTA update request is completed.
In another aspect, a computing device is disclosed. The computing device includes a bus. The computing device also includes a memory circuit comprising a plurality of memory partitions. The memory circuit is coupled to the bus. The computing device also includes a control circuit coupled to the bus. The control circuit is configured to receive a FOTA update request for a memory partition in the memory circuit. The control circuit is also configured to suspend a scrubbing operation for the memory partition for a predetermined amount of time while completing the FOTA update request. The control circuit is also configured to resume the scrubbing operation when the FOTA update request is completed.
With reference now to the drawing figures, several exemplary aspects of the present disclosure are described. The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.
Aspects disclosed in the detailed description include systems and methods for flash memory conflict avoidance. In an exemplary aspect, a firmware over the air (FOTA) update is given priority over a scrubbing operation unless the memory element meets or exceeds a predefined health degradation parameter. When the memory element meets or exceeds the predefined health degradation parameter, the scrubbing operation is given priority over the FOTA update. By enforcing these priorities, scrubbing and FOTA updates do not occur at the same time and conflicts are thereby avoided. Since conflicts are avoided, the chance of memory corruption is decreased and the chance of “bricking” the computing device is likewise decreased.
Before addressing particulars of prioritizing the scrubbing operation or the FOTA updates, a brief overview of exemplary contexts that may benefit from the present disclosure is provided with reference to
In this regard,
Other devices can be connected to the system bus 208. As illustrated in
The CPU(s) 202 may also be configured to access the display controller(s) 220 over the system bus 208 to control information sent to one or more displays 226. The display controller(s) 220 sends information to the display(s) 226 to be displayed via one or more video processors 228, which process the information to be displayed into a format suitable for the display(s) 226. The display(s) 226 can include any type of display, including, but not limited to, a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, a light emitting diode (LED) display, etc.
While
In general, scrubbing involves the relocation of a partition and an update to the MIBIB. Thus, while FOTA updates have been discussed above, a brief discussion of scrubbing operations and problems that can arise from FOTA/scrubbing conflicts is provided with reference to
Conflicts may occur when there is a FOTA update at the same time the firmware partition is being scrubbed as illustrated in
To avoid such conflicts, exemplary aspects of the present disclosure contemplate allowing FOTA updates to have priority over and suspend scrubbing operations unless the health of the memory to be scrubbed is below a predefined threshold. When the health of the memory to be scrubbed is below the predefined threshold, FOTA updates are suspended until the scrubbing operation is complete.
In this regard,
By way of further explanation, the control circuit in the modem or CPU 202 may include a FOTA module (not shown). The FOTA module may be software or hardware and may handle the FOTA updates. Further, exemplary aspects of the present disclosure allow the FOTA module in the control circuit to disable scrubbing for a requested amount of time (e.g., T1). The disable request may disable scrubbing until an enable scrub request is sent or for the requested amount of time. An example message flow 700 showing these requests is provided with reference to
Note that it is possible that the FOTA circuit 702 may not complete the FOTA update in the time T1, and thus, exemplary aspects of the present disclosure contemplate that the FOTA circuit 702 may make time extension requests (sometimes referred to as timer requests) as better illustrated by a message flow 800 illustrated in
To prevent a telescoping FOTA update from monopolizing use of the FLASH memory and completely precluding a scrubbing operation, there may be a mechanism in place to preclude the FOTA update from proceeding if the health of the NAND FLASH is below a certain threshold. As shown in the process 600, that threshold may be defined in terms of a sequence number. That is, the FOTA circuit should take responsibility in taking feedback from the NAND FLASH memory regarding the health of cells which may be degraded due to the read-disturb phenomenon and/or other adverse environmental conditions (e.g., heat) using health descriptors. Such health may limit the number of times that the FOTA update can delay a scrubbing operation. Once past this limit, a health monitor scrubbing operation may be triggered.
One way that the health monitor may be implemented is through the previously mentioned sequence number. Each partition may be assigned a sequence number that is incremented for every erase or scrubbing operation performed on that partition. By way of example, if an expected lifecycle of a FLASH memory circuit is fifteen years, and scrubbing operations occur every two months, then a maximum sequence number may be ninety (15 years×6 scrubs/year). Accordingly, a health monitor check infers that the health of a given partition is low if the sequence number is greater than forty-five (45), and forty-five may be set as the threshold above which a FOTA update is held in abeyance while scrubbing takes place and below which the FOTA update delays the scrubbing operation. This threshold may be set by a memory vendor at some other level as needed or desired (e.g., if the vendor knows the life expectancy is different or the scrub frequency is different). Once a scrubbing operation is complete and the partitions are rearranged, the scrub circuit may hand over control of the partitions to the FOTA circuit along with the changed page-table. Then, the FOTA circuit may resume its process.
In an exemplary aspect, the FOTA circuit may capture certain additional information in evaluating the health of the memory circuit. In particular, the device temperature may be determined from a temperature sensor (not shown) and the sequence number may be used. The scrub disable timer may be a function of both the temperature and the sequence number. That is, the timer may be allowed to be high if the temperature is low and the sequence number is below a threshold (e.g., P defined above). However, if either the temperature is high or the sequence number is above the threshold (P), then the timer may be limited to a low number or the FOTA update may be suspended until the scrub is done. Still other parameters may be evaluated in determining when to suspend or defer FOTA updates in favor of the scrubbing operation.
An alternate process 900 is provided in
Still another alternate process 1000 is illustrated in
The systems and methods for flash memory conflict avoidance according to aspects disclosed herein may be provided in or integrated into any processor-based device. Examples, without limitation, include a set top box, an entertainment unit, a navigation device, a communications device, a fixed location data unit, a mobile location data unit, a global positioning system (GPS) device, a mobile phone, a cellular phone, a smart phone, a session initiation protocol (SIP) phone, a tablet, a phablet, a server, a computer, a portable computer, a mobile computing device, a wearable computing device (e.g., a smart watch, a health or fitness tracker, eyewear, etc.), a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, a portable digital video player, an automobile, a vehicle component, avionics systems, a drone, and a multicopter.
Those of skill in the art will further appreciate that the various illustrative logical blocks, modules, circuits, and algorithms described in connection with the aspects disclosed herein may be implemented as electronic hardware, instructions stored in memory or in another computer readable medium and executed by a processor or other processing device, or combinations of both. The devices described herein may be employed in any circuit, hardware component, integrated circuit (IC), or IC chip, as examples. Memory disclosed herein may be any type and size of memory and may be configured to store any type of information desired. To clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. How such functionality is implemented depends upon the particular application, design choices, and/or design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.
The various illustrative logical blocks, modules, and circuits described in connection with the aspects disclosed herein may be implemented or performed with a processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).
The aspects disclosed herein may be embodied in hardware and in instructions that are stored in hardware, and may reside, for example, in Random Access Memory (RAM), flash memory, Read Only Memory (ROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), registers, a hard disk, a removable disk, a CD-ROM, or any other form of computer readable medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a remote station. In the alternative, the processor and the storage medium may reside as discrete components in a remote station, base station, or server.
It is also noted that the operational steps described in any of the exemplary aspects herein are described to provide examples and discussion. The operations described may be performed in numerous different sequences other than the illustrated sequences. Furthermore, operations described in a single operational step may actually be performed in a number of different steps. Additionally, one or more operational steps discussed in the exemplary aspects may be combined. It is to be understood that the operational steps illustrated in the flowchart diagrams may be subject to numerous different modifications as will be readily apparent to one of skill in the art. Those of skill in the art will also understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.
The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations. Thus, the disclosure is not intended to be limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
