Embodiments of the present disclosure relate to systems and methods for testing electronic signals, and more particularly to systems and methods for measuring signal waveforms.
Digital storage oscilloscopes (DSOs) and other measurement devices may analyze an electronic signal in order to measure various characteristics of the electronic signal. These measurement devices may comprise a trigger system to trigger in response to various events of the electronic signal, such as an edge, a level, a glitch, a slew rate, and a runt, for example. Accordingly, the triggering may result in capturing a desired waveform from an electronic device.
Furthermore, a measurement device usually provides a plurality of channels (e.g., four channels), each of which may be used as a trigger source to simultaneously observe analog characteristics of several electronic signals. However, it is difficult to capture desired waveforms for more complicated observations, such as simultaneously testing several electronic signals in high-speed circuits. For example, while testing a high-speed memory chip or a central processing module (CPU), electronic signals with a specified timing are desired to be observed. In this case, a user often has to manually control the measurement device by repeatedly pressing a capture button until desired waveforms are finally captured. This method is often inefficient and labor intensive.
What is needed, therefore, is systems and methods for measuring signal waveforms allowing for a more efficient and less labor intensive way to capture and analyze signal waveforms.
A system for measuring a signal waveform is provided. The system comprises a parameter receiving module, a waveform receiving module, a waveform filter, and a data storing module. The parameter receiving module is configured for receiving one or more filtration conditions. The waveform receiving module is configured for receiving the signal waveform. The waveform filter is configured for filtering the signal waveform to obtain a desired waveform, wherein the filtering comprises determining logic matrices for the signal waveform according to the one or more filtration conditions. The data storing module is configured for storing the desired waveform into a storage device.
Other objects, advantages and novel features will become more apparent from the following detailed description of certain embodiments of the present disclosure when taken in conjunction with the accompanying drawings, in which:
The test instrument 1 is configured for capturing signal waveforms from a circuit under test (CUT) 5. The signal waveforms may be in a format of *.cvs, *.xls or any other suitable files, for example. In one embodiment, the test instrument 1 may be a digital storage oscilloscope (DSO) or any other test device that can capture signal waveforms. In one embodiment, the test instrument 1 provides four channels (such as CH1, CH2, CH3, and CH4) connected to the CUT 5 for testing electronic signals from the CUT 5.
The CUT 5 may comprise a motherboard, a CPU, or a high-speed memory chip, such as a double-data rate (DDR) memory. Accordingly, the CUT 5 may comprise a clock signal. A channel (e.g., CH1) of the test instrument 1 may be connected to the clock signal. Other channels (e.g., CH2, CH3, and CH4) of the test instrument 1 may be connected to three other electronic signals of the CUT 5 to be analyzed. The test instrument 1 may simultaneously capture a set of signal waveforms including a CH1 waveform (i.e., a clock signal waveform), a CH2 waveform, a CH3 waveform, and a CH4 waveform. It may be understood that a signal waveform is a graph of voltage plotted against time, with voltage represented by a Y-axis, and time represented by an X-axis of a coordinate axis system. It may be further understood that each of a set of signal waveforms may be divided into a plurality of waveform segments on the X-axis of the coordinate axis system, where each of the signal waveform segments represents a clock period interval.
Filtration conditions may be used to define criteria that desired waveforms are required to fit. For example, conditions about timing (hereinafter, “timing conditions”), conditions about single channel signal integrity (SI) parameter (hereinafter, “single channel SI parameter conditions”), and condition about inter-channel SI parameter (hereinafter, “inter-channel SI parameter conditions”) may compose the filtration conditions and will be further explained herein. Depending on the embodiment, the filtration conditions may include any combination of conditions as mentioned above.
The computing device 2 includes a measurement unit 20. It may be understood that the computing device 2 may comprise one or more processors, such a processor 21 to execute the measurement unit 20. The measurement unit 20 is configured for controlling the test instrument 1 to capture signal waveforms from the CUT 5 via the respective channels and for receiving the signal waveforms from the test instrument 1. The measurement unit 20 may filter the signal waveforms to obtain one or more desired waveforms according to filtration conditions and store the desired waveforms into the storage device 3. Furthermore, the measurement unit 20 may be configured for analyzing the desired waveforms in accordance with a user's preference, and output a result to the display device 4. The desired waveforms have at least one waveform segment that meets at least one of the filtration conditions as described above. The user's preference may include a time-domain analysis, a frequency-domain analysis, and an abnormal signal analysis, for example. The user's preference, in one embodiment, may correspond to a user controlling the computing device 2 via a test file, where the test file comprises instructions for the computing device 2.
The storage device 3 communicates with the computing device 2, and is configured for storing the desired waveforms transmitted from the computing device 2.
The display device 4 is configured for displaying a result of an analysis of the desired waveforms from the measurement unit 20. The display device 4 may comprise one or more displays arranged in various positions to display the result of the desired waveform analysis.
The parameter receiving module 201 is configured for receiving a predetermined number and one or more filtration conditions defined by a user. Depending on the embodiment, the predetermined number may define a number of sets of desired waveforms that meet the one or more filtration conditions, or define a number of waveform segments that meet the one or more filtration conditions. Each time the test instrument 1 obtains a set of signal waveforms from the CUT 5, the set of signal waveforms may contain more than one waveform segment that meet the one or more filtration conditions.
The waveform receiving module 202 is configured for generating and sending instructions to the test instrument 1 so as to control the test instrument 1 to respond to the instructions. The instructions include establishing connections, initializing, and causing triggers, for example. The waveform receiving module 202 is further configured for receiving the signal waveforms from the test instrument 1.
The waveform filter 203 is configured for filtering the signal waveforms to obtain desired waveforms according to the one or more filtration conditions. The waveform filter 203 includes a parameter matrix determining module 2031 and a determining module 2032. The parameter matrix determining module 2031 is configured for determining related matrices for the signal waveforms, such as a voltage matrix, a feature point matrix, a SI parameter matrix, a timing logic matrix, a single channel SI logic matrix, and an inter-channel SI logic matrix, for example. The determining module 2032 is configured for determining if the signal waveforms are a set of desired waveforms, and for determining if a count of desired waveforms is less than the predetermined number. It may be understood that the count of desired waveforms may be the count of sets of desired waveforms.
The data storing module 204 is configured for storing the desired waveforms into the storage device 3.
The waveforms analyzing module 205 is configured for analyzing the desired waveforms according to a user's preference. As mentioned above, the user's preference may include a time-domain analysis, a frequency-domain analysis, and an abnormal signal analysis, for example.
The outputting module 206 is configured for outputting a result of an analysis of the desired waveforms to the display device 4.
In block S300, the parameter receiving module 201 receives a predetermined number and one or more filtration conditions determined by a user. As mentioned above, the predetermined number may define a number of sets of desired waveforms that meet the one or more filtration conditions, or define a number of waveform segments that meet the one or more filtration conditions. Each time the test instrument 1 obtains a set of signal waveforms from the CUT 5, the set of signal waveforms may contain one or more waveform segment that meet the filtration conditions.
In block S301, the waveform receiving module 202 generates and sends instructions to the test instrument 1 so as to control the test instrument 1 to respond to the instructions. As mentioned above, the test instrument 1 may trigger on events such as an edge, a level, a glitch, and a runt. For example, the test instrument 1 may trigger on a rise of a clock signal. To obtain sufficient data, in one embodiment, the test instrument 1 captures as much data as it can on each trigger.
In block S302, the test instrument 1 captures a set of signal waveforms according to the instructions. In one particular example, the test instrument 1 captures four signal waveforms from the CUT 5, which comprises a clock signal waveform.
In block S303, the waveform receiving module 204 receives the set of signal waveforms (i.e. the four signal waveforms) from the test instrument 1.
In block S304, the parameter matrix determining module 2031 determines logic matrices for the set of signal waveforms according to the filtration conditions. As mentioned above, the logic matrices may include a timing logic matrix, a single channel SI logic matrix, and an inter-channel SI logic matrix. Before determining the logic matrices, the parameter matrix determining module 2031 may determine voltage matrices and the SI parameter matrices for the signal waveforms. Further details of determining logic matrices are described in
In block S305, the determining module 2032 determines if the set of signal waveforms are a set of desired waveforms. The determining module may check the logic matrices determined in block S304 as explained in greater detail in
If the signal waveforms are a set of desired waveforms, in block S306, then the data storing module 204 stores the desired waveforms into the storage device 3. It may be understood that the data storing module 204 may only store representative data of the desired waveforms into the storage device 3, such as the voltage matrices and the SI parameter matrices, for example.
In block S307, the determining module 2032 determines if a count of the desired waveforms is less than the predetermined number. If the count of the desired waveforms is less than the predetermined number, then the flow may move to block S301.
Otherwise, if the count of the desired waveforms is equal to the predetermined number, in block S308, then the waveforms analyzing module 205 analyzes the desired waveforms according to the user's preference.
In block S309, the outputting module 206 outputs a result of an analysis of the desired waveforms to the display device 4.
In block S400, the parameter matrix determining module 2031 may determine a voltage matrix for the signal waveforms. The voltage matrix may define a column number of the voltage matrix equal to a number of sampling points of each signal waveform captured by the test instrument 1. It may be understood that a matrix may have one or more rows and one or more columns defining the matrix. For example, a 3×5 matrix has a column number 5 and a row number 3.
In block S401, the parameter matrix determining module 2031 determines feature points for the signal waveforms, and correspondingly determines a feature point matrix. Further details of determining the feature point matrix are described below with respect to
In block S402, the parameter matrix determining module 2031 calculates SI parameters for the signal waveforms, and correspondingly determines a SI parameter matrix. Further details of determining the SI parameter matrix are described below with respect to
In block S403, the parameter matrix determining module 2031 determines a timing logic matrix by determining if each of the waveform segments satisfies the timing conditions according to the filtration conditions. The timing logic matrix may define a column number of the timing logic matrix equal to a period number of of the clock signal waveform. For example, if the clock signal waveform comprises 100 clock periods, then the column number of the timing logic matrix is 100, that is, the timing logic matrix has 100 columns. In one embodiment, results derived from the determining module 2032 may be represented as numbers, character strings, or Boolean quantities. Correspondingly, the timing logic matrix may be in a form of numbers, character strings, or Boolean quantities.
In block S404, the parameter matrix determining module 2031 determines a single channel SI logic matrix by determining if each of the waveform segments satisfies the single channel SI parameter conditions according to the filtration conditions. The single channel SI matrix may define a column number of the single channel SI matrix equal to a period number of the clock signal waveform. It may be understood that results derived from the determining module 2032 may be represented as numbers, character strings, or Boolean quantities. Correspondingly, the single channel SI logic matrix may be in a form of numbers, character strings, or Boolean quantities. The single channel SI parameter conditions may include, a positive pulse width, a negative pulse width, a rise time, and a fall time, for example. In one particular example, a single channel SI parameter condition for the channel A is a positive pulse width between 1.775 ns and 1.975 ns for a waveform segment, assuming a positive pulse width matrix of channel A is [0, 1.780, 1.525, 1.850, 0]. However, in another particular example, if “0” denotes true, and “1” denotes false, then a single channel SI logic matrix for channel A may be [0, 1, 0, 1, 0]. However, it may be understood that the single channel SI logic matrix, as well as other determined matrices may be much more complicated than the above mentioned matrices.
In block S405, the parameter matrix determining module 2031 determines an inter-channel SI logic matrix by determining if each of the waveform segments satisfies inter-channel SI parameter conditions according to the filtration conditions. The inter-channel SI logic matrix may define a column number of the s inter-channel SI logic matrix equal to a certain period of the clock signal waveform. It may be understood that results derived from the determining module 2032 may be represented as numbers, character strings, or Boolean quantities. Correspondingly, the inter-channel SI logic matrix may be in a form of numbers, character strings, or Boolean quantities. The inter-channel SI parameter conditions include, a positive pulse width difference, a negative pulse width difference, a rise time difference, a fall time difference, for example. For example, one inter-channel SI parameter condition is that a positive pulse width of channel A has to be greater than a positive pulse width of channel B. Assuming that a positive pulse width matrix of channel A is [0, 1.780, 1.525, 1.850, 0], a positive pulse width matrix of channel B is [0, 1.770, 1.545, 1.830, 0], and “0” denotes true, and “1” denotes false, then an inter-channel SI logic matrix may be [0, 1, 0, 1, 0], in one particular example.
Although certain inventive embodiments of the present disclosure have been specifically described, the present disclosure is not to be construed as being limited thereto. Various changes or modifications may be made to the present disclosure without departing from the scope and spirit of the present disclosure.
Number | Date | Country | Kind |
---|---|---|---|
200710201723.8 | Sep 2007 | CN | national |