Patent Application
20090024975
The present invention relates generally to physical design, development and manufacturing of integrated circuits (ICs) on semiconductor chips, for use in automated computing systems. More particularly, the present invention relates to an integrated circuit (IC) layout debugging method and tool.
When conducting hierarchical design and physical development of ICs, designers often face the problem of having voluminous smaller designs at various levels of the IC topological design hierarchy. When a layout person needs to trace signal paths, which traverse numerous design hierarchies within the same design window, all the viewable hierarchical design levels distract the layout person trying to conduct a debugging process involving only a few targeted hierarchical levels. Although current electronic design automation tools offer methods of traversing design hierarchies within the same design window, none of these electronic design automation tools offer an easy interface to allow the user to traverse design hierarchies.
Therefore, the need exists for a hierarchical design navigation method and a navigation apparatus for use in debugging layout induced design errors including design rule check (DRC) violations and layout-to-schematic verification (LVS) violations.
An additional need exists for a convenient design hierarchy method and device, which can save time and effort in debugging and repairing these errors.
Further, the need exists for a scroll mechanism to traverse design hierarchical design levels allowing users to control a definable viewable scope at different levels of design hierarchy quickly, which in turn will aid the debugging process.
A method and an apparatus are disclosed for the display of hierarchical navigation in the automated design of integrated circuits under test. A user, using a computer, assigns a head pointer assignment and a tail pointer assignment, which form a definition of a viewable scope of at least one hierarchical level of design from a plurality of hierarchical levels of design. The tail pointer assignment must be either equal to or greater than the head pointer assignment. These head pointer and tail pointer assignments are stored in a repository of the computer to set the definition of the viewable scope of the at least one hierarchical level of design. After being set, the viewable scope of the at least one hierarchical level of design is displayed on a computer display device, where the viewable scope of the at least one hierarchical level of design can be traversed by moving the viewable scope up and down, using a scrolling mechanism of the computer, and where the user controls the scrolling mechanism to perform the useful, concrete and tangible result of traversing the viewable scope of the at least one hierarchical level of design and conducting a debugging operation of the integrated circuit under test, without distractions from voluminous levels of IC topological information, of the plurality of hierarchical levels of design.
The subject matter that is regarded as the invention is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The foregoing and other objects, features, and advantages of the invention are apparent from the following detailed description taken in conjunction with the accompanying drawings, which are meant to be exemplary, and not limiting, wherein:
Exemplary embodiments of a method and an apparatus are disclosed for display of hierarchical navigation in the design automation process of the design, physical development and manufacturing of integrated circuits including head and tail pointers used to define the viewable scope of the desired design hierarchy to be traversed. The disclosed exemplary embodiments are intended to be illustrative only, since numerous modifications and variations therein will be apparent to those of ordinary skill in the art. In reference to the drawings, like numbers will indicate like parts continuously throughout the view. Further, the terms “a”, “an”, “first”, “second” and “third” herein do not denote limitations of quantity, but rather denote the presence of one or more of the referenced item(s).
The hierarchical and display navigation method 70 (herein referred to as “method 70”) and the hierarchical navigation and display system 20 (herein referred to as “system 20”) implementing method 70 are illustrated in
Referring to
In addition, system 20 includes a combination of controllers including display controller 23, memory controller 25 and input/output (I/O) controller 27 and a combination of computer peripheral devices cooperatively coupled to system 20 including display 21, a set of input devices including keyboard 60 and mouse 29, network interface 28, and output device 34, via standard interface connectivity. Network interface 28 cooperatively couples computer workstation processor 22 via network 50 to integrated circuit test cradle 51. An integrated circuit under test 52 is plugged into integrated circuit test cradle 51 to undergo testing and debugging exercises.
An integrated circuit under test 52 has a three dimensional layered topology of viewable design data comprising a plurality of hierarchical levels of design P53, which is composed of hierarchical levels of design L1, L2 up to Ln. Display 21 displays the plurality of hierarchical levels of design P53, when no limited viewable scope of hierarchical levels of design have been defined and set for viewing by the operator/user. In the alternative, display 21 displays only the viewable scope of hierarchical levels of design, which have been defined and set for viewing by the operator/user. By not displaying the viewable scope of the plurality of hierarchical levels of design, operator/user fatigue is reduced, causing the operator/user to make fewer mistakes in exercising the IC under test 52, during test and debugging operations in the IC design and development process.
Referring to
After the tail pointer P54 and the head pointer P55 assignments have been made, defining the viewable scope 195 of the hierarchical level or levels of design, L1, 12 or up to Ln, the tail pointer P54 and the head pointer P55 assignments are stored in entry locations R91, R92 up to Rn of hierarchical level of design repository 26 by either the operator/user or automatically by program 41 setting the definition of the viewable scope 195 of the at least one hierarchical level of design of the plurality of hierarchical levels of design P53.
Once the viewable scope 195 of the at least one hierarchical level of design is set by storing the tail pointer P54 and head pointer P55 assignments in entry locations R91, R92 up to Rn of hierarchical level of design repository 26, program 41 calls a first algorithm A31 of a plurality of algorithms composed of first algorithm A1, second algorithm A2, up to nth algorithm An from algorithm unit 30 to cause the viewable scope 195 of the at least one hierarchical level of design which is defined to be displayed by display 21. Once the viewable scope 195 of the at least one hierarchical level of design is defined and displayed on display 21, the operator/user can use a scrolling device to traverse the viewable scope 195 of the at least one hierarchical level of design by activating and moving the scrolling device up and down causing a corresponding up and down moving of a cursor on the screen of display 21. In this embodiment, the scrolling device can be mouse 29 or a combination of keys when activated on keyboard 60.
Therefore, the execution of program 41 by computer workstation processor 22, causes computer workstation process 22 to implement the embodiment of method 70 and thus provide an engineering design aid that the operator/user has programmed to perform the useful, concrete and tangible result of controlling a scrolling device to traverse the viewable scope 195 of one or more hierarchical levels of design in a graphical layout of an integrated circuit under test 52 displayed by display 21 and conduct a debugging operation of the integrated circuit under test 52, without the distraction from voluminous layers of IC topological information and resulting information overload while traversing the plurality of hierarchical levels of design P53.
At operation 76, method 70 either repeatedly returns to operation 72 where the viewable scope 195 of additional hierarchical levels of design can be defined differently by assigning additional head pointer P54 and tail pointer P55 assignments, where additional iterations of the exercising of integrated circuit under test 52 are performed by the operator/user. In the exemplary embodiment, at operation 76, in accordance with method 70, the user can end the operation of method 70, by deactivating program 41 and ending the design debugging session.
While the disclosure has been described with reference to an exemplary method and system embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the scope of the disclosure. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the disclosure without departing from the essential scope thereof. Therefore, it is intended that the disclosure not be limited to the particular exemplary embodiment disclosed as the best mode contemplated for carrying out this disclosure, but that the disclosure will include all embodiments falling within the scope of the appended claims.
