Patent Application
20240381790
Semiconductor device fabrication involves formation of memory stacks, which can be difficult to form and are often sensitive to etching processes, such as exposure to energetic species, and sensitive to oxidation, moisture, and additional exposure to energetic species after etching. As a result, some memory stacks undergo post-etching processes to address damage from etching and exposure to the environment, which may be followed by encapsulation of the memory stacks prior to subsequent processing. However, some methods of post-etching processing before encapsulation, and the corresponding apparatuses, may not be unable to sufficiently address the damage and exposures to the memory stacks and may further damage the memory stacks.
The background description provided herein is for the purposes of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
The systems, methods and devices of this disclosure each have several innovative aspects, no single one of which is solely responsible for the desirable attributes disclosed herein. Included among these aspects are at least the following implementations, although further implementations may be set forth in the detailed description or may be evident from the discussion provided herein.
In the following description, numerous specific details are set forth to provide a thorough understanding of the presented embodiments. The disclosed embodiments may be practiced without some or all of these specific details. In other instances, well-known process operations have not been described in detail to not unnecessarily obscure the disclosed embodiments. While the disclosed embodiments will be described in conjunction with the specific embodiments, it will be understood that it is not intended to limit the disclosed embodiments.
In this application, the terms “semiconductor wafer,” “wafer,” “substrate,” “wafer substrate,” and “partially fabricated integrated circuit” are used interchangeably. One of ordinary skill in the art would understand that the term “partially fabricated integrated circuit” can refer to a silicon wafer during any of many stages of integrated circuit fabrication thereon. A wafer or substrate used in the semiconductor device industry typically has a diameter of 200 mm, or 300 mm, or 450 mm. The following detailed description assumes the invention is implemented on a wafer. However, the invention is not so limited. The work piece may be of various shapes, sizes, and materials. In addition to semiconductor wafers, other work pieces that may take advantage of this invention include various articles such as printed circuit boards, magnetic recording media, magnetic recording sensors, mirrors, optical elements, micro-mechanical devices and the like.
Semiconductor fabrication processes often involve deposition of silicon nitride material. In one example, silicon nitride may be used in semiconductor device fabrication as diffusion barriers, gate insulators, sidewall spacers, and encapsulation layers. Conformal silicon nitride layers may also be used in other applications. For example, silicon nitride may be used during fabrication of memory structures. Some memory structures include metal oxide materials used for bit storage. However, as advanced memory structures are developed to accommodate smaller device sizes and improve efficiency, new challenges arise. Advanced memory architectures such as magnetoresistive random-access memory and phase change random-access memory (PCRAM) rely on new materials (other than metal oxides), such as chalcogenides, for bit storage.
In some memory devices, a chalcogenide, such as an ovonic threshold switching (OTS) chalcogenide, is present on the stack. The OTS and other chalcogenides may be sensitive to various gases and plasmas. In the case of PCRAM for example, the phase of a metal chalcogenide determines the bit state. Some example chalcogenides include sulfur (S), selenium (Se), and tellurium (Te). These new materials are air and moisture sensitive and may require encapsulation layers. When combined with appropriate metalloid ions such as germanium (Ge), antimony (Sb), etc., these chalcogenides form a phase change layer. In some cases, the memory device includes a germanium antimony tellurium (GST) material. If damaged, the chalcogenide may not function properly; for instance, the phase change layer may not change phases.
Using chalcogenides requires both depositing the chalcogenide and removing portions of the deposited chalcogenide from a wafer, such as removing some of the chalcogenide from within a trench or via, to create the desired structure. It is desirable to etch the chalcogenide within desirable nonuniformity tolerances, but without damaging and/or altering the composition of the chalcogenide material that is intended to remain on the wafer. However, removing some chalcogenides from a wafer poses unique and difficult challenges and considerations, and conventional etching is unable to remove some chalcogenides within desirable nonuniformity tolerances without damaging and/or altering the composition of the chalcogenide material.
Some of the conventional techniques for removing chalcogenides may also adversely affect the wafer. For example, reactive-ion etching (“RIE”) that uses a plasma sometimes results in poor etching uniformity as well as unwanted damage to the chalcogenide which can diminish its properties and prevent it from being an effective PCRAM. The plasma in RIE etching is also directional, not isotropic, thereby limiting its ability to etch in a direction perpendicular to the substrate surface preventing it from etching under shelves or overhangs. For instance, wafers may have “features” such as via or contact holes, which may be characterized by one or more of narrow and/or re-entrant openings, constrictions within the feature, and high aspect ratios One example of a feature is a hole or via in a semiconductor substrate or a layer on the substrate. Other examples include a trench in a substrate or layer, as well as overhangs or shelves that may require an etch in a location that may not be accessible with directional ions used in RIE etching.
Some processes that use RIE etching require performing post-etching operations, sometimes referred to as “clean” or “cleaning” operations, to remove at least some of the damaged chalcogenide material. However, these cleaning operations can reduce throughput, increase costs, further damage the wafer, and can be difficult to implement. Some such cleaning operations utilize a wet cleaning process in which a wafer is exposed to numerous liquid chemicals that remove the damaged chalcogenide material from the surface of the wafer. However, wet cleaning processes can damage the wafer in various manners. In some instances, the liquid chemicals themselves may change the composition of some chalcogenide materials, such as GST, which can further damage the chalcogenide. Additionally, the capillary forces exerted by the wet cleaning liquids on structures with chalcogenides, such as liquid within a trench or via, can cause the structure to collapse. Some wet cleaning processes may avoid this collapse by using surface modification reactants, but these reactants can remain on the surface of the chalcogenide and adversely affect the chalcogenide or other materials on the wafer. The amount of damage removal is also dependent on the selectivity of the damaged chalcogenide to the undamaged bulk chalcogenide, thereby increasing the challenge and difficult of removing the damaged chalcogenide.
Further, the liquids used in wet cleaning processes can be costly and require a complex liquid storage and delivery system that can be difficult to operate and maintain. Further, wet cleaning operations are performed at atmospheric pressure while many etching and post-etching processes, such as deposition of the encapsulation layer onto the etched chalcogenides, are performed at vacuum pressures. Wafers are therefore transferred from a vacuum environment in which the etching is performed, to atmospheric pressure for the wet cleaning, and then back to the vacuum environment for further post-etching processes. Transferring the wafer between vacuum and atmospheric environments increases processing time which decreases throughput, can lead to wafer defects through particle contamination, and can expose the etched chalcogenide material to air, oxygen, or N2, and therefore oxidize and damage the etched chalcogenide material. Wet cleaning operations are also generally performed in a separate chamber which, along with the complex liquid storage and delivery system, requires additional space in a fabrication environment, thereby enlarging the footprint of the semiconductor processing tool and preventing additional tools from being positioned in the facility and thereby decreasing overall throughput within the facility.
Provided herein are techniques and apparatuses for etching and further processing chalcogenide materials. The techniques use thermal etching, which may include thermal atomic layer etching, to perform the cleaning operations of the chalcogenide materials after RIE etching or other ion-based etching, instead of the wet cleaning operations, and/or to etch the bulk chalcogenide material instead of the RIE or other ion-based etching. This may include performing thermal etching on a single layer of chalcogenide material or multiple layers of chalcogenide in a stack of materials. As explained in greater detail below, thermal etching may modify a surface of a layer of chalcogenide material by flowing a first chemical species having a fluoride or a chloride onto the wafer to create a modified layer of chalcogenide material, and remove the modified layer of chalcogenide material, without using a plasma, by flowing a second chemical species comprising a compound with a center atom that is aluminum, boron, silicon, or germanium, and with at least one chlorine, onto the wafer.
Atomic layer etching (“ALE”) processes remove thin layers of material using sequential self-limiting reactions. Generally, an ALE cycle is the minimum set of operations used to perform an etch process one time, such as etching a monolayer. The result of one ALE cycle is that at least some of a film layer on a substrate surface is etched. Typically, an ALE cycle includes a modification operation to form a reactive layer, followed by a removal operation to remove or etch only this reactive layer. The cycle may include certain ancillary operations such as removing one of the reactants or byproducts, as well as a cleaning operation to remove residues that have built up on surfaces of the processing chamber. Generally, a cycle contains one instance of a unique sequence of operations.
As an example, an ALE cycle may include the following operations: (i) delivery of a first process gas that is a reactant gas, (ii) purging of the reactant gas from the chamber, (iii) delivery of a second process gas that is a removal gas and an optional plasma, and (iv) purging of the chamber. The modification operation (item (ii) above) generally forms a thin, reactive surface layer with a thickness less than the un-modified material, such as one, two, or three, atomic layers thick, for instance, or less than a whole atomic layer in one cycle.
The etching processes described herein may rely upon chemical reactions in conjunction with maintaining the substrate at a particular temperature or temperature range to drive chemical reactions in the modification and/or the removal operations which may be considered “thermal ALE” or “thermal etching”. In some embodiments, the thermal etching or thermal ALE may be considered an isotropic etch. In some embodiments, one or more layers of the substrate may be modified with chemical adsorption (hereinafter “chemisorption”), not with a plasma, while the substrate is maintained at a first temperature, after which the one or more modified layers of the substrate may be removed with desorption, not with a plasma, while the substrate is at a second temperature. Some implementations may optionally use a plasma during the modification operation and not during the removal operation. In some embodiments the first and second temperatures may be the same, while in some other embodiments they may be different than each other.
Chemisorption and desorption are temperature dependent chemical reactions that may occur in separate temperature regimes, may occur in partially overlapping temperature regimes, or may occur in the same temperature regime. Because of this, some of the thermal etching techniques described herein maintain the temperature of the substrate at the same, or substantially the same (e.g., within about 10% or 5% of each other), temperature during the modification and removal operations. Some other embodiments modulate the temperature of the substrate between the modification and removal operations in order to enable and utilize chemisorption that occurs at one temperature for the modification operation, and to enable and utilize desorption that occurs at a different temperature for the removal operation.
In some thermal etching processes provided herein, one or more surface layers of material are modified by chemisorption while the substrate is maintained at a first temperature; this may result in the creation of one or more modified surface layers of the substrate. The substrate includes layers of material and exposed surfaces that may be a uniform layer of material or may be a non-uniform layer that includes different molecules and elements. A first process gas with modifying molecules may be flowed onto the substrate that is maintained at the first temperature. In some embodiments, the modifying molecules may include a fluorine or a chlorine, as described below, in order to fluorinate or chlorinate molecules on the substrate. The first process gas may also include a carrier gas, such as N2, Ar, He, and Ne. This first temperature allows for chemisorption between the modifying molecules and at least some of the molecules in the exposed surface(s) of material.
The one or more modified surface layers may be removed while the substrate is maintained at the second temperature. In some embodiments, the second temperature alone may enable and cause desorption of the modified molecules from the substrate thereby removing the modified molecules from the substrate. In some other embodiments, a second process gas with removal molecules may be flowed onto the substrate, including onto the exposed surfaces of the substrate. The second process gas may also include a carrier gas as described above. These removal molecules may react with the modified molecules to form a different volatile molecule, which may be considered a volatized molecule. This volatized molecule may in turn be removed from the substrate by desorption when the substrate is at the second temperature. In some embodiments, this flowing of the second process gas may be part of the removal operation or may be a separate operation that occurs before, after, or during the heating of the substrate.
In some embodiments, thermal ALE may be isotropic and thus non-directional. In some other embodiments thermal ALE is not isotropic when directional ions are used in the etching process, such as during the modification operation.
Other thermal etching may be performed in which the modifying and removal molecules are at least co-flowed onto the substrate, and thus the modification and removal operations at least partially overlap. One or more process gases containing both modifying molecules and removal molecules may be simultaneously flowed onto the wafer during such processing. In many implementations of this thermal etching, the modifying molecules and the removal molecules have limited to no adverse reaction with each other, such that they may be co-flowed onto the substrate. In some instances, this co-flow may occur for all of the etching while in other instances, the co-flow may only occur for a part of the etching. In some examples having only partially overlapping flows, the modifying molecules may be flowed onto the substrate before the removal molecules are flowed onto the substrate, after which both the modifying molecules and the removal molecules may be simultaneously flowed onto the substrate. In some instances, the flow of both the modifying molecules and the removal molecules may stop at substantially the same time (e.g., within about 10% or 5% of each other) while in other instances, the flow of modifying molecules may stop and the removal molecules may be flowed onto the substrate.
The techniques provided herein may also deposit one or more encapsulation materials onto the etched chalcogenide. This may include depositing encapsulation material using chemical vapor deposition (“CVD”), plasma-enhanced CVD (“PECVD”), or atomic layer deposition (“ALD”) in a processing chamber separate from the processing chamber in which etching is performed. Some embodiments may transfer the wafer between these processing chambers without exposing the wafer to atmospheric pressure such that the wafer remains at a vacuum pressure in both processing chambers and during transfer between the processing chambers. In some embodiments, a layer of a first encapsulation material may be deposited on the etched chalcogenide while the wafer remains in the processing chamber in which etching is performed, and the first encapsulation material may include an aluminum, such as aluminum oxide. After the first encapsulation material is deposited, the wafer may be transferred to another processing chamber where additional encapsulation material is deposited on the wafer.
Aspects of this disclosure relate to thermal etching of one or more layers of chalcogenide material. As provided above, thermal etching processes rely upon chemical reactions in conjunction maintaining the substrate at a particular temperature or temperature range to drive chemical reactions in the modification and/or the removal operations. In some embodiments, the thermal etching or thermal ALE may be considered an isotropic etch, i.e., a non-directional etch. In some embodiments, one or more layers of the substrate may be modified with chemisorption, not with a plasma, while the substrate is maintained at a first temperature, after which the one or more modified layers of the substrate may be removed with desorption, not with a plasma, while the substrate is at a second temperature. Some implementations may optionally use a plasma during the modification operation and not during the removal operation. In some embodiments the first and second temperatures may be the same, while in some other embodiments they may be different than each other.
Some of the techniques described herein etch a chalcogenide material by performing a modification operation in which a first chemical species containing a fluorine, such as hydrogen fluoride, or a chlorine, such as hydrogen chloride, is flowed onto the wafer to modify the surface of a layer of the chalcogenide and form a modified layer of the chalcogenide material. The first chemical species having the fluoride or chloride may be considered the modifying molecules described herein. This modification converts a layer of the chalcogenide to a fluorinated chalcogenide or chlorinated chalcogenide. The modified layer of chalcogenide is reactive and can be removed by flowing a second chemical species containing a compound with a center atom that is aluminum, boron, silicon, or germanium, and with at least one chlorine, onto the wafer. The compound in the second chemical species reacts with the fluorinated chalcogenide or chlorinated chalcogenide to form volatile molecules that desorb from the wafer.
The chalcogenide may be any of those listed herein. In some implementations, the chalcogenide may be a phase change material, such as a germanium (Ge) antimony (Sb) tellurium (Te) (collectively “GST” or “GeSbTe”) material. This may also include n-doped GeSbTe compounds (N-GST), Sb2Te, and Sb2Te doped with Ag and In (AIST). As provided above, phase change materials are advantageous for use in forming memory devices because, for instance, the phase of a metal chalcogenide determines the bit state. In some embodiments, the chalcogenide may include those that do not change phase, such as an ovonic threshold switching (OTS) material which may include a compound with germanium, arsenic, and selenium (GeAsSe) or a compound containing germanium, antimony, selenium and nitrogen (GeSb,Se,N), for example.
In block 103, the wafer is heated to a first temperature which may be, as provided herein, considered both a specific temperature, or may be a temperature range. In some embodiments, the first temperature may be between about 20° C. and about 500° C., about 20° C. and about 150° C., about 20° C. and about 80° C., about 20° C. and about 100° C., about 100° C. and about 450° C., about 100° C. and about 400° C., about 150° C. and about 400° C., about 200° C. and about 600° C., about 200° C. and about 500° C., about 200° C. and about 350° C., or about 350° C. and about 500° C., for example. As discussed in more detail below, the wafer may be maintained at the first temperature during all, or substantially all (e.g., at least 80%, 90%, or 95%), of the etching, of the modification operation, and/or the removal operation.
In block 105, the layer of chalcogenide on the wafer is etched by modifying a surface of the layer of chalcogenide by flowing a first chemical species having a fluoride or a chloride onto the wafer and to create a layer of fluorinated chalcogenide or chlorinated chalcogenide, and removing the layer of fluorinated chalcogenide or chlorinated chalcogenide by flowing a second chemical species having a compound with a center atom that is aluminum, boron, silicon, or germanium, and with at least one chlorine. Some implementations may have separate modification and removal operations that may, in some instances, be separated by a purge operation. These implementations may be considered self-limited etching. Some other implementations may have at least partially overlapping modification and removal operations which may be performed, in some embodiments, by co-flowing the first species (i.e., the modifying molecules) and the second species (i.e., the removal molecules) onto the wafer.
The first chemical species having a fluoride may include one or more of the following non-limiting examples: a hydrogen fluoride, such as HF, a sulfur fluoride, such as sulfur tetrafluoride or sulfur hexafluoride or sulfuryl fluoride (SO2F2), a nitrogen fluoride such as nitrogen trifluoride, and a xenon fluoride, such as xenon difluoride. The first chemical species having a chlorine may include one or more of the following non-limiting examples: a hydrogen chloride, such as HCl, a sulfur chloride, such as sulfur dichloride or sulfur tetrachloride or sulfuryl chloride (SO2Cl2), or a nitrogen chloride such as trichloramine (NCl3). The use of a fluorine species or chlorine species, as opposed to other halogens or molecules, for modifying the surface of the layer of chalcogenide results in a unique reactive compound that enables and allows for the removal of all the chalcogenide when in the presence of the removal molecules because fluorine and chlorine bind very strongly to the surface and weaken the bonds to the underlayers. The first chemical species may be flowed in vapor form onto the wafer and may be flowed as a part of a process gas that may optionally include a carrier gas such as nitrogen, argon, helium, or neon, for instance.
The second chemical species having a compound with a center atom that is aluminum, boron, silicon, or germanium, and with at least one chlorine, may include various compounds. In some implementations, the compound may optionally include a hydrogen, a methyl group, or an ethyl group. For example, the compound may have an aluminum center atom along with a chlorine and a methyl group, such as dimethylaluminum chloride (DMAC), or trimethylaluminum (TMA) chloride. In another example, the compound may have a boron center along with multiple chlorides, such as boron trichloride (BCl3). In yet another example, the compound may have a silicon center along with multiple chlorides, such as silicon tetrachloride (SiCl4).
The compound of the second chemical species reacts with the fluorinated chalcogenide or chlorinated chalcogenide to cause its elements to become volatile and desorb from the wafer. For example, this exchange reaction is energetically favorable and therefore the fluorinated chalcogenide or chlorinated chalcogenide is able to form volatile compounds with the compound through, for example, transfer of chlorine, or through combining to form volatile germanium, antimony and tellurium compounds containing a combination of fluorides and chlorides. The second chemical species may also be flowed in vapor form onto the wafer and may be flowed as a part of a process gas that may be optionally include a carrier gas such as nitrogen, argon, helium, or neon, for instance.
In some embodiments, the etching of block 105 may be performed under various process conditions that enable such etching. In addition to the temperature ranges provided above, some implementations may maintain the substrate at a temperature between about 20° C. and about 500° C., about 20° C. and about 150° C., about 20° C. and about 80° C., about 20° C. and about 100° C., about 100° C. and about 450° C., about 100° C. and about 400° C., about 150° C. and about 400° C., about 200° C. and about 600° C., about 200° C. and about 500° C., about 200° C. and about 350° C., or about 350° C. and about 500° C., for example, during the etching. The etching may also be performed while the processing chamber is maintained at a pressure of between about 20 millitorr (mTorr) and 760 Torr (1 atm), including between about 20 mTorr and 600 mTorr, about 30 mTorr and 500 mTorr, and about 40 mTorr and 400 mTorr, as well as between about 3 Torr and 8 Torr, and about 4 Torr and 8 Torr, 2 Torr and 10 Torr, and 100 Torr and 760 Torr, for example. As discussed in more detail below, some implementations perform the etching of block 105 at substantially constant process conditions (e.g., with minor deviations, such as deviations of about 10% or 5% of the set conditions), while other implementations may vary one or more of the process conditions during the etching.
Some implementations may etch chalcogenide material using separate modification and removal operations.
Following block 203, a surface of the layer of chalcogenide is modified in block 205A, i.e., this block represents the modification operation. The layer of chalcogenide is modified as described above with respect to block 105 of
In some embodiments, an activation energy may be provided to assist with overcoming the activation barrier for the modifying molecule to adsorb on the wafer. This activation energy may be provided with thermal energy, radical energy, and/or UV photons, in some instances, which may include heating the wafer and/or generating a plasma or photons. This adsorption of the modifying molecule onto the first material may be considered chemical adsorption or “chemisorption” which is an energy dependent (e.g., a temperature dependent) chemical reaction. For some thermal etching techniques, this chemisorption during the modification operation may only occur at a particular temperature range that enables the activation barrier of the molecules in the layer of material and the incoming modifying molecules to be overcome which allows for dissociation and chemical bonding between these molecules and an adsorbate in the modifying molecule. Outside of this temperature range, the chemisorption may not occur, or may occur at undesirable (e.g., slow) rates.
Accordingly, some implementations of block 205A modify the surface layer of chalcogenide using only thermal activation energy, not a plasma. The first process gas is flowed onto the wafer that is maintained at the first temperature which provides the activation energy, and the chalcogenide is modified by chemisorption to from the modified layer of chalcogenide. The first temperature may be any temperature or temperature range provided herein, such as between about 20° C. and about 500° C., about 20° C. and about 150° C., about 20° C. and about 80° C., about 20° C. and about 100° C., about 100° C. and about 450° C., about 100° C. and about 400° C., about 150° C. and about 400° C., about 200° C. and about 600° C., about 200° C. and about 500° C., about 200° C. and about 350° C., or about 350° C. and about 500° C., for example. Additionally, the wafer may be maintained at the first temperature during all, or substantially all (e.g., at least 80%, 90%, or 95%), of the modification operation. The duration of the modification operation may be the duration for which modification of substantially all (e.g., at least 80%, 90%, or 95%) of desired exposed molecules on the substrate occurs. This may range from about 0.5 seconds to about 600 seconds, about 0.5 seconds to about 400 seconds, about 0.5 seconds to about 300 seconds, about 0.5 seconds to about 10 seconds, about 0.5 seconds to about 5 seconds, about 1 second to about 5 seconds, or about 5 seconds to about 300 seconds, for example.
In some implementations, ionic energy, such as from a plasma, may be used to drive the modification operation of block 205A. In some instances, a plasma may be ignited and a fluorine or a chlorine may react with the wafer or may be adsorbed onto the surface of the wafer. The species generated from a plasma can be generated directly by forming a plasma in the process chamber housing the wafer or they can be generated remotely in a process chamber that does not house the wafer, and can be supplied into the process chamber housing the wafer.
After the modification operation of block 205A, the modified chalcogenide, i.e., the fluorinated chalcogenide or chlorinated chalcogenide, is removed from the wafer in block 205B. This removal is performed as described above with respect to block 105 of
For desorption, a particular temperature range may enable the activation barrier of the modified molecule to be overcome which allows for the release of the modified layer from the wafer. In some examples, the temperature ranges at which chemisorption and desorption occur do not overlap while in others they may partially or fully overlap. Accordingly, in order to remove a molecule from a wafer using chemisorption and desorption, some implementations may maintain the wafer at the same, or substantially same (e.g., within about 1.0% or 5% of each other), temperature during the removal and modification operations. In order to remove a molecule from a wafer using chemisorption and desorption that occur in different temperature regimes, the modification operation of block 205A may occur in the first temperature range and the removal operation of block 205B may occur in the second different temperature range which may be higher or lower than the first temperature. Some such embodiments may perform multiple cycles to remove multiple layers of material by maintaining the wafer at the same, or substantially the same, temperature during the removal and modification operations, while other embodiments may repeatedly heat and cool the wafer between the two temperature regimes for chemisorption and desorption.
In some of the embodiments that use different temperature regimes, during or before block 205B, the temperature of the wafer may be brought to a second temperature that is different than the first temperature at which the wafer is maintained during the modification operation of block 205A. In some other embodiments, the second temperature is the same, or substantially the same (e.g., within about 10% or 5% of each other), temperature as the first temperature. This second temperature may be the temperature at which desorption occurs for the one or more modified surface layers. In some embodiments, the second temperature may be greater than the first temperature, and in these embodiments, block 205B may include heating the wafer from the first temperature to the second temperature. In some other embodiments, the second temperature may be less than the first temperature, and in these embodiments, the wafer may be actively cooled from the first temperature to the second temperature.
The wafer may be heated using radiant heating, convection heating, solid-to-solid heat transfer, or with a plasma. Additionally, the wafer top, bottom, or both, may be heated. The heating of the wafer may also occur in a non-linear fashion, in some embodiments, as discussed further below. As also described below, the wafer may be actively cooled in various manners. In some instances, a wafer may be heated to two different temperatures by positioning the wafer onto two separate substrate supports, such as heated pedestals, that are each maintained at a different temperature than each other. The wafer may therefore be heated to two different temperatures by being transferred between and placed at these two different substrate supports.
In block 205B, the one or more modified surface layers may be removed while the wafer is maintained at the second temperature. In some embodiments, the second temperature alone may enable and cause desorption of the modified molecules from the wafer thereby removing the modified molecules from the wafer.
In some embodiments, the second temperature may be between about 20° C. and about 500° C., about 20° C. and about 150° C., about 20° C. and about 80° C., about 20° C. and about 100° C., about 100° C. and about 450° C., about 100° C. and about 400° C., about 150° C. and about 400° C., about 200° C. and about 600° C., about 200° C. and about 500° C., about 200° C. and about 350° C., or about 350° C. and about 500° C., for example. Additionally, the wafer may be maintained at the temperature during all, or substantially all (e.g., at least 80%, 90%, or 95%), of the removal operation. The duration of the removal operation may be the duration for which desorption of substantially all (e.g., at least 80%, 90%, or 95%) of desired molecules on the wafer occurs. This may range from about 0.5 seconds to about 600 seconds, about 0.5 seconds to about 400 seconds, about 0.5 seconds to about 300 seconds, about 0.5 seconds to about 10 seconds, about 0.5 seconds to about 5 seconds, about 1 second to about 5 seconds, or about 5 seconds to about 300 seconds, for example.
The performance of blocks 205A and 205B may be considered a single thermal ALE cycle. In some implementations, these blocks 205A and 205B may be repeated in order to perform multiple cycles and remove an atomic monolayer, a sub-monolayer, as well as multiple layers of the chalcogenide. Some embodiments remove a fraction of a monolayer in one cycle as some etch rates may be lower than the lattice constant of the material that is being etched. This may include performing, for example, about 1 to about 1,000 cycles, about 1 to about 500 cycles, about 1 to about 100 cycles, about 1 cycle to about 30 cycles, or about 1 to about 20 cycles. Any suitable number of ALE cycles may be included to etch a desired amount of chalcogenide film. In some embodiments, ALE is performed in cycles to etch about 1. Angstroms (Å) to about 50 Å of the surface of the layers on the wafer. In some embodiments, cycles of ALE etch between about 2 Å and about 50 Å of the surface of the layers on the wafer. In some embodiments, each ALE cycle may etch at least about 0.1 Å, 0.5 Å, 1 Å, 2 Å, or 3 Å. As further illustrated in
In some operations, an optional purge operation of block 207 may be performed after the modification operation of block 205A and before the removal operation of block 205B. In a purge operation, non-surface-bound active modifying molecules, such as the fluorine species or chlorine species, and/or other residue or particulates, may be removed from the process chamber, the chamber walls, the chamber gas volume, and/or the substrate. This can be done by purging and/or evacuating the process chamber to remove the active species or other elements, without removing the adsorbed layer. The species generated in a plasma can be removed by stopping the plasma and allowing the remaining species to decay, optionally combined with purging and/or evacuation of the chamber. Purging can be done using any inert gas such as N2, Ar, Ne, He and their combinations. Purging may also be done after any operation, block, or step provided herein, including after a modification operation, after a removal operation, or both. Since the purging is optional, some implementations may not have any purging.
Some implementations vary the process conditions of the modifying and removal operations of blocks 205A and 205B, respectively, such as the duration, temperatures, and pressures of each operation. In some embodiments, blocks 205A and 205B may be performed for substantially the same about of time (e.g., within about 10% or 5% of each other), while in other embodiments they may be performed for different times. For example, block 205A may be performed for a time period shorter or longer than block 205B. The various time periods of each block may range, from about 0.5 seconds to about 500 seconds, about 0.5 seconds to about 400 seconds, about 0.5 seconds to about 300 seconds, about 0.5 seconds to about 10 seconds, about 0.5 seconds to about 5 seconds, about 1 second to about 5 seconds, or about 5 seconds to about 300 seconds, for example.
In some implementations, the modification operation of block 205A and the removal operation of block 205B may be performed at different pressures. For example, the modification operation of block 205A may be performed at a first pressure, or first pressure range, and the removal operation of block 205B may be performed at a second pressure, or second pressure range, different than the modification operation of block 205A. Although not depicted in
Some implementations of the described etching are further explained with
In diagrams 302a-302e a single layer of chalcogenide material is etched from a wafer. In 302a, the wafer is provided and it has one or more layers of chalcogenide, with each chalcogenide molecule represented as unshaded circles. The top layer of the chalcogenide may be considered a surface layer 306. In 302b, a first process gas with modifying molecules 308 (the solid black circles, some of which are identified with identifier 308) that include a fluoride or chloride is introduced to the wafer which modifies the chalcogenide surface layer 306 to form a fluorinated chalcogenide or a chlorinated chalcogenide. The schematic in 302b shows that some of the modifying molecules 308 are adsorbed onto the chalcogenide molecules 304 of the surface layer 306 to create a modified surface layer 310 that includes modified molecules 312 (one modified molecule 312 is identified inside a dotted ellipse in 302b). As stated above, the modifying molecules 308 may be a species having a fluorine, such as hydrogen fluoride, or a species having a chloride, such as hydrogen chloride. Additionally, the chalcogenide may be any of the materials provided herein, such as GeSbTe or OTS materials. For some thermal ALE techniques, this diagram 302b may occur while the wafer is maintained at the first temperature as described above, e.g., that enables chemisorption of the modifying molecule on the surface of the chalcogenide material. In some other implementations, this modification operation may be plasma assisted.
In diagram 302c, after the modified molecules 312 and the modified surface layer 310 have been created in 302b, the first process gas may be optionally purged from the chamber, as described above and represented in block 207 in
In diagram 302d, removal molecules 314 are introduced into the process chamber and in some embodiments, this may occur by flowing a second process gas having the second species, i.e., having the removal molecules 314, onto the wafer and the second species may include a compound with a center atom that is aluminum, boron, silicon, or germanium, and with at least one chlorine, such as DMAC. Schematic 302d further illustrates that the removal molecules 314, shown as a shaded diamond, react with the fluorinated chalcogenide or the chlorinated chalcogenide, i.e., the modified molecules 312, which causes the chalcogenide 304 and the fluoride 308 or chloride 308 to desorb from, and thus be removed from, the wafer. In some embodiments, the reaction between the removal molecules 314 and the modified molecules 312 causes the modifying molecules 308 to desorb from the wafer, and causes the removal molecules and the chalcogenide to form another compound 316, illustrated by a combination of the chalcogenide 304 unshaded circle and the removal molecule 314 shaded diamond, which desorbs from the wafer. In some other embodiments, not illustrated, the removal molecules and the modified molecules together form another compound that is caused to desorb from the wafer.
In some thermal ALE embodiments, this removal operation may be performed at a second temperature where desorption of the modified molecules 312 of the modified surface layer 310 from the wafer occurs; no plasma may be utilized in some of these removal operations. In some embodiments, the second temperature is the same, or substantially the same (e.g., within about 10% or 5% of each other), as the first temperature. In other embodiments, the first and second temperatures may be different than each other and, in these embodiments, the temperature may be changed from the first temperature to the second temperature by either heating or cooling the substrate. In some instances, the temperature in one or more of the operations may be ramped up.
In 302e, the modified molecules 312, and therefore the modified surface layer 310, have been removed from the wafer.
As noted above, some implementations may have at least partially overlapping flows of the modifying species and the removal species, such as overlapping flows of HF and BCl3, for instance.
In some embodiments, the modification operation of block 405A and the removal operation of block 405B overlap for only some of the etching. In other embodiments, these blocks 405A and 405B overlap for substantially all of the etching (e.g., within about 10% or 5% of each other); some of these implementations have the first and the second chemical species in the same process gas flowed onto the wafer, and some other implementations have these species in separate process gases that are co-flowed or simultaneously flowed onto the wafer.
In
In some embodiments, the temperature of the wafer may be adjusted during the etching illustrated in
Similarly, the wafer temperature may be increased or decreased during the modifying, the removing, or both. Referring to
Alternatively or additionally, the chamber pressure may be adjusted during the etching of
Similarly, the chamber pressure increase or decrease may be performed during the modifying, the removing, or both. Referring to
In
In some implementations, it may be advantageous to keep the first and second species separate until they enter the process chamber. This may avoid a cross reaction between the first and second species. The first and second species may therefore be flowed in separate lines and through separate ports into the processing chamber, such as through a dual-plenum showerhead or through separate nozzles, for instance. This may allow the two chemistries to meet only on the wafer surface.
In some embodiments, the temperature of the wafer may be adjusted during the etching illustrated in
Alternatively or additionally, the chamber pressure may be adjusted during the etching of
The modification and removal operations with overlapping flows is further illustrated in
Here, some of the modifying molecules 608 are adsorbed onto the chalcogenide molecules 604 of the surface layer 606 to create a modified surface layer 610 that includes modified molecules 612 (one modified molecule 612 is identified inside a dotted ellipse in 602b. As stated above, the modifying molecules 608 may include a fluorine, such as hydrogen fluoride, or a chlorine, such as hydrogen chloride. The removal molecules 614 are also co-flowed onto the wafer and the second species may include compound with a center atom that is aluminum, boron, silicon, or germanium, and with at least one chlorine as provided above. These removal molecules 614 react with the modified molecules 612 and the cause the chalcogenide to desorb from, and thus be removed from, the wafer. In some embodiments, the first species and the second species may be flowed separately into the processing chamber via separate gas lines and/or separate ports (e.g., separate injection nozzles or ports within the same showerhead).
In some embodiments, as the first species and the second species, e.g., the modifying molecules and the removal molecules, are flowed onto the wafer, additional layers of chalcogenide may be etched. For instance,
Diagram 602b may be considered an illustration of etching during simultaneous flows of the first and second species onto the wafer. As described above with respect to
Referring back to
In some of the embodiments provided here, the flow rate of the first process gas may remain constant and the flow rate of the second process gas may remain constant. In some other embodiments, the first and second process gases may be flowed at the same or different flow rates. In some other embodiments, it may be advantageous to vary the flow rate of the first and/or the second process gases. This may include, for instance, increasing the second process gas flowrate during the removal operation in order to provide more removal molecules as the removal operation progresses. Some example flow rates may include between about 50 sccm and 1000 sccm.
As provided above, the thermal etching provided herein may be used for various purposes. In some implementations, the thermal etching may be used for the cleaning operations of a chalcogenide after the chalcogenide has been etched using RIE etching or other ion-assisted etching. Additionally or alternatively, some implementations may perform the thermal etching to etch the bulk chalcogenide. In some such instances, the thermal etching may be used instead of the RIE etching or other ion-assisted etching.
Aspects of the thermal etching used as a cleaning operation after another etching process, such as the RIE or other ion-assisted etching, is performed on the chalcogenide will now be discussed.
As noted above, a cleaning operation that utilizes thermal etching, such as thermal ALE, may be performed on the chalcogenide after this RIE or other ion-assisted etching. Diagram 728c illustrates the chalcogenide 732 after the thermal etching cleaning operation has been performed. As shown, at least a part of the damaged and/or oxidized sidewall 733 of the chalcogenide 732 has been removed; this is represented by the chalcogenide 732 having straight sidewalls 733 that has a width 735B narrower than the width 735B in diagram 728b. In some implementations that use thermal ALE, the amount of chalcogenide 732 that is removed can be controlled on a cycle-by-cycle basis and therefore can remove the chalcogenide on a monolayer or sub-monolayer level. One or more cycles of thermal ALE can therefore be performed on the chalcogenide 732 in order to remove the desired amount of chalcogenide. In some embodiments, only some of the damaged and/or oxidized portion of the chalcogenide may be removed by thermal etching because some processing may have an acceptable amount of damaged and/or oxidized chalcogenide that can remain on the wafer. This may improve throughput by performing less etching on the wafer and thereby reducing the wafer's processing time. In some other implementations, substantially all of the damaged and/or oxidized portion of the chalcogenide and in some instances, additional layers of the bulk chalcogenide, may be removed.
Some implementations may further include depositing an encapsulation layer of material after the thermal etching has been performed on the chalcogenide. In some embodiments, as illustrated in diagram 728d of
As device and features size continue to shrink in the semiconductor industry, and also as 3D devices structures become more prevalent in integrated circuit (IC) design, the capability of depositing thin conformal films (films of material having a uniform thickness relative to the shape of the underlying structure, even if non-planar) continues to gain importance. ALD is a film forming technique which is well-suited to the deposition of conformal films due to the fact that a single cycle of ALD only deposits a single thin layer of material, the thickness being limited by the amount of one or more film precursor reactants which may adsorb onto the substrate surface (i.e., forming an adsorption-limited layer) prior to the film-forming chemical reaction itself. Multiple “ALD cycles” may then be used to build up a film of the desired thickness, and since each layer is thin and conformal, the resulting film substantially conforms to the shape of the underlying devices structure. In certain embodiments, each ALD cycle includes the following steps: (1) exposure of the substrate surface to a first precursor, (2) purge of the reaction chamber in which the substrate is located, activation of a reaction of the substrate surface, typically with a plasma and/or a second precursor, and purge of the reaction chamber in which the substrate is located.
Depositing a thin film via thermal ALD may include: heating the substrate to an elevated temperature, exposing the substrate to a precursor to adsorb onto a surface of the substrate, and exposing the substrate to one or more gas reactants to drive a surface reaction between the one or more gas reactants and the precursor, thereby forming the thin film via thermal ALD. Specifically, depositing the first silicon oxide layer via thermal ALD includes: heating the substrate to an elevated temperature, exposing the substrate to a silicon-containing precursor to adsorb onto a surface of the substrate, and exposing the substrate to an oxygen-containing reactant to drive a reaction between the oxygen-containing reactant and the silicon-containing precursor, thereby forming the first silicon oxide layer via thermal ALD.
The duration of each ALD cycle may typically be less than 25 seconds or less than 10 seconds or less than 5 seconds. The plasma exposure step (or steps) of the ALD cycle may be of a short duration, such as a duration of 1 second or less, for example. The plasma may be of other durations longer than that 1 second, such as 2 seconds, 5 seconds, or 10 seconds, for instance.
In some instances, the encapsulation material may include a silicon, such as a silicon nitride or a silicon oxide. In some implementations, the silicon-containing precursor includes a silane, such as an aminosilane. An aminosilane includes at least one nitrogen atom bonded to a silicon atom, but may also contain hydrogens, oxygens, halogens and carbons. Examples of aminosilanes may include bis(tert-butylamino)silane (BTBAS), N-(diethylaminosilyl)-N-ethylethanamine (SAM-24), tris(dimethylamino)silane (3DMAS), and tetrakis(dimethylamino)silane (4DMAS). In some embodiments, other materials may be deposited for the encapsulation layer. For example, encapsulation layers described herein may include Group IV element nitrides or carbides, any of which may be doped (such as with oxygen) or undoped. In various embodiments, the encapsulation layer may be any of the following chemistries or any of their combinations: silicon nitride (SiN), silicon carbide (SiC), oxygen-doped silicon carbide (SiCO), germanium nitride (GeN), germanium carbide (GeC), and oxygen-doped germanium carbide (GeCO).
In some implementations, operation 862 of
During an ALD cycle of
In some ALD processes that use a plasma to react the adsorbed precursor, the chamber pressure in the plasma processing chamber may be relatively low and between about 10 mTorr and about 200 mTorr, or may be relatively high and between about 1 Torr and about 7 Torr. An RF field is applied to the plasma processing chamber to generate ions and radicals of the oxygen-containing reactant. In various implementations, the RF frequency used to generate the plasma may be at least about 13.56 MHz, at least about 27 MHz, at least about 40 MHz, or at least about 60 MHz, though other frequencies may also be used. In some implementations, the RF power may be a few hundred Watts, for example about 500 W or less, about 400 W or less, or about 300 W or less, though it will be understood that other RF powers may be applied depending on substrate area. In some implementations, the duration of the plasma exposure phase may be between about 0.1 seconds and about 120 seconds or between about 1 second and about 60 seconds.
Additional etching techniques of a chalcogenide that may be used for cleaning operations after an RIE etching or other ion-assisted etching, as well as for etching the bulk chalcogenide material will now be discussed.
In some embodiments, the etching operations, including the thermal etching and thermal ALE, may be performed in one or more etching chambers while the encapsulation deposition is performed in another processing chamber, such as a deposition chamber that is configured to deposit material on a wafer. The wafer may therefore be transferred from the one or more etching chambers to the deposition processing chamber, as represented by optional block 913 in
For example, the one or more etching chambers and the deposition chamber may be maintained at a vacuum or other low pressure and the wafer may be transferred from the one or more etching chambers to the deposition chamber through one or more transfer chambers that are also maintained at vacuum or other low pressure. During this transfer, the wafer and the etched chalcogenide are not exposed to atmospheric pressure. Transferring the wafer in such a manner advantageously reduces the time that the etched chalcogenide is exposed to air, oxygen, or other environmental gases, thereby reducing or preventing unwanted oxidation of the chalcogenide; this transferring also advantageously increases throughput of the processed wafer by eliminating pump down steps and additional transfers that are performed when a wafer is transferred between vacuum and atmospheric pressures.
Transferring the wafer is further explained with
The tool 1000 also includes a wafer transfer unit is configured to transport one or more wafers within the tool 1000. For example, after a wafer has been etched in the first processing chamber 1002, the wafer transfer unit is able to transfer the wafer from the first processing chamber 1002, to the second processing chamber 1004 where thermal etching described herein may be performed on one or more wafers. Following this thermal etching in the second processing chamber 1004, the wafer transfer unit may transfer one or more wafers from the second processing chamber 1004 to the third processing chamber 1006 where one or more layers of encapsulation material may be deposited on one or more wafers.
In the depicted illustration of
The first and second wafer transfer modules may each be a vacuum transfer module (VTM). Airlock 1018, also known as a loadlock or transfer module, is shown and may be individually optimized to perform various fabrication processes. The tool 1000 also includes a pressure unit 1016 that is configured to lower the pressure of the tool 1000 to a vacuum or low pressure, e.g., between about 1 mTorr and about 10 Torr, and maintain the tool 1000 at this pressure. This includes maintaining the first, second and third processing chambers 1002-1006, the first wafer transfer module 1010, and the second wafer transfer module 1012 at the vacuum or low pressure.
As the wafer is transferred throughout the tool, it is able to be within an environment that is maintained at the vacuum or low pressure. For example, as the wafer is transferred from the first processing chamber 1002, into the first wafer transfer module 1010, to the second wafer transfer module 1014, to the second processing chamber 1004, the wafer is exposed to and maintained at the vacuum or low pressure, and therefore not exposed to atmospheric pressure. Similarly, as the wafer is transferred from the second processing module 1004, to the second wafer transfer module 1014, and to the third processing module 1006, the wafer is maintained at the vacuum or low pressure and not exposed to atmospheric pressure.
In a further example, a substrate is placed in one of the FOUPs 1024 and the front-end robot 1020 transfers the substrate from the FOUP 1024 to an aligner, which allows the substrate to be properly centered before it is etched, or deposited upon, or otherwise processed. After being aligned, the substrate is moved by the front-end robot 1020 into an airlock 1018. Because airlock modules have the ability to match the environment between an ATM and a VTM, the substrate is able to move between the two pressure environments without being damaged. From the airlock module 1018, the substrate is moved by the first robot arm unit 1008 through the first wafer transfer module 1010, or VTM 1010, and into the first processing chamber 1002. In order to achieve this substrate movement, the first robot arm unit 1008 uses end effectors on each of its arms.
In some of the implementations that use the tool 1000 of
In some embodiments, instead of using the RIE etching or other ion-assisted etching to remove the chalcogenide, thermal etching may be used to etch the bulk chalcogenide. The techniques for thermal etching of the bulk chalcogenide may be the same as provided above, such as in
In order to etch the bulk chalcogenide as well as to etch some of the damaged and/or oxidized chalcogenide, some of the thermal etching provided herein may include etching multiple layers, such as concurrently etching the multiple layers of chalcogenide. This may include multiple layers of chalcogenide located within stacks of material. For example, the wafer may have a plurality of trenches, holes, or vias that each have sidewalls with multiple layers of material and differing geometries. In order to form various devices, a chalcogenide material may be deposited into these trenches, holes, or vias and with the isotropic nature of the thermal etching described herein, the chalcogenide material can be etched within the various structures.
Etching multiple layers of chalcogenide material is illustrated in
Thermal etching of the bulk chalcogenide material 1158 may be performed in order to remove multiple layers of the chalcogenide material 1158, which includes concurrently etching multiple layers of this chalcogenide material 1158. Because the thermal etching is isotropic and non-directional, the thermal etching of the chalcogenide material 1158 is able to etch within each area, overhang, recess, and other geometric area of the feature 1152. In diagram 1128a, the thermal etching may remove multiple layers of the chalcogenide 1158 within the gap 1164 of the feature 1152 which may include layers of the bulk, monolithic chalcogenide 1158. Once the chalcogenide 1158 has been removed from the gap 1164, the chalcogenide may be present as discrete, separate portions of material within the various areas of the feature. For instance, in diagram 1128a, areas 1160A, 1160B, and 1160C that are encompassed within the dotted squares, have discrete portions of chalcogenide 1158 therein; directional etching, such as RIE etching, is unable to etch the chalcogenide within these areas. However, the thermal etching techniques are able to reach and etch each layer of the chalcogenide 1158 in these areas concurrently. In Figure diagram 1128b, the chalcogenide 1158 has been etched back in each of the areas, including etching multiple layers concurrently. In some instances, each portion of the chalcogenide 1158 in each area may be considered a layer of the chalcogenide 1158.
Similar to above, after the chalcogenide material 1158 has been etched, an encapsulation material 1162 (shown with dark shading) is deposited thereon with ALD as illustrated in diagram 1128c. Because ALD is a conformal deposition, the encapsulation material 1162 is able to be deposited on the various geometries in the feature 1152.
Various apparatuses may be used to perform thermal etching of the bulk chalcogenide. For example, in tool 1000 of
Tool 1200 also includes a wafer transfer unit configured to transport one or more wafers within the tool 1200. Additional features of tool 1200 will be discussed in greater detail below, and various features are discussed here with respect to some of the described techniques. In the depicted illustration, the wafer transfer unit includes a first robotic arm unit 1208 in a first wafer transfer module 1210 and a second robotic arm unit 1212 in a second wafer transfer module 1214 that may be considered an equipment front end module (EFEM) configured to received containers for wafers, such as a front opening unified module (FOUP) 1216. The first robotic arm unit 1208 is configured to transport a wafer between the first processing chamber 1202 and the second processing chamber 1204, and between the second the second robotic arm unit 1212. The second robotic arm unit 1212 is configured to transport the wafer between a FOUP and the first robotic arm unit 1208. After a wafer has been etched using thermal etching, such as thermal ALE, in the first processing chamber 1202, the wafer transfer unit is able to transfer the wafer from the first processing chamber 1202, to the second processing chamber 1204 where one or more layers of encapsulation material may be deposited on one or more wafers.
Similar to above, the first transfer module 1210 may a vacuum transfer module (VTM). Airlock 1220, also known as a loadlock or transfer module, is shown and may be individually optimized to perform various fabrication processes. The tool 1200 also includes a pressure unit 1216 that is configured to lower the pressure of the tool 1200 to a vacuum or low pressure, e.g., between about 1 mTorr and about 10 Torr, and maintain the tool 1200 at this pressure. This includes maintaining the first and second processing chambers 1202 and 1204, and the first wafer transfer module 1210 at the vacuum or low pressure. The second wafer transfer module 1214 may be at a different pressure, such as atmospheric. As the wafer is transferred throughout the tool 1200, it is therefore maintained at the vacuum or low pressure. For example, as the wafer is transferred from the first processing chamber 1202, into the first wafer transfer module 1210, and to the second processing chamber 1204, the wafer is maintained at the vacuum or low pressure and not exposed to atmospheric pressure.
In a further example, a substrate is placed in one of the FOUPs 1218 and the second robot arm unit 1212, or front-end robot, transfers the substrate from the FOUP 1218 to an aligner, which allows the substrate to be properly centered before it is etched, or deposited upon, or otherwise processed. After being aligned, the substrate is moved by the front-end robot 1212 into the airlock 1220. Because airlock modules have the ability to match the environment between an ATM and a VTM, the substrate is able to move between the two pressure environments without being damaged. From the airlock module 1220, the substrate is moved by the first robot arm unit 1208 through the first wafer transfer module 1210, or VTM 1210, and into the first processing chamber 1202. In order to achieve this substrate movement, the first robot arm unit 1208 uses end effectors on each of its arms.
Deposition of the encapsulation material may be performed in different manners, some of which are now described. Referring back to
In block 1315, a first encapsulation material is deposited on the wafer after the thermal etching and while the wafer remains in the etching chamber. This deposition may use one of the first or second chemical species used in the etching, along with one or more additional constituents in order to deposit the first encapsulation material. In some implementations, at least some of the process conditions may remain the same as those used in the etching, such as temperature of the wafer or pressure in the processing chamber. Some implementations may deposit a first encapsulation material that include an aluminum which may offer good protection of the underlying chalcogenide, such as GST. The first encapsulation material include, for instance, an aluminum oxide or an aluminum fluoride.
In one example, the etching of operation 1305 may include a second chemical species that includes DMAC. The deposition in operation 1315 may flow the second species having DMAC, and flow a third chemical species, such as water vapor, onto the wafer to deposit aluminum oxide. The water vapor and processing conditions cause the DMAC to be converted to aluminum oxide and further cause the aluminum oxide to be deposited via ALD onto the wafer. In another example, the second species may have TMA which is flowed onto the wafer with third chemical species, such as water vapor, onto the wafer to deposit aluminum oxide. The water vapor again converts the TMA to an aluminum oxide which is deposited via ALD onto the wafer. The activation energy for the deposition is provided by the thermal energy of wafer and processing chamber, not with a plasma. ALD deposition using thermal energy, not a plasma, may be considered thermal ALD. Accordingly, some implementations of block 1315 use thermal ALD to deposit the first encapsulation material.
After the deposition of the first encapsulation material in the chamber in which etching was performed, blocks 1313 and 1311 may be performed to transfer the wafer to the deposition processing chamber and perform further deposition therein.
In some embodiments, two different chalcogenides may be etched on the wafer.
After the etching of the block 1405, the wafer is transferred from the processing chamber to a deposition chamber in block 1407. This transferring may be the same as described above, such as with respect to block 913 of
After this deposition, the wafer may be transferred back to the processing chamber for further etching, as provided in block 1411. In some other embodiments, the wafer may be transferred to one or more other processing chambers for different processing, after which the wafer may be transferred to the processing chamber for etching. Once in the processing chamber, or etching chamber, the wafer is heated to the first temperature in block 1413, similar to block 1403, and the second layer chalcogenide is etched as provided in block 1415. In some embodiments, other RIE or other ion-assisted etching may be performed and the etching in block 1415 may be cleaning operations, while in other embodiments, the etching may be etching the bulk chalcogenide material.
The etching of block 1415 includes modifying a surface of the second chalcogenide with a first chemical species having a fluoride or chloride and thereby creating a first layer of fluorinated chalcogenide or chlorinated chalcogenide, and removing the second layer of fluorinated chalcogenide or chlorinated chalcogenide with a second chemical species containing a compound with a center atom that is aluminum, boron, silicon, or germanium, and with at least one chlorine. It will be understood that the etching of block 1415 may be performed in any manner provided herein, including as two shown in
In some embodiments, the first temperature, the first chemical species, and the second chemical species may be used to etch both the first chalcogenide material and the second chalcogenide material. In some other embodiments, one or more of these items may be different for etching the first and second chalcogenides. For example, the first species used for etching the first chalcogenide may include a fluorine while the first species used for etching the second chalcogenide may include a chlorine. In another example, the second species used for etching the first chalcogenide may include DMAC while the second species used for etching the second chalcogenide may include TMA.
After block 1415, the wafer may again be transferred from the processing chamber to the deposition chamber in block 1417 for another deposition of a second encapsulation material onto the wafer in block 1419. The encapsulation deposition may be the same as provided herein. In some embodiments, the encapsulation material deposited onto the first chalcogenide and the second chalcogenide may be the same, while in other embodiments they may differ.
The technique of
After this first encapsulation material 1536 is deposited, another etching process may be performed which etches the second chalcogenide 1540 as shown in diagram 1528d and described above with respect to blocks 1413 and 1415. The etching is also illustrated as a reduction of the width 1527A of the second chalcogenide material 1540 between diagram 1528c and 1528d where the width 1527B is smaller. A second encapsulation layer 1542 is then deposited on the etched second chalcogenide material 1540 and in some instances, as illustrated in diagram 1528e, on the first encapsulation material 1536. The second encapsulation material 1442 is depicted with shading having a dotted boundary line. Diagram 1528e corresponds with block 1419 of
The techniques and apparatuses described herein provide numerous benefits and advantages. For example, using thermal etching to perform cleaning operations after RIE etching or other ion-based etching allows the wet cleaning operations to be omitted which provides numerous benefits. Some such benefits include not having the wafer transferred from a vacuum environment, to atmosphere for the wet cleaning, and back to the vacuum environment thereby retaining the wafer at vacuum, preventing or reducing unwanted oxidization of the chalcogenide, and improving wafer throughput by decreasing processing time. Further, the liquid delivery system for the wet cleaning operations is not needed for the apparatus which reduces the tool's footprint, reduces maintenance of the system, and reduces costs by not requiring such system and liquids. Additional benefits also include reducing or eliminating damage that may be caused to the chalcogenide and wafer by the wet cleaning operations, such as structure collapse from the liquid surface tension, and no surface modification reactants are needed.
The thermal techniques provided herein may also enable etching on a monolayer or sub-monolayer scale to remove precise amounts of chalcogenide and therefore provide uniform etching. As described above, because these thermal etching techniques are isotropic, complex geometries may be etched without requiring a line of sight or directional etching.
The apparatuses provided herein also reduce complexity and increase wafer throughput by being able to process wafers, including etching and depositing encapsulation material in multi-station chambers.
The present disclosure includes the apparatuses provided above and herein below. Referring now to
The process gas unit 1624 is configured to flow process gases, which may include liquids and/or gases, such as a reactant, modifying molecules, converting molecules, or removal molecules, onto a substrate 1634 in the chamber interior 1632. The process gas unit 1624 also includes one or more flow features 1642 configured to flow the first process gas onto the substrate 1634, such as a hole, a nozzle (two of which are depicted), or a showerhead. The one or more flow features 1642 may be positioned above, below, on the side, or a combination of positions, within the chamber interior 1632, such as on the processing chamber walls, top, and bottom, for instance. The process gas unit 1624 may include a mixing vessel for blending and/or conditioning process gases for delivery to the chamber interior 1632. One or more mixing vessel inlet valves may control introduction of process gases to the mixing vessel.
The process gas unit 1624 may include a first process gas source 1636, a first process liquid source 1638, a vaporization point (not depicted) which may vaporize the first liquid into a gas, and a carrier gas source 1640. Some reactants may be stored in liquid form prior to vaporization and subsequent to delivery to the process chamber 1622. The first process gas may comprise a chlorine or a fluorine configured to modify one or more layers of material on the substrate, without using a plasma, in some embodiments; the second process gas may comprise a compound with a center atom that is aluminum, boron, silicon, or germanium, and with at least one chlorine, onto the wafer in the second processing chamber as described above.
In some implementations, the vaporization point may be a heated liquid injection module. In some other implementations, the vaporization point may be a heated vaporizer. In some other embodiments, the vapor may be generated by drawing a vacuum above a container containing the liquid reagent. In yet other implementations, the vaporization point may be eliminated from the process station. In some implementations, a liquid flow controller (LFC) upstream of the vaporization point may be provided for controlling a mass flow of liquid for vaporization and delivery to the chamber interior 1632. The carrier gas source 1640 includes one or more carrier gases or liquids that may be flowed with the processing gas; these may be inert gases like N2, Ar, Ne, He. The apparatus 1620 may also include a vacuum pump 1633 configured to pump the chamber interior to low pressures, such as a vacuum having a pressure of 1 mTorr or 10 Torr, for example.
The chamber interior 1632 includes substrate support features 1635 that are configured to support and thermally float a substrate 1634 in the chamber. The substrate support features 1635 may include clamps, horizontal pins or supports, vertical pins or supports, and semi-circular rings, for instance, that support the substrate 1634 in the chamber interior 1632. These features are configured to support the substrate 1634 such that the thermal mass of the substrate 1634 is reduced as much as possible to the thermal mass of just the substrate. Each substrate support feature 1635 may therefore have minimal contact with the substrate 1634 and may be the smallest number of features required to adequately support the substrate during processing (e.g., in order to support the weight of the substrate and prevent inelastic deformation of the substrate). For instance, the surface area of one substrate support feature 1635 in contact with a substrate may be less than about 1%, 0.5%, 0.1%, 0.05%, or 0.01% of the overall surface area of the back side of the substrate; also, for instance, 2, 3, or 4 features may be utilized.
In one example, the support features 1635 may include two or more vertical pins that have grooves wrapped or spiraled along the vertical, longitudinal axis and that are offset at varying distances from the longitudinal axis and configured to support a substrate. When the vertical pin rotates along its longitudinal axis and the edge of a substrate is positioned in the groove, the edge of the groove, and therefore the edge of the substrate, moves farther away from the longitudinal axis. When multiple vertical pins are used to support a substrate, the rotation of the vertical pins causes the grooves to apply a supporting force to the substrate in a direction perpendicular to the longitudinal axis.
In some embodiments, the chamber 1622 may include a wafer support pedestal that includes substrate lift pins. During thermal ALE processing, the lift pins may support and position the substrate away from the pedestal such that there is substantially no transference of thermal energy between the pedestal and substrate (e.g., less than 10%, 5%, 1%, 0.5%, or 0.1% of energy transferred between the two). In some other embodiments, the chamber 1622 may not have a pedestal. In some embodiments, an electrostatic chuck (ESC) may be used that contains substrate heating unit 1626 configured to heat the substrate to temperatures provided herein, such as between about 20° C. and 500° C.
The substrate heating unit 1626 is configured to heat the substrate to multiple temperatures and maintain such temperatures for at least 1 second, 5 seconds, 10 seconds, 30 seconds, 1 minute, 2 minutes, or 3 minutes, for example. In some embodiments, the substrate heating unit 1626 is configured to heat the substrate between at least two temperature ranges, with the first range between about 20° C. and 150° C., and the second range between about 200° C. and 600° C., as well as configured to maintain the substrate at a temperature within these ranges for at least 1 second, 5 seconds, or 10 seconds, for example. Additionally, in some embodiments, the substrate heating unit 1626 is configured to heat the substrate from the first temperature range to the second temperature range in less than about 250 milliseconds, 150 milliseconds, 100 milliseconds, or 50 milliseconds, for instance.
The substrate heating unit 1626 may utilize radiant heating, convective heating, laser heating, plasma heating, solid-to-solid thermal transference (e.g., transferring heat generated by one or more heating elements in a heated electrostatic chuck or pedestal to a substrate supported by or on that chuck or pedestal), or a combination of these items. For radiant heating, the substrate heating unit 1626 may be used for emitted light heating, ultraviolet heating, microwave heating, radio frequency heating, and induction heating. For example, the substrate heating unit 1626 may include light emitting diodes (LEDs) that emit visible light with wavelengths that may include and range between 400 nanometers (nm) and 800 nm. This may also include, for instance, a heat lamp, light emitting diodes (e.g., LEDs), a ceramic heater, a quartz heater, or a plurality of Gradient Index (GRIN) Lenses connected to a light energy source. A GRIN lens is configured to deliver heat energy (thermal or light) from the light energy source to the substrate in a uniform manner; the light source may be a laser or high-intensity light source that transmits the heat energy through a conduit, such as a fiber optic cable, to the GRIN lenses. The heating elements utilized by the substrate heating unit 1626 may be positioned above, below, on the side, or a combination of the positions, the substrate 1634, and they may be positioned inside, outside, or both, the chamber interior 1632. In
For solid-to-solid thermal transference, the substrate heating unit 1626 may have one or more heating surfaces that are configured to contact and heat the substrate in the chamber interior. In some embodiments, the substrate heating unit 1626 may have a heating platen, such as a flat surface or a surface of a substrate pedestal, that is configured to contact the back surface of the substrate and heat the substrate. This heating platen may have heating elements such as a heating coil, heating fluid, or radiative heating discussed above, that may heat the surface of the heating platen. The substrate may be heated when the back of the substrate is in direct contact with, or is offset from the heating platen but close enough to receive thermal energy from, the heating platen. When using this solid-to-solid thermal transference to heat the substrate, the substrate is separated from the heating platen when it is cooled. While some conventional ALE apparatuses may have a substrate pedestal that includes both heating and cooling elements, these apparatuses are unable to quickly (e.g., under 250 milliseconds) cycle between the temperatures of thermal ALE because of the large thermal masses of the pedestal that are repeatedly heated and cooled. For instance, it may take multiple seconds or minutes to heat a pedestal from a first temperature range (e.g., 20° C. to 100° C.) to a second temperature range (e.g., 200° C. to 500° C.), as well as to cool the pedestal from the second temperature range to a lower temperature that can cool the substrate to the first temperature range. Accordingly, after using this solid-to-solid heating technique, the heating platen and the substrate are separated from each other which may be accomplished, for instance, by moving the substrate and/or the heating platen away from each other. Without this separation, cooling occurs of both the thermal mass of the substrate and the heating platen which increases the cooling time which decreases substrate throughput. In some embodiments, an ESC or pedestal having the substrate heating unit and a Peltier element for cooling may enable fast heating and cooling times (such as about 30 seconds to cool a substrate to a desired temperature). In some embodiments, this may be performed at low pressures, such as less then 1 Torr, including less than 50 mTorr, for example.
The substrate cooling unit 1628 of
Various factors may increase the ability of the cooling fluid to cool the substrate. It has been discovered through various experiments that the higher the flow rate of the cooling fluid, the faster the substrate is cooled. In one example experiment, a cooling gas at about −196° C. flowed onto a substrate at a flow rate of 1 liter per second was found to reduce the temperature of a substrate from about 220° C. to about 215° C. in about 5,000 milliseconds, while the same cooling gas a flow rate of 10 liters per second reduced the temperature of a substrate from about 220° C. to about 195° C. in about 5,000 milliseconds. It was also discovered that a gap (1786 in
In some embodiments, the substrate cooling unit 1628 may use solid-to-solid thermal transference to actively cool the substrate 1634. In some of these embodiments, a cooling platen, such as a flat, cooled surface may be used to contact the bottom of the substrate and cool the substrate. This platen may be cooled by flowing a cooling fluid on, through, or underneath the platen. When using this solid-to-solid cooling, similar to the solid-to-solid heating discussed above, the substrate is separated from the cooling platen during heating of the substrate, such as by moving the substrate away from the cooling platen by, for instance, raising it up with lift pins. Without this separation, both the thermal masses of the substrate and cooling platen are cooled which requires more cooling that in turn increases process time and decreases throughput. In some embodiments, radiant heating of the top of the substrate or plasma heating of the bottom of the substrate may be used in conjunction with solid-to-solid cooling.
In some embodiments, the substrate cooling unit 1628 may use laser cooling to cool the substrate. This may enable the cooling of a substrate that includes thulium molecules on at least the exposed surface of the substrate by utilizing a reverse Navier-Stokes reaction. For example, the temperature of the substrate manifests itself in phonons and the laser cooling emits photons to the substrate surface which interact with and pick-up phonons in the thulium, and then leave the substrate with the phonon from the thulium at a higher energy level. The removal of these phonons causes a decrease in the temperature of the substrate. The thulium may be doped onto the surface of the substrate in order to enable this laser cooling, and this doping may be incorporated into the techniques listed above, such as occurring after or before any operation, such as the removal operation.
As noted above, some embodiments of the apparatus may include a plasma source configured to generate a plasma within the chamber interior. These plasma sources may be a capacitively coupled plasma (CCP), an inductively coupled plasma (ICP), an upper remote plasma, and a lower remote plasma.
In some embodiments, the apparatuses described herein may include a controller that is configured to control various aspects of the apparatus in order to perform the techniques described herein. For example, in
In some implementations, the controller 1666 is part of an apparatus or a system, which may be part of the above-described examples. Such systems or apparatuses can include semiconductor processing equipment, including a processing tool or tools, chamber or chambers, a platform or platforms for processing, and/or specific processing components (a gas flow system, a substrate heating unit, a substrate cooling unit, etc.). These systems may be integrated with electronics for controlling their operation before, during, and after processing of a semiconductor wafer or substrate. The electronics may be referred to as the “controller,” which may control various components or subparts of the system or systems. The controller 1666, depending on the processing parameters and/or the type of system, may be programmed to control any of the processes disclosed herein, including the delivery of processing gases, temperature settings (e.g., heating and/or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, positional and operation settings, wafer transfers into and out of a tool and other transfer tools and/or load locks connected to or interfaced with a specific system.
Broadly speaking, the controller 1666 may be defined as electronics having various integrated circuits, logic, memory, and/or software that receive instructions, issue instructions, control operation, enable cleaning operations, enable endpoint measurements, and the like. The integrated circuits may include chips in the form of firmware that store program instructions, digital signal processors (DSPs), chips defined as application specific integrated circuits (ASICs), and/or one or more microprocessors, or microcontrollers that execute program instructions (e.g., software). Program instructions may be instructions communicated to the controller in the form of various individual settings (or program files), defining operational parameters for carrying out a particular process on or for a semiconductor wafer or to a system. The operational parameters may, in some embodiments, be part of a recipe defined by process engineers to accomplish one or more processing operations during the fabrication of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and/or dies of a wafer.
The controller 1666, in some implementations, may be a part of or coupled to a computer that is integrated with, coupled to the system, otherwise networked to the system, or a combination thereof. For example, the controller may be in the “cloud” or all or a part of a fab host computer system, which can allow for remote access of the wafer processing. The computer may enable remote access to the system to monitor current progress of fabrication operations, examine a history of past fabrication operations, examine trends or performance metrics from a plurality of fabrication operations, to change parameters of current processing, to set processing operations to follow a current processing, or to start a new process. In some examples, a remote computer (e.g. a server) can provide process recipes to a system over a network, which may include a local network or the Internet. The remote computer may include a user interface that enables entry or programming of parameters and/or settings, which are then communicated to the system from the remote computer. In some examples, the controller 1666 receives instructions in the form of data, which specify parameters for each of the processing operations to be performed during one or more operations. It should be understood that the parameters may be specific to the type of process to be performed and the type of tool that the controller is configured to interface with or control. Thus as described above, the controller 1666 may be distributed, such as by comprising one or more discrete controllers that are networked together and working towards a common purpose, such as the processes and controls described herein. An example of a distributed controller for such purposes would be one or more integrated circuits on a chamber in communication with one or more integrated circuits located remotely (such as at the platform level or as part of a remote computer) that combine to control a process on the chamber.
As noted above, depending on the process operation or operations to be performed by the apparatus, the controller 1666 might communicate with one or more of other apparatus circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, neighboring tools, tools located throughout a factory, a main computer, another controller, or tools used in material transport that bring containers of wafers to and from tool locations and/or load ports in a semiconductor manufacturing factory.
As also stated above, the controller is configured to perform any technique described above. For instance, referring to apparatus 1620 of
As noted above, some etching performed herein may be temperature controlled features of the processing chamber, such as its side walls, top, and/or bottom, as well as the showerhead and gas delivery system.
The processing chamber 1702 includes sides walls 1712A, a top 1712B, and a bottom 1712C, that at least partially define the chamber interior 1714, which may be considered a plenum volume. As stated herein, it may be desirable in some embodiments to actively control the temperature of the processing chamber walls 1712A, top 1712B, and bottom 1712C in order to prevent unwanted condensation on their surfaces. Some emerging semiconductor processing operations flow vapors, such as water and/or alcohol vapor, onto the substrate which adsorb onto the substrate, but they may also undesirably adsorb onto the chamber's interior surfaces. This can lead to unwanted deposition and etching on the chamber interior surfaces which can damage the chamber surfaces and cause particulates to flake off onto the substrate thereby causing substrate defects. In order to reduce and prevent unwanted condensation on the chamber's interior surfaces, the temperature of chamber's walls, top, and bottom may be maintained at a temperature at which condensation of chemistries used in the processing operations does not occur.
This active temperature control of the chamber's surfaces may be achieved by using heaters to heat the chamber walls 1712A, the top 1712B, and the bottom 1712C. As illustrated in
The chamber walls 1712A, top 1712B, and bottom 1712C, may also be comprised of various materials that can withstand the chemistries used in the processing techniques. These chamber materials may include, for example, an aluminum, anodized aluminum, aluminum with a polymer, such as a plastic, a metal or metal alloy with a yttria coating, a metal or metal alloy with a zirconia coating, and a metal or metal alloy with aluminum oxide coating; in some instances the materials of the coatings may be blended or layers of differing material combinations, such as alternating layers of aluminum oxide and yttria, or aluminum oxide and zirconia. These materials are configured to withstand the chemistries used in the processing techniques, such as anhydrous HF, water vapor, methanol, isopropyl alcohol, chlorine, fluorine gases, nitrogen gas, hydrogen gas, helium gas, and the mixtures thereof.
The apparatus 1700 may also be configured to perform processing operations at or near a vacuum, such as at a pressure of about 0.1 Torr to about 100 Torr, or about 20 Torr to about 200 Torr, or about 0.1 Torr to about 10 Torr. This may include a vacuum pump 1784 configured to pump the chamber interior 1714 to low pressures, such as a vacuum having a pressure of about 0.1 Torr to about 100 Torr, including about 0.1 Torr to about 10 Torr, and about 20 Torr to about 200 Torr, or about 0.1 Torr to about 10 Torr.
Various features of the pedestal 1704 will now be discussed. The pedestal 1704 includes a heater 1722 (encompassed by the dashed rectangle in
The heater's plurality of LEDs may be arranged, electrically connected, and electrically controlled in various manners. Each LED may be configured to emit a visible blue light and/or a visible white light. In certain embodiments, white light (produced using a range of wavelengths in the visible portion of the EM spectrum) is used. In some semiconductor processing operations, white light can reduce or prevent unwanted thin film interference. For instance, some substrates have backside films that reflect different light wavelengths in various amounts, thereby creating an uneven and potentially inefficient heating. Using white light can reduce this unwanted reflection variation by averaging out the thin film interference over the broad visible spectrum provided by white light. In some instances, depending on the material on the back face of the substrate, it may be advantageous to use a visible non-white light, such as a blue light having a 450 nm wavelength, for example, in order to provide a single or narrow band of wavelength which may provide more efficient, powerful, and direct heating of some substrates that may absorb the narrow band wavelength better than white light.
Various types of LED may be employed. Examples include a chip on board (COB) LED or a surface mounted diode (SMD) LED. For SMD LEDs, the LED chip may be fused to a printed circuit board (PCB) that may have multiple electrical contacts allowing for the control of each diode on the chip. For example, a single SMD chip is typically limited to having three diodes (e.g., red, blue, or green) that can be individually controllable to create different colors, for instance. SMD LED chips may range in size, such as 2.8×2.5 mm, 3.0×3.0 mm, 3.5×2.8 mm, 5.0×5.0 mm, and 5.6×3.0 mm. For COB LEDs, each chip can have more than three diodes, such as nine, 12, tens, hundreds or more, printed on the same PCB. COB LED chips typically have one circuit and two contacts regardless of the number of diodes, thereby providing a simple design and efficient single color application. The ability and performance of LEDs to heat the substrate may be measured by the watts of heat emitted by each LED; these watts of heat may directly contribute to heating the substrate.
In some embodiments, the plurality of LEDs may include at least about 1,000 LEDs, including about 1,200, 1,500, 2,000, 3,000, 4,000, 5,000, or more than 6,000, for instance. Each LED may, in some instances, be configured to uses 4 watts or less at 100% power, including 3 watts at 100% power and 1 watt at 100% power. These LEDs may be arranged and electrically connected into individually controllable zones to enable temperature adjustment and fine tuning across the substrate. In some instances, the LEDs may be grouped into at least 20, for instance, independently controllable zones, including at least about 25, 50, 75, 80, 85 90, 95, or 100 zones, for instance. These zones may allow for temperature adjustments in the radial and azimuthal (i.e., angular) directions. These zones can be arranged in a defined pattern, such as a rectangular grid, a hexagonal grid, or other suitable pattern for generating a temperature profile as desired. The zones may also have varying shapes, such as square, trapezoidal, rectangular, triangular, obround, elliptical, circular, annular (e.g., a ring), partially annular (i.e., an annular sector), an arc, a segment, and a sector that may be centered on the center of the heater and have a radius less than or equal to the overall radius of the substrate heater's PCB. These zones are able to adjust the temperature at numerous locations across the wafer in order to create a more even temperature distribution as well as desired temperature profiles, such as higher temperatures around the edge of the substrate than in the center of the substrate. The independent control of these zones may also include the ability to control the power output of each zone. For example, each zone may have at least 15, 20, or 25 adjustable power outputs. In some instances, each zone may have one LED thereby enabling each LED to be individually controlled and adjusted which can lead to a more uniform heating profile on the substrate. Accordingly, in some embodiments, each LED of the plurality of LEDs in the substrate heater may be individually controllable.
In certain embodiments, the substrate heater 1722 is configured to heat the substrate to multiple temperatures and maintain each such temperatures for various durations. These durations may include the following non-limiting examples of at least about 1 second, at least about 5 seconds, at least about 10 seconds, at least about 30 seconds, at least about 60 seconds, at least about 90 seconds, at least about 120 second, at least about 150 seconds, or at least about 180 seconds. The substrate heater may be configured to heat the substrate to between about 50° C. and 600° C., including between about 50° C. and 150° C., including about 130° C., or between about 150° C. and 350° C., for example. The substrate heater may be configured to maintain the substrate at a temperature within these ranges for various durations, including the following non-limiting examples: at least about 1 second, at least about 5 seconds, at least about 10 seconds, at least about 30 seconds, at least about 60 seconds, at least about 90 seconds, at least about 120 seconds, at least about 150 seconds, or at least about 180 seconds, for example. Additionally, in some embodiments, the substrate heater 1722 is configured to heat the substrate to any temperature within these ranges in less than about 60 seconds, less than about 45 seconds, less than about 30 seconds, or less than about 15 seconds, for instance. In certain embodiments, the substrate heater 1722 is configured to heat a substrate at one or more heating rates, such as between at least about 0.1° C./second and at least about 20° C./second, for example.
The substrate heater may increase the temperature of the substrate by causing the LEDs to emit the visible light at one or more power levels, including at least about 80%, at least about 90%, at least about 95%, or at least about 100% power. In some embodiments, the substrate heater is configured to emit between about 10 W and 4000 W, including at least about 10 W, at least about 30 W, at least about 0.3 kilowatt (kW), at least about 0.5 kW, at least about 2 kW, at least about 3 kW, or at least about 4 kw. The apparatus is configured to supply between about 0.1 kw and 9 kW of power to the pedestal; the power supply is connected to the substrate heater through the pedestal but is not depicted in the Figures. During temperature ramps, the substrate heater may operate at the high powers, and may operate at the lower power levels (e.g., include between about 5 W and about 0.5 kW) to maintain the temperature of a heated substrate.
In some embodiments, the substrate heater may also include a pedestal cooler that is thermally connected to the LEDs such that heat generated by the plurality of LEDs can be transferred from the LEDs to the pedestal cooler. This thermal connection is such that heat can be conducted from the plurality of LEDs to the pedestal cooler along one or more heat flow pathways between these components. In some instances, the pedestal cooler is in direct contact with one or more elements of the substrate heater, while in other instances other conductive elements, such as thermally conductive plates (e.g., that comprise a metal) are interposed between the substrate heater and the pedestal cooler. Referring back to
As provided herein, it may be advantageous to actively heat the exterior surfaces of the processing chamber 1702. In some instances, it may similarly be advantageous to heat the exterior surfaces of the pedestal 1704 in order to prevent unwanted condensation and deposition on its external surfaces. As illustrated in
The pedestal may also include a window to protect the substrate heater, including the plurality of LEDs, from damage caused by exposure to the processing chemistries and pressures used during processing operations. As illustrated in
As shown in
The pedestal 1704 is therefore configured, in some embodiments, to support the substrate 1718 by thermally floating, or thermally isolating, the substrate within the chamber interior 1714. The pedestal's 1704 plurality of substrate supports 1708 are configured to support the substrate 1718 such that the thermal mass of the substrate 1718 is reduced as much as possible to the thermal mass of just the substrate 1718. Each substrate support 1708 may have a substrate support surface 1720 that provides minimal contact with the substrate 1718. The number of substrate supports 1708 may range from at least 3 to, for example, at least 6 or more. The surface area of the support surfaces 1720 may also be the minimum area required to adequately support the substrate during processing operations (e.g., in order to support the weight of the substrate and prevent inelastic deformation of the substrate). In some embodiments, the surface area of one support surface 1720 may be less than about 0.1%, less than about 0.075%, less than about 0.05%, less than about 0.025%, or less than about 0.01%, for instance.
The substrate supports are also configured to prevent the substrate from being in contact with other elements of the pedestal, including the pedestal's surfaces and features underneath the substrate. The substrate 1718 is also offset from the substrate heater 1722 (as measured in some instances from a top surface of the substrate heater 1722 which may be the top surface of the LEDs 1724) by a distance which may affect numerous aspects of heating the substrate 1718.
As stated, the substrate supports 1708 are configured to support the substrate 1718 above the window. In some embodiments, these substrate supports are stationary and fixed in position; they may not be lift pins or a support ring. In some embodiments, at least a part of each substrate support 1708 that includes the support surface 1720 may be comprised of a material that is transparent at least to light emitted by LEDs 1724. This material may be, in some instances, quartz or sapphire. The transparency of these substrate supports 1708 may enable the visible light emitted by the substrate heater's 1722 LEDs to pass through the substrate support 1708 and to the substrate 1718 so that the substrate support 1708 does not block this light and the substrate 1718 can be heated in the areas where it is supported. This may provide a more uniform heating of the substrate 1718 than with a substrate support comprising a material opaque to visible light. In some other embodiments, the substrate supports 1708 may be comprised of a non-transparent material, such as zirconium dioxide (ZrO2).
Referring back to
The gas distribution unit 1710 is configured to flow process gases, which may include liquids and/or gases, such as a reactant, modifying molecules, converting molecules, or removal molecules, onto the substrate 1718 in the chamber interior 1714. As seen in
The through-holes 1778 may be configured in various ways in order to deliver uniform gas flow onto the substrate. In some embodiments, these through-holes may all have the same outer diameter, such as between about 0.03 inches and 0.05 inches, including about 0.04 inches (1.016 mm). These faceplate through-holes may also be arranged throughout the faceplate in order to create uniform flow out of the faceplate.
Referring back to
In some embodiments, the gas distribution unit 1710 may include a second unit heater 1782 that is configured to heat the faceplate 1776. This second unit heater 1782 may include one or more resistive heating elements, fluid conduits for flowing a heating fluid, or both. Using two heaters 1780 and 1782 in the gas distribution unit 1710 may enable various heat transfers within the gas distribution unit 1710. This may include using the first and/or second unit heaters 1780 and 1782 to heat the faceplate 1776 in order to provide a temperature-controlled chamber, as described above, in order to reduce or prevent unwanted condensation on elements of the gas distribution unit 1710.
The apparatus 1700 may also be configured to cool the substrate. This cooling may include flowing a cooling gas onto the substrate, moving the substrate close to the faceplate to allow heat transfer between the substrate and the faceplate, or both. Actively cooling the substrate enables more precise temperature control and faster transitions between temperatures which reduces processing time and improves throughput. In some embodiments, the first unit heater 1780 that flows the heat transfer fluid through fluid conduits may be used to cool the substrate 1718 by transferring heat away from the faceplate 1776 that is transferred from the substrate 1719. A substrate 1718 may therefore be cooled by positioning it in close proximity to the faceplate 1776, such as by a gap 1786 of less than or equal to 5 mm or 2 mm, such that the heat in the substrate 1718 is radiatively transferred to the faceplate 1776, and transferred away from the faceplate 1776 by the heat transfer fluid in the first unit heater 1780. The faceplate 1776 may therefore be considered a heat sink for the substrate 1718 in order to cool the substrate 1718.
In some embodiments, the apparatus 1700 may further include a cooling fluid source 1773 which may contain a cooling fluid (a gas or a liquid), and a cooler (not pictured) configured to cool the cooling fluid to a desired temperature, such as less than or equal to at least about 90° C., at least about 70° C., at least about 50° C., at least about 20° C., at least about 10° C., at least about 0° C., at least about −50° C., at least about −100° C., at least about −150° C., at least about −190° C., at least about −200° C., or at least about −250° C., for instance. The apparatus 1700 includes piping to deliver the cooling fluid to the one or more fluid inlets 1770, and the gas distribution unit 1710 which is configured to flow the cooling fluid onto the substrate. In some embodiments, the fluid may be in liquid state when it is flowed to the chamber 1702 and may turn to a vapor state when it reaches the chamber interior 1714, for example if the chamber interior 1714 is at a low pressure state, such as described above, e.g., between about 0.1 Torr and 10 Torr, or between about 0.1 Torr and 100 Torr, or between about 20 Torr and 200 Torr, for instance. The cooling fluid may be an inert element, such as nitrogen, argon, or helium. In some instances, the cooling fluid may include, or may only have, a non-inert element or mixture, such as hydrogen gas. In some embodiments, the flow rate of the cooling fluid into the chamber interior 1714 may be at least about 0.25 liters per minute, at least about 0.5 liters per minute, at least about 1 liters per minute, at least about 5 liters per minute, at least about 10 liters per minute, at least about 50 liters per minute, or at least about 100 liters per minute, for example. In certain embodiments, the apparatus may be configured to cool a substrate at one or more cooling rates, such as at least about 5° C./second, at least about 10° C./second, at least about 15° C./second, at least about 20° C./second, at least about 30° C./second, or at least about 40° C./second.
In some embodiments, the apparatus 1700 may actively cool the substrate by both moving the substrate close to the faceplate and flowing cooling gas onto the substrate. In some instances, the active cooling may be more effective by flowing the cooling gas while the substrate is in close proximity to the faceplate. The effectiveness of the cooling gas may also be dependent on the type of gas used.
The apparatuses provided herein can therefore rapidly heat and cool a substrate.
In some embodiments, the apparatus 1700 may include a mixing plenum for blending and/or conditioning process gases for delivery before reaching the fluid inlets 1770. One or more mixing plenum inlet valves may control introduction of process gases to the mixing plenum. In some other embodiments, the gas distribution unit 1710 may include one or more mixing plenums within the gas distribution unit 1710. The gas distribution unit 1710 may also include one or more annular flow paths fluidically connected to the through-holes 1778 which may equally distribute the received fluid to the through-holes 1778 in order to provide uniform flow onto the substrate.
Apparatus 1700 includes a controller 1731, which may be the same as controller 1666 and which may include one or more physical or logical controllers, that is communicatively connected with and that controls some or all of the operations of a processing chamber, and is able to perform any of the processes described herein.
Process station 2000 fluidly communicates with reactant delivery system 2001 for delivering process gases to a distribution showerhead 2006. Reactant delivery system 2001 includes a mixing vessel 2004 for blending and/or conditioning process gases for delivery to showerhead 2006. One or more mixing vessel inlet valves 2020 may control introduction of process gases to mixing vessel 2004. Similarly, a showerhead inlet valve 2005 may control introduction of process gasses to the showerhead 2006.
Some reactants, like BTBAS, may be stored in liquid form prior to vaporization at and subsequent delivery to the process station. For example, the embodiment of
In some embodiments, reactant liquid may be vaporized at a liquid injector. For example, a liquid injector may inject pulses of a liquid reactant into a carrier gas stream upstream of the mixing vessel. In one scenario, a liquid injector may vaporize reactant by flashing the liquid from a higher pressure to a lower pressure. In another scenario, a liquid injector may atomize the liquid into dispersed microdroplets that are subsequently vaporized in a heated delivery pipe. It will be appreciated that smaller droplets may vaporize faster than larger droplets, reducing a delay between liquid injection and complete vaporization. Faster vaporization may reduce a length of piping downstream from vaporization point 2003. In one scenario, a liquid injector may be mounted directly to mixing vessel 2004. In another scenario, a liquid injector may be mounted directly to showerhead 2006.
In some embodiments, a liquid flow controller upstream of vaporization point 2003 may be provided for controlling a mass flow of liquid for vaporization and delivery to process station 2000. For example, the liquid flow controller (LFC) may include a thermal mass flow meter (MFM) located downstream of the LFC. A plunger valve of the LFC may then be adjusted responsive to feedback control signals provided by a proportional-integral-derivative (PID) controller in electrical communication with the MFM. However, it may take one second or more to stabilize liquid flow using feedback control. This may extend a time for dosing a liquid reactant. Thus, in some embodiments, the LFC may be dynamically switched between a feedback control mode and a direct control mode. In some embodiments, the LFC may be dynamically switched from a feedback control mode to a direct control mode by disabling a sense tube of the LFC and the PID controller.
Showerhead 2006 distributes process gases toward substrate 2012. In the embodiment shown in
In some embodiments, a microvolume 2007 is located beneath showerhead 2006. Performing an ALD and/or CVD process in a microvolume rather than in the entire volume of a process station may reduce reactant exposure and sweep times, may reduce times for altering process conditions (e.g., pressure, temperature, etc.), may limit an exposure of process station robotics to process gases, etc. Example microvolume sizes include, but are not limited to, volumes between 0.1 liter and 2 liters. This microvolume also impacts productivity throughput. While deposition rate per cycle drops, the cycle time also simultaneously reduces. In certain cases, the effect of the latter is dramatic enough to improve overall throughput of the module for a given target thickness of film.
In some embodiments, pedestal 2008 may be raised or lowered to expose substrate 2012 to microvolume 2007 and/or to vary a volume of microvolume 2007. For example, in a substrate transfer phase, pedestal 2008 may be lowered to allow substrate 2012 to be loaded onto pedestal 2008. During a deposition process phase, pedestal 2008 may be raised to position substrate 2012 within microvolume 2007. In some embodiments, microvolume 2007 may completely enclose substrate 2012 as well as a portion of pedestal 2008 to create a region of high flow impedance during a deposition process.
Optionally, pedestal 2008 may be lowered and/or raised during portions the deposition process to modulate process pressure, reactant concentration, etc., within microvolume 2007. In one scenario where process chamber body 2002 remains at a base pressure during the deposition process, lowering pedestal 2008 may allow microvolume 2007 to be evacuated. Example ratios of microvolume to process chamber volume include, but are not limited to, volume ratios between 1:2000 and 1:10. It will be appreciated that, in some embodiments, pedestal height may be adjusted programmatically by a suitable computer controller.
In another scenario, adjusting a height of pedestal 2008 may allow a plasma density to be varied during plasma activation and/or treatment cycles included in the deposition process. At the conclusion of the deposition process phase, pedestal 2008 may be lowered during another substrate transfer phase to allow removal of substrate 2012 from pedestal 2008.
While the example microvolume variations described herein refer to a height-adjustable pedestal, it will be appreciated that, in some embodiments, a position of showerhead 2006 may be adjusted relative to pedestal 2008 to vary a volume of microvolume 2007. Further, it will be appreciated that a vertical position of pedestal 2008 and/or showerhead 2006 may be varied by any suitable mechanism within the scope of the present disclosure. In some embodiments, pedestal 2008 may include a rotational axis for rotating an orientation of substrate 2012. It will be appreciated that, in some embodiments, one or more of these example adjustments may be performed programmatically by one or more suitable computer controllers.
In some embodiments, the processing chamber in
In some embodiments, the plasma may be monitored in-situ by one or more plasma monitors. In one scenario, plasma power may be monitored by one or more voltage, current sensors (e.g., VI probes). In another scenario, plasma density and/or process gas concentration may be measured by one or more optical emission spectroscopy sensors (OES). In some embodiments, one or more plasma parameters may be programmatically adjusted based on measurements from such in-situ plasma monitors. For example, an OES sensor may be used in a feedback loop for providing programmatic control of plasma power. It will be appreciated that, in some embodiments, other monitors may be used to monitor the plasma and other process characteristics. Such monitors may include, but are not limited to, infrared (IR) monitors, acoustic monitors, and pressure transducers.
In some embodiments, the plasma may be controlled via input/output control (IOC) sequencing instructions. In one example, the instructions for setting plasma conditions for a plasma process phase may be included in a corresponding plasma activation recipe phase of a deposition process recipe. In some cases, process recipe phases may be sequentially arranged, so that all instructions for a deposition process phase are executed concurrently with that process phase. In some embodiments, instructions for setting one or more plasma parameters may be included in a recipe phase preceding a plasma process phase. For example, a first recipe phase may include instructions for setting a flow rate of an inert and/or a reactant gas, instructions for setting a plasma generator to a power set point, and time delay instructions for the first recipe phase. A second, subsequent recipe phase may include instructions for enabling the plasma generator and time delay instructions for the second recipe phase. A third recipe phase may include instructions for disabling the plasma generator and time delay instructions for the third recipe phase. It will be appreciated that these recipe phases may be further subdivided and/or iterated in any suitable way within the scope of the present disclosure.
In some deposition processes, plasma strikes last on the order of a few seconds or more in duration. In certain implementations, much shorter plasma strikes may be used. These may be on the order of 10 ms to 1 second, typically, about 20 to 80 ms, with 50 ms being a specific example. Such very short RF plasma strikes require extremely quick stabilization of the plasma. To accomplish this, the plasma generator may be configured such that the impedance match is set preset to a particular voltage, while the frequency is allowed to float. Conventionally, high-frequency plasmas are generated at an RF frequency at about 13.56 MHz. In various embodiments disclosed herein, the frequency is allowed to float to a value that is different from this standard value. By permitting the frequency to float while fixing the impedance match to a predetermined voltage, the plasma can stabilize much more quickly, a result which may be important when using the very short plasma strikes associated with some types of deposition cycles.
In some embodiments, pedestal 2008 may be temperature controlled via heater 2010. In some embodiments, the heater 2010 may be the same as the heater unit described above and shown in
Although
For some processing chambers, such as deposition chambers 1006 and 1204 in
As provided above, a system controller may be employed on the tools described herein to control process conditions during etching and/or deposition. The controller, 1029 in
The controller is configured to perform any technique described above. For instance, referring to apparatus 1000 of
While the subject matter disclosed herein has been particularly described with respect to the illustrated embodiments, it will be appreciated that various alterations, modifications and adaptations may be made based on the present disclosure, and are intended to be within the scope of the present invention. It is to be understood that the description is not limited to the disclosed embodiments but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the scope of the claims.
A PCT Request Form is filed concurrently with this specification as part of the present application. Each application that the present application claims benefit of or priority to as identified in the concurrently filed PCT Request Form is incorporated by reference herein in their entireties and for all purposes.
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/US2022/042570 | 9/4/2022 | WO |
| Number | Date | Country | |
|---|---|---|---|
| 63260946 | Sep 2021 | US |
