Techniques for providing a direct injection semiconductor memory device

Abstract

Techniques for providing a direct injection semiconductor memory device are disclosed. In one exemplary embodiment, the techniques may be realized as a direct injection semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. At least one of the plurality of memory cells may include a first region coupled to a respective bit line of the array, a second region coupled to a respective source line of the array, a body region spaced apart from and capacitively coupled to a respective word line of the array, wherein the body region may be electrically floating and disposed between the first region and the second region, and a third region coupled to a respective carrier injection line of the array, wherein the respective carrier injection line may be one of a plurality of carrier injection lines in the array that are coupled to each other.

Description

FIELD OF THE DISCLOSURE

The present disclosure relates generally to semiconductor memory devices and, more particularly, to techniques for providing a direct injection semiconductor memory device.

BACKGROUND OF THE DISCLOSURE

The semiconductor industry has experienced technological advances that have permitted increases in density and/or complexity of semiconductor memory devices. Also, the technological advances have allowed decreases in power consumption and package sizes of various types of semiconductor memory devices. There is a continuing trend to employ and/or fabricate advanced semiconductor memory devices using techniques, materials, and devices that improve performance, reduce leakage current, and enhance overall scaling. Silicon-on-insulator (SOI) and bulk substrates are examples of materials that may be used to fabricate such semiconductor memory devices. Such semiconductor memory devices may include, for example, partially depleted (PD) devices, fully depleted (FD) devices, multiple gate devices (for example, double, triple gate, or surrounding gate), and Fin-FET devices.

A semiconductor memory device may include a memory cell having a memory transistor with an electrically floating body region wherein electrical charges may be stored. When excess majority electrical charges carriers are stored in the electrically floating body region, the memory cell may store a logic high (e.g., binary “1” data state). When the electrical floating body region is depleted of majority electrical charge carriers, the memory cell may store a logic low (e.g., binary “0” data state). Also, a semiconductor memory device may be fabricated on silicon-on-insulator (SOI) substrates or bulk substrates (e.g., enabling body isolation). For example, a semiconductor memory device may be fabricated as a three-dimensional (3-D) device (e.g., multiple gate devices, Fin-FETs, recessed gates and pillars).

In one conventional technique, the memory cell of the semiconductor memory device may be read by applying bias signals to a source/drain region and/or a gate of the memory transistor. As such, a conventional reading technique may involve sensing an amount of current provided/generated by/in the electrically floating body region of the memory cell in response to the application of the source/drain region or gate bias signals to determine a data state stored in the memory cell. For example, the memory cell may have two or more different current states corresponding to two or more different logical states (e.g., two different current conditions/states corresponding to two different logic states: a binary “0” data state and a binary “1” data state).

In another conventional technique, the memory cell of the semiconductor memory device may be written to by applying bias signals to the source/drain region(s) and/or the gate of the memory transistor. As such, a conventional writing technique may result in an increase/decrease of majority charge carriers in the electrically floating body region of the memory cell which, in turn, may determine the data state of the memory cell. An increase of majority charge carriers in the electrically floating body region may result from impact ionization, band-to-band tunneling (gate-induced drain leakage “GIDL”), or direct injection. A decrease of majority charge carriers in the electrically floating body region may result from charge carriers being removed via drain region charge carrier removal, source region charge carrier removal, or drain and source region charge carrier removal, for example, using back gate pulsing.

Often, conventional reading and/or writing operations may lead to relatively large power consumption and large voltage potential swings which may cause disturbance to unselected memory cells in the semiconductor memory device. Also, pulsing between positive and negative gate biases during read and write operations may reduce a net quantity of majority charge carriers in the electrically floating body region of the memory cell in the semiconductor memory device, which, in turn, may result in an inaccurate determination of the state of the memory cell. Furthermore, in the event that a bias is applied to the gate of the memory transistor that is below a threshold voltage potential of the memory transistor, a channel of minority charge carriers beneath the gate may be eliminated. However, some of the minority charge carriers may remain “trapped” in interface defects. Some of the trapped minority charge carriers may recombine with majority charge carriers, which may be attracted to the gate as a result of the applied bias. As a result, the net quantity of majority charge carriers in the electrically floating body region may be reduced. This phenomenon, which is typically characterized as charge pumping, is problematic because the net quantity of majority charge carriers may be reduced in the electrically floating body region of the memory cell, which, in turn, may result in an inaccurate determination of the state of the memory cell.

In view of the foregoing, it may be understood that there may be significant problems and shortcomings associated with conventional techniques for fabricating and/or operating semiconductor memory devices.

SUMMARY OF THE DISCLOSURE

Techniques for providing a direct injection semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a direct injection semiconductor memory device comprising a plurality of memory cells arranged in an array of rows and columns. At least one of the plurality of memory cells may comprise a first region coupled to a respective bit line of the array and a second region coupled to a respective source line of the array. At least one of the plurality of memory cells may also comprise a body region spaced apart from and capacitively coupled to a respective word line of the array, wherein the body region may be electrically floating and disposed between the first region and the second region. At least one of the plurality of memory cells may further comprise a third region coupled to a respective carrier injection line of the array and wherein the respective carrier injection line may be one of a plurality of carrier injection lines in the array that are coupled to each other.

In accordance with other aspects of the particular exemplary embodiment, the first region, the body region, and the second region may form a first bipolar transistor.

In accordance with further aspects of this particular exemplary embodiment, the body region, the second region, and the third region may form a second bipolar transistor.

In accordance with additional aspects of this particular exemplary embodiment, the respective carrier injection line may contact the third region.

In accordance with yet another aspect of this particular exemplary embodiment, the direct injection semiconductor memory device may further comprise a constant voltage source applying a positive bias to the third region via the respective carrier injection line.

In accordance with other aspects of the particular exemplary embodiment, the respective bit line may extend from the first region perpendicular to at least a portion of at least one of the respective source line, the respective word line, and the respective carrier injection line.

In accordance with further aspects of this particular exemplary embodiment, the respective word line may extend from near the body region horizontally parallel to at least a portion of at least one of the respective source line and the respective carrier injection line.

In accordance with additional aspects of this particular exemplary embodiment, the respective source line may extends from the second region horizontally parallel to at least one of the respective word line and the respective carrier injection line.

In accordance with yet another aspect of this particular exemplary embodiment, the direct injection semiconductor memory device may further comprise a fourth region disposed between the third region and a substrate.

In accordance with other aspects of the particular exemplary embodiment, the fourth region may be N-doped region and the substrate is a P-type substrate.

In accordance with further aspects of this particular exemplary embodiment, the first region and the second region may be N-doped regions.

In accordance with additional aspects of this particular exemplary embodiment, the body region and the third region may be P-doped regions.

In another particular exemplary embodiment, the techniques may be realized as a method for biasing a direct injection semiconductor memory device comprising the steps of applying a plurality of voltage potentials to a least one of a plurality of memory cells arranged in an array of rows and columns. The step of applying a plurality of voltage potentials to the at least one of a plurality of memory cells may comprise applying a first voltage potential to a first region via a respective bit line of the array and applying a second voltage potential to a second region via a respective source line of the array. The step of applying a plurality of voltage potentials to the at least one of a plurality of memory cells may also comprise applying a third voltage potential to a respective word line of the array, wherein the word line is spaced apart from and capacitively to a body region that is electrically floating and disposed between the first region and the second region. The step of applying a plurality of voltage potentials to the at least one of a plurality of memory cells may further comprise applying a fourth voltage potential to a third region via a respective carrier injection line of the array, and wherein the respective carrier injection lines is one of a plurality of the carrier injection lines in the array that are coupled to each other.

In accordance with other aspects of the particular exemplary embodiment, the method for biasing a direct injection semiconductor memory device further comprise increasing the third voltage potential applied to the respective word line from the third voltage potential applied to the respective word line during a hold operation to perform a read operation.

In accordance with further aspects of this particular exemplary embodiment, the method for biasing a direct injection semiconductor memory device further comprise increasing the second voltage potential applied to the respective source line from the second voltage potential applied to the respective source line during a hold operation to perform a read operation.

In accordance with additional aspects of this particular exemplary embodiment, the method for biasing a direct injection semiconductor memory device further comprise increasing the first voltage potential applied to the respective bit line from the first voltage potential applied to the respective bit line during a hold operation in order to reduce a disturbance during a read operation.

In accordance with yet another aspect of this particular exemplary embodiment, the method for biasing a direct injection semiconductor memory device may further comprise maintaining the third voltage potential applied to the respective word line from the third voltage potential applied to the respective word line during a hold operation to perform a write logic high operation.

In accordance with other aspects of the particular exemplary embodiment, the method for biasing a direct injection semiconductor memory device may further comprise lowering the second voltage potential applied to the second region via the respective source line from the second voltage potential applied to the second region during a hold operation to perform a write logic high operation.

In accordance with further aspects of this particular exemplary embodiment, the method for biasing a direct injection semiconductor memory device further comprise increasing the third voltage potential applied to the respective word line from the third voltage potential applied to the respective word line during a hold operation to perform a write logic low operation.

In accordance with additional aspects of this particular exemplary embodiment, the method for biasing a direct injection semiconductor memory device may further comprise increasing the second voltage potential applied to the respective source line from the second voltage potential applied to the respective source line during a hold operation to perform a write logic low operation.

In accordance with yet another aspect of this particular exemplary embodiment, the method for biasing a direct injection semiconductor memory device may further comprise maintaining the first voltage potential applied to the respective bit line from the first voltage potential applied to the respective bit line during a hold operation to perform a write logic low operation.

In accordance with other aspects of the particular exemplary embodiment, the method for biasing a direct injection semiconductor memory device may further comprise increasing the first voltage potential applied to the respective bit line during a write logic low operation from the first voltage potential applied to the respective bit line during a hold operation to maintain a logic high stored in the memory cell.

The present disclosure will now be described in more detail with reference to exemplary embodiments thereof as shown in the accompanying drawings. While the present disclosure is described below with reference to exemplary embodiments, it should be understood that the present disclosure is not limited thereto. Those of ordinary skill in the art having access to the teachings herein will recognize additional implementations, modifications, and embodiments, as well as other fields of use, which are within the scope of the present disclosure as described herein, and with respect to which the present disclosure may be of significant utility.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to facilitate a fuller understanding of the present disclosure, reference is now made to the accompanying drawings, in which like elements are referenced with like numerals. These drawings should not be construed as limiting the present disclosure, but are intended to be exemplary only.

FIG. 1 shows a block diagram of a semiconductor memory device including a memory cell array, data write and sense circuitry, and memory cell selection and control circuitry in accordance with an embodiment of the present disclosure.

FIG. 2 shows a schematic diagram of at least a portion of a memory cell array having a plurality of memory cells in accordance with an embodiment of the present disclosure.

FIG. 3 shows a cross-sectional view of two memory cells along a column direction of a memory cell array in accordance with an embodiment of the present disclosure.

FIG. 4 shows control signal voltage waveforms for performing a refresh operation on a memory cell in accordance with an embodiment of the present disclosure.

FIG. 5 shows control signal voltage waveforms for performing a refresh operation on a memory cell in accordance with an alternative embodiment of the present disclosure.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

Referring to FIG. 1, there is shown a block diagram of a semiconductor memory device 10 comprising a memory cell array 20, data write and sense circuitry 36, and memory cell selection and control circuitry 38 in accordance with an embodiment of the present disclosure. The memory cell array 20 may comprise a plurality of memory cells 12 each coupled to the memory cell selection and control circuitry 38 via a word line (WL) 28, a source line (CN) 30, and a carrier injection line (EP) 34, and to the data write and sense circuitry 36 via a bit line (EN) 32. It may be appreciated that the source line (CN) 30 and the bit line (EN) 32 are designations used to distinguish between two signal lines and they may be used interchangeably.

The data write and sense circuitry 36 may read data from and may write data to selected memory cells 12. In an exemplary embodiment, the data write and sense circuitry 36 may include a plurality of data sense amplifiers. Each data sense amplifier may receive at least one bit line (EN) 32 and a current or voltage reference signal. For example, each data sense amplifier may be a cross-coupled type sense amplifier to sense a data state stored in a memory cell 12.

Each data sense amplifier may employ voltage and/or current sensing circuitry and/or techniques. In an exemplary embodiment, each data sense amplifier may employ current sensing circuitry and/or techniques. For example, a current sense amplifier may compare current from a selected memory cell 12 to a reference current (e.g., the current of one or more reference cells). From that comparison, it may be determined whether the selected memory cell 12 stores a logic high (e.g., binary “1” data state) or a logic low (e.g., binary “0” data state). It may be appreciated by one having ordinary skill in the art that various types or forms of the data write and sense circuitry 36 (including one or more sense amplifiers, using voltage or current sensing techniques, to sense a data state stored in a memory cell 12) may be employed to read data stored in memory cells 12 and/or write data to memory cells 12.

The memory cell selection and control circuitry 38 may select and/or enable one or more predetermined memory cells 12 to facilitate reading data therefrom and/or writing data thereto by applying control signals on one or more word lines (WL) 28, source lines (CN) 30, and/or carrier injection lines (EP) 34. The memory cell selection and control circuitry 38 may generate such control signals from address signals, for example, row address signals. Moreover, the memory cell selection and control circuitry 38 may include a word line decoder and/or driver. For example, the memory cell selection and control circuitry 38 may include one or more different control/selection techniques (and circuitry therefor) to select and/or enable one or more predetermined memory cells 12. Notably, all such control/selection techniques, and circuitry therefor, whether now known or later developed, are intended to fall within the scope of the present disclosure.

In an exemplary embodiment, the semiconductor memory device 10 may implement a two step write operation whereby all the memory cells 12 in a row of memory cells 12 may be written to a predetermined data state by first executing a “clear” or a logic low (e.g., binary “0” data state) write operation, whereby all of the memory cells 12 in the row of memory cells 12 are written to logic low (e.g., binary “0” data state). Thereafter, selected memory cells 12 in the row of memory cells 12 may be selectively written to the predetermined data state (e.g., a logic high (binary “1” data state). The semiconductor memory device 10 may also implement a one step write operation whereby selective memory cells 12 in a row of memory cells 12 may be selectively written to either a logic high (e.g., binary “1” data state) or a logic low (e.g., binary “0” data state) without first implementing a “clear” operation. The semiconductor memory device 10 may employ any of the exemplary writing, preparation, holding, refresh, and/or reading techniques described herein.

The memory cells 12 may comprise N-type, P-type and/or both types of transistors. Circuitry that is peripheral to the memory array 20 (for example, sense amplifiers or comparators, row and column address decoders, as well as line drivers (not illustrated herein)) may also include P-type and/or N-type transistors. Regardless of whether P-type or N-type transistors are employed in memory cells 12 in the memory cell array 20, suitable voltage potentials (for example, positive or negative voltage potentials) for reading from and/or writing to the memory cells 12 will be described further herein.

Referring to FIG. 2, there is shown a schematic diagram of at least a portion of the memory cell array 20 having the plurality of memory cells 12 in accordance with an embodiment of the present disclosure. Each of the memory cells 12 may comprise a first bipolar transistor 14a and a second bipolar transistor 14b coupled to each other. For example, the first bipolar transistor 14a and/or the second bipolar transistor 14b may be an NPN bipolar transistor or a PNP bipolar transistor. As illustrated in FIG. 2, the first bipolar transistor 14a may be an NPN bipolar transistor and the second bipolar transistor 14b may be a PNP bipolar transistor. In another exemplary embodiment, the first memory transistor 14a may be a PNP bipolar transistor and the second memory transistor 14b may be an NPN bipolar transistor.

Each memory cell 12 may be coupled to a respective word line (WL) 28, a respective source line (CN) 30, a respective bit line (EN) 32, and a respective carrier injection line (EP) 34. Data may be written to or read from a selected memory cell 12 by applying suitable control signals to a selected word line (WL) 28, a selected source line (CN) 30, a selected bit line (EN) 32, and/or a selected carrier injection line (EP) 34. In an exemplary embodiment, each word line (WL) 28, source line (CN) 30, and carrier injection line (EP) 34 may extend horizontally parallel to each other in a row direction. Each bit line (EN) 32 may extend vertically in a column direction perpendicular to each word line (WL) 28, source line (CN) 30, and/or carrier injection line (EP) 34.

In an exemplary embodiment, one or more respective bit lines (EN) 32 may be coupled to one or more data sense amplifiers (not shown) of the data write and sense circuitry 36 to read data states of one or more memory cells 12 in the column direction. A data state may be read from one or more selected memory cells 12 by applying one or more control signals to the one or more selected memory cells 12 via a selected word line (WL) 28, a selected source line (CN) 30, and/or a selected carrier injection line (EP) 34 in order to generate a voltage potential and/or a current in the one or more selected memory cells 12 and output the generated voltage potential and/or current to the data write and sense circuitry 36 via a corresponding bit line (EN) 32 in order to read a data state stored in each selected memory cell 12.

In the event that a data state is read from a selected memory cell 12 via a selected bit line (EN) 32, then only the bit line (EN) 32 may be coupled to the data sense amplifier of the data write and sense circuitry 36 while the source line (CN) 30 may be separately controlled via a voltage potential/current source (e.g., a voltage potential/current driver) of the data write and sense circuitry 36. In an exemplary embodiment, the data sense amplifier of the data write and sense circuitry 36 and the voltage potential/current source of the data write and sense circuitry 36 may be configured on opposite sides of the memory cell array 20.

Also, a data state may be written to one or more selected memory cells 12 by applying one or more control signals to the one or more selected memory cells 12 via a selected word line (WL) 28, a selected source line (CN) 30, a selected bit line (EN) 32, and/or a selected carrier injection line (EP) 34. The one or more control signals applied to the one or more selected memory cells 12 via a selected word line (WL) 28, a selected source line (CN) 30, a selected bit line (EN) 32, and/or a selected carrier injection line (EP) 34 may control the first bipolar transistor 14a and/or the second bipolar transistor 14b of each selected memory cell 12 in order to write a desired data state to each selected memory cell 12.

The carrier injection lines (EP) 34 corresponding to different rows of the memory cell array 20 may be coupled to each other. In an exemplary embodiment, the carrier injection lines (EP) 34 (e.g., EP<0>, EP<1>, and EP<2>) of the memory cell array 20 may be coupled together her and driven by subcircuits of the memory cell selection and control circuitry 38 (e.g., driver, inverter, and/r logic circuits). The subcircuits coupled to each carrier injection line (EP) 34 may be independent voltage drivers located within and/or integrated with the memory cell selection and control circuitry 38. To reduce an amount of area required by the subcircuits of the memory cell selection and control circuitry 38, a plurality of carrier injection lines (EP) 34 of the memory cell array 20 may be coupled to a single subcircuit within the memory cell selection and control circuitry 38. In an exemplary embodiment, the subcircuits of the memory cell selection and control circuitry 38 may bias a plurality of carrier injection lines (EP) 34 coupled together to different voltage potentials and/or current levels (e.g., 0V, 10V, etc).

As illustrated in FIG. 2, three rows of carrier injection lines (EP) 34 may be coupled together, however, it may be appreciated by one skilled in the art that the number of rows of carrier injection lines (EP) 34 coupled together within the memory cell array 20 may vary. For example, four rows of carrier injection lines (EP) 34, sixteen rows of carrier injection lines (EP) 34, thirty-two rows of carrier injection lines (EP) 34, and/or sixty-four rows of carrier injection lines (EP) 34 may be coupled together.

Referring to FIG. 3, there is shown a cross-sectional view of two memory cells 12 along a column direction of the memory cell array 20 shown in FIG. 1 in accordance with an embodiment of the present disclosure. As discussed above, each memory cell 12 may comprise two bipolar transistors. In an exemplary embodiment, the first bipolar transistor 14a may be a NPN bipolar transistor and the second bipolar transistor 14b may be a PNP bipolar transistor. In an exemplary embodiment, the first bipolar transistor 14a and the second bipolar transistor 14b may share one or more common regions. The first NPN bipolar transistor 14a may comprise an N+ emitter region 120, a P− base region 122, and an N+ collector region 124. The second PNP bipolar transistor 14b may comprise the P− collector region 122, the N+ base region 124, and a P+ emitter region 126. The N+ region 120, the P− region 122, the N+ region 124, and/or the P+ region 126 may be disposed in sequential contiguous relationship within a pillar or fin configuration that may extend vertically from and/or perpendicularly to a plane defined by an N-well region 128 and/or a P− substrate 130. In an exemplary embodiment, the P− region 122 may be an electrically floating body region of the memory cell 12 configured to accumulate/store charges, and may be spaced apart from and capacitively coupled to the word line (WL) 28.

As shown in FIG. 3, the N+ emitter region 120 of the first bipolar transistor 14a may be coupled to a corresponding bit line (EN) 32. In an exemplary embodiment, the N+ emitter region 120 of the first bipolar transistor 14a may be formed of a semiconductor material (e.g., silicon) comprising donor impurities and coupled to the bit line (EN) 32. For example, the N+ emitter region 120 may be formed of a silicon material doped with phosphorous or arsenic impurities. In an exemplary embodiment, the bit line (EN) 32 may be formed of a metal layer. In another exemplary embodiment, the bit line (EN) 32 may be formed of a polycide layer (e.g., a combination of a metal material and a silicon material). The bit line (EN) 32 may provide a means for accessing one or more selected memory cells 12 on a selected row.

As also shown in FIG. 3, the P− base region 122 of the first bipolar transistor 14a or the P− collector region 122 of the second bipolar transistor 14b may be capacitively coupled to a corresponding word line (WL) 28. In an exemplary embodiment, the P− region 122 may be formed of a semiconductor material (e.g., silicon) comprising acceptor impurities. For example, the P− region 122 may be formed of a silicon material doped with boron impurities. The P− region 122 and the word line (WL) 28 may be capacitively coupled via an insulating or dielectric material. In an exemplary embodiment, the word line (WL) 28 may be formed of a polycide layer or a metal layer extending in a row direction of the memory cell array 20.

As further shown in FIG. 3, the N+ region 124 of the memory cell 12 may be coupled to a source line (CN) 30. In an exemplary embodiment, the N+ region 124 may be formed of a semiconductor material (e.g., silicon) comprising donor impurities. For example, the N+ region 124 may be formed of a silicon material doped with phosphorous or arsenic impurities. In an exemplary embodiment, the source line (CN) 30 may be formed of a polycide layer. In another exemplary embodiment, the source line (CN) 30 may be formed of a metal layer. The source line (CN) 30 may circumferentially surround the N+ region 124 of the memory cell 12. The source line (CN) 30 may reduce a disturbance to the memory cell 12. For example, the source line (CN) 30 may be formed of a metal layer and therefore may reduce a hole disturbance in the memory cell 12. The source line (CN) 30 may extend horizontally in a row direction parallel to the word line (WL) 28 and/or the carrier injection line (EP) 34, and may be coupled to a plurality of memory cells 12 (e.g., a row of memory cells 12). For example, the source line (CN) 30, the word line (WL) 28, and/or the carrier injection line (EP) 34 may be arranged in different planes and configured to be parallel to each other. In an exemplary embodiment, the source line (CN) 30 may be arranged in a plane between a plane containing the word line (WL) 28 and a plane containing the carrier injection line (EP) 34.

As further shown in FIG. 3, the P+ emitter region 126 of the second bipolar transistor 14a may be coupled to the carrier injection line (EP) 34. The P+ region 126 may be formed of a semiconductor material (e.g., silicon) comprising acceptor impurities and directly coupled to the carrier injection line (EP) 34. For example, the P+ region 126 may be formed of a silicon material doped with boron impurities. In an exemplary embodiment, the P+ region 126 may be configured as an input region for charges to be stored in the P− region 122 of the memory cell 12. The charges to be stored in the P− region 122 of the memory cell 12 may be supplied by the carrier injection line (EP) 34 and input into the P− region 122 via the N+ region 124 and/or the P+ region 126.

The carrier injection line (EP) 34 may be formed of a polycide layer or a metal layer extending in a row direction of the memory cell array 20. For example, the carrier injection line (EP) 34 may extend horizontally in parallel to the word line (WL) 28 and/or the source line (CN) 30, and may be coupled to a plurality of memory cells 12 (e.g., a row of memory cells 12). For example, the carrier injection line (EP) 34 and the word line (WL) 28 and/or the source line (CN) 30 may be arranged in different planes and configured to be parallel to each other. In an exemplary embodiment, the carrier injection line (EP) 34 may be arranged in a plane below a plane containing the word line (WL) 28 and a plane containing the carrier injection line (EP) 34.

As discussed above, carrier injection lines (EP) 34 corresponding to different rows of the memory cell array 20 may be coupled to each other in order to bias and/or access memory cells 12 in different rows of the memory cell array 20. Thus, in an exemplary embodiment, P+ regions 126 of memory cells 12 in different rows of memory cell array 20 may be coupled to each other by coupling the carrier injection lines (EP) 34 corresponding to different rows of the memory cell array 20. In another exemplary embodiment, carrier injection lines (EP) 34 corresponding to different rows of the memory cell array 20 may be coupled to each other via a carrier injection line plate, a carrier injection grid, or a combination of a carrier injection line plate and a carrier injection grid.

As further shown in FIG. 3, the N-well region 128 may be disposed between the P+ region 126 and the P− substrate 130. The N-well region 128 may be formed of a semiconductor material (e.g., silicon) comprising donor impurities and extending in a planar direction parallel to the P− substrate 130. For example, the N-well region 128 may be formed of a silicon material doped with phosphorous or arsenic impurities. In an exemplary embodiment, the N-well region 128 may comprise a strip protruding portion corresponding to each row of the memory cell array 20. For example, the strip protruding portion of the N-well region 128 may be configured to accommodate a row of memory cells 12 of the memory cell array 20.

In an exemplary embodiment, the P− substrate 130 may be made of a semiconductor material (e.g., silicon) comprising acceptor impurities and may form a base of the memory cell array 20. For example, the P− substrate 130 may be formed of a silicon material doped with boron impurities. In alternative exemplary embodiments, a plurality of P− substrates 130 may form a base of the memory cell array 20 or a single P− substrate 130 may form the base of the memory cell array 20. Also, the P-substrate 130 may be made in the form of a P-well substrate.

Referring to FIG. 4, there are shown control signal voltage waveforms for performing a refresh operation on a memory cell in accordance with an embodiment of the present disclosure. The refresh operation may include control signals configured to perform one or more sub-operations. In an exemplary embodiment, the refresh operation may include a preparation to start operation, a read operation, a write logic low (e.g., binary “0” data state) operation, a write logic high (e.g., binary “1” data state) operation, and/or preparation to end operation.

Prior to performing a refresh operation, the control signals may be configured to perform a hold operation in order to maintain a data state (e.g., a logic high (binary “1” data state) or a logic low (binary “0” data state)) stored in the memory cell 12. In particular, the control signals may be configured to perform a hold operation in order to maximize a retention time of a data state (e.g., a logic low (binary “0” data state) and/or a logic high (binary “1” data state)) stored in the memory cell 12. Also, the control signals for the hold operation may be configured to eliminate or reduce activities or fields (e.g., electrical fields between junctions which may lead to leakage of charges) within the memory cell 12. In an exemplary embodiment, during a hold operation, a negative voltage potential may be applied to the word line (WL) 28 that may be capacitively coupled to the P− region 122 of the memory cell 12 while voltage potentials applied to other regions (e.g., the N+ region 120, the N+ region 124, and/or the P+ region 126) may be maintained at approximately 0V. For example, the negative voltage potential applied to the word line (WL) 28 (e.g., capacitively coupled to the P− region 122 of the memory cell 12) may be −1.5V. During the hold operation, the junction between the N+ region 124 and the P− region 122 and the junction between the N+ region 120 and the P− region 122 may be reverse biased in order to retain a data state (e.g., a logic high (binary “1” data state) or a logic low (binary “0” data state)) store in the memory cell 12.

In an exemplary embodiment, a refresh operation may include control signals to perform a preparation to start operation where the control signals may be applied to a memory cell 12 in order to prepare the memory cell 12 for one or more subsequent operations (e.g., a read operation and/or a write operation). For example, control signals applied to a memory cell 12 may be configured to minimize a time delay between voltages applied to the N+ region 124 of the memory cell 12 and the word line (WL) 28 in order to reduce a disturbance. A leakage of charge carriers from the P− region 122 may result when the preparation to start operation is not performed. For example, when 0V is applied to the bit line (EN) 32, 1.5V is applied to the source line (CN) 30 (at the start of a read operation), and −1.5V is applied to the word line (WL) 28, an electric field may be created across the junction from the P− region 122 and the N+ region 124. The electric field may cause a leakage (e.g., in a logic high (binary “1” data state) or an increase (e.g., in a logic low (binary “0” data state)) of charge stored in the memory cell 12, or band-to-band tunneling (e.g., gate-induced drain leakage “GIDL”).

In an exemplary embodiment, control signals applied to a memory cell 12 during the preparation to start operation may be configured to reduce band-to-band tunneling (e.g., gate-induced drain leakage “GIDL”). For example, a positive voltage potential may be applied to the N+ region 124 of the memory cell 12, while voltage potentials applied to other regions (e.g., the N+ region 120, the capacitively coupled P− region 122 via the word line (WL) 28, and/or the P+ region 126) of the memory cell 12 may be maintained at the same voltage potentials applied during the hold operation. The positive voltage potential applied to the source line (CN) 30 may be raised to 1.5V from 0V, while the voltage potential applied to the bit line (EN) 32 and the carrier injection line (EP) 34 may be maintained at 0V. The voltage potential applied to the word line (WL) 28 (e.g., capacitively coupled to the P− region 122) may be maintained at −1.5V.

In an exemplary embodiment, a refresh operation may include a read operation where the control signals may be configured to read a data state (e.g., a logic low (binary “0” data state) and/or a logic high (binary “1” data state)) stored in one or more selected memory cells 12 of one or more selected rows of the memory cell array 20. The control signals may be configured to a predetermined voltage potential to implement a read operation via the bit line (EN) 32. In an exemplary embodiment, a voltage potential applied to the word line (WL) 28 (e.g., capacitively coupled to the P− region 122) and/or a voltage potential applied to the N+ region 124 via the source line (CN) may be raised to a predetermined voltage potential in order to read a data state stored in the memory cell 12. In another exemplary embodiment, in the event that voltage potentials are applied to the memory cell 12 in preparation for the read operation (e.g., in the preparation to start operation as discussed above), the voltage potential applied to the N+ region 124 of the memory cell 12 may remain the same as the voltage potential applied during the preparation to start operation. For example, the voltage potential applied to the word line (WL) 28 (e.g., capacitively coupled to the P− region 122 of the memory cell 12) may be raised to −0.5V from −1.5V, while the voltage potential applied to the N+ region 124 of the memory cell 12 may be raised to or maintained at 1.5V.

In an exemplary embodiment, during the read operation, the voltage potential applied to the word line (WL) 28 (e.g., capacitively coupled to the P− region 122 of the memory cell 12) may be raised to −0.5V and the voltage potential applied to the source line (CN) 30 may be raised to 1.5V. Under such biasing, the junction between the P− region 122 and the N+ region 120 may become forward biased. Also, under such biasing, the junction between the P− region 122 and the N+ region 124 may be reverse biased or become weakly forward biased (e.g., above the reverse bias voltage and below forward bias threshold voltage or the voltage potential at the p-diffusion region is higher than the voltage potential at the n-diffusion region). A voltage potential or current may be generated when forward biasing the junction between the P− region 122 and the N+ region 120. The voltage potential or current generated may be output to a data sense amplifier via the bit line (EN) 32 coupled to the N+ region 120. An amount of voltage potential or current generated may be representative of a data state (e.g., a logic low (binary “0” data state) and/or a logic high (binary “1” data state)) stored in the memory cell 12.

In an exemplary embodiment, when a logic low (e.g., binary “0” data state) is stored in the memory cell 12, the junction between the P− region 122 and the N+ region 120 may remain reverse biased or become weakly forward biased (e.g., above the reverse bias voltage and below forward bias threshold voltage or the voltage potential at the p-diffusion region is higher than the voltage potential at the n-diffusion region). A small amount of voltage potential and current or no voltage potential and current (e.g., compared to a reference voltage potential or current) may be generated when the junction between the P-region 122 and the N+ region 120 is reverse biased or weakly forward biased. A data sense amplifier in the data write and sense circuitry 36 may detect the small amount of voltage potential and current or no voltage potential and current via the bit line (EN) 32 coupled to the N+ region 120.

In another exemplary embodiment, when a logic high (e.g., binary “1” data state) is stored in the memory cell 12, the junction between the P− region 122 and the N+ region 120 may be forward biased. A larger amount of voltage potential or current (e.g., compared to a reference voltage potential or current) may be generated when the junction between the P− region 122 and the N+ region 120 is forward biased. A data sense amplifier in the data write and sense circuitry 36 may detect the larger amount of voltage potential or current via the bit line (EN) 32 coupled to the N+ region 120.

In an exemplary embodiment, a refresh operation may include a write logic high (e.g., binary “1” data state) operation where the control signals may be configured to write a logic high (e.g., binary “1” data state) to one or more selected memory cells 12 of one or more selected rows of the memory cell array 20. For example, the write logic high (e.g., binary “1” data state) operation may be performed on one or more selected rows of the memory cell array 20 or the entire memory cell array 20 and a subsequent write logic low (e.g., binary “0” data state) operation may be performed on one or more selected memory cells 12. In an exemplary embodiment, a voltage potential applied to the N+ region 120 and/or the P+ region 126 of the memory cells 12 may be maintained at 0V. The voltage potential applied to the word line (WL) 28 (e.g., capacitively coupled to the P-region 122) may be lowered to −1.5V. Simultaneously to or subsequent to lowering a voltage potential applied to the word line (WL) 28, a voltage potential applied to the source line (CN) 30 may be lowered to −1.0V.

Under such biasing, the junction between the N+ region 120 and the P− region 122 may be reverse biased and the junction between the P+ region 126 and the N+ region 124 may become forward biased. A logic high (e.g., binary “1” data state) may be written to the P− region 122 (e.g., majority charge carriers injected into the P− region 122 from the P+ region 126) via the forward biased junction between the P+ region 126 and the N+ region 124. As more majority charge carriers are accumulated in the P− region 122, the voltage potential at the P− region 122 may increase to approximately 0.7V to 1.0V above the voltage potential at N+ region 124. At this time, the first bipolar transistor 14a may start to switch to an “ON” state and the current generated by the first bipolar transistor 14a may increase the voltage potential at N+ region 124 due to resistive voltage potential drop on the source line (CN) 30. The increase of the voltage potential at N+ region 124 may lead to a decrease of current flow in the second bipolar transistor 14b, which in turn may cause a decrease in the voltage potential on the source line (CN) 30 after the write logic high (e.g., binary “1” data state) operation has been completed. For example, the voltage potential on the source line (CN) 30 may decrease toward 0V due to the increase of the voltage potential at the N+ region 124

In an exemplary embodiment, a refresh operation may include a write logic low (e.g., binary “0” data state) operation where the control signals may be configured to perform one or more write operations to one or more selected memory cells 12. For example, the write logic low (e.g., binary “0” data state) operation may be performed to one or more selected memory cells 12 after a write logic high (e.g., binary “1” data state) operation in order to deplete the majority charge carriers accumulated in the P− regions 122 of the one or more selected memory cells 12. In an exemplary embodiment, a voltage potential applied to the N+ region 120 via the bit line (EN) 32 may be maintained at 0V in order to perform the write logic low (e.g., binary “0” data state) operation. A voltage potential applied to the N+ region 124 via the source line (CN) 30 may be raised to 1.0V from −1.0V during the write logic high (e.g., binary “1” data state) operation. Subsequent to or simultaneously to raising the voltage potential applied to the N+ region 124 via the source line (CN) 30, a voltage potential applied to the word line (WL) 28 may be raised to approximately 0.5V from −1.5V.

Under such biasing, the junction between the N+ region 120 and the P− region 122 may become forward biased and the first bipolar transistor 14a (e.g., regions 120-124) may be switched to an “ON” state. The majority charge carriers accumulated in the P− region 122 during the write logic high (e.g., binary “1” data state) operation may be removed via the forward biased junction between the N+ region 120 and the P− region 122. After removing the majority charge carriers accumulated in the P-region 122, a logic low (e.g., binary “0” data state) may be written to the memory cell 12.

In order to maintain a logic high (e.g., binary “1” data state) in one or more unselected memory cells 12 during the write logic low (e.g., binary “0” data state) operation, a masking operation may be performed on the one or more unselected memory cells 12. For example, the voltage potential applied to the N+ region 120 of the one or more unselected memory cells 12 may be raised to 1.0V or higher (e.g., 1.2V) in order to prevent the depletion of majority charge carriers accumulated in the P-region 122. Under such biasing, the junction between the N+ region 120 and the P− region 122 may not be forward biased and the junction between the P− region 122 and the N+ region 124 may not be forward biased in order to prevent the depletion of majority charge carriers accumulated in the P− region 122 and the logic high (e.g., binary “1” data state) may be maintained in the memory cell 12.

In an exemplary embodiment, a refresh operation may also include a preparation to end operation. During the preparation to end operation, the voltage potentials applied to the memory cells 12 may adjust the amount of majority charge carriers or data state stored in the P− region 122 of the memory cells 12. The voltage potential applied to the word line (WL) 28 (e.g., capacitively coupled to the P− region 122) may be lowered to −1.5V and may determine an amount of majority charge carriers or data state stored in the P− region 122 of the memory cells 12. Also, the voltage potentials applied to other regions (e.g., N+ region 120, N+ region 124, and P+ region 126) may be lowered to and/or maintained at 0V in order to maintain a data state stored in the memory cell 12.

Referring to FIG. 5, there are shown control signal voltage waveforms for performing a refresh operation on a memory cell in accordance with an alternative embodiment of the present disclosure. The refresh operation may include control signals configured to perform one or more sub-operations. In an exemplary embodiment, the refresh operation may include a read operation, a write logic low (e.g., binary “0” data state) operation, a write logic high (e.g., binary “1” data state) operation, and/or preparation to end operation.

Prior to performing a refresh operation, the control signals may be configured to perform a hold operation in order to maintain a data state (e.g., a logic high (binary “1” data state) or a logic low (binary “0” data state)) stored in the memory cell 12. In particular, the control signals may be configured to perform a hold operation in order to maximize a retention time of a data state (e.g., a logic low (binary “0” data state) and/or a logic high (binary “1” data state)) stored in the memory cell 12. Also, the control signals for the hold operation may be configured to eliminate or reduce activities or fields (e.g., electrical fields between junctions which may lead to leakage of charges) within the memory cell 12. In an exemplary embodiment, during a hold operation, a negative voltage potential may be applied to the word line (WL) 28 that may be capacitively coupled to the P− region 122 of the memory cell 12 while voltage potentials applied to other regions (e.g., the N+ region 120, the N+ region 124, and/or the P+ region 126) may be maintained at approximately 0V. For example, the negative voltage potential applied to the word line (WL) 28 (e.g., capacitively coupled to the P− region 122 of the memory cell 12) may be −1.5V. During the hold operation, the junction between the N+ region 124 and the P− region 122 and the junction between the N+ region 120 and the P− region 122 may be reverse biased in order to retain a data state (e.g., a logic high (binary “1” data state) or a logic low (binary “0” data state)) stored in the memory cell 12.

In an exemplary embodiment, a refresh operation may include a read operation where the control signals may be configured to read a data state (e.g., a logic low (binary “0” data state) and/or a logic high (binary “1” data state)) stored in one or more selected memory cells 12 of one or more selected rows of the memory cell array 20. The control signals may be configured to a predetermined voltage potential to implement a read operation via the bit line (EN) 32. The read operation may be performed to each memory cell 12 on a selected row of memory cells 12 in disparate steps. For example, a first read operation may be performed to a first selected memory cell 12 on a selected row of memory cells 12 and a second read operation may be performed to a second selected memory cell 12 on the selected row of memory cells 12. In an exemplary embodiment, a first read operation may be performed to a first selected memory cell 12 (e.g., corresponding to a first bit line (EN<0>) 32) on a selected row (e.g., corresponding to a word line (WL) 28) of memory cells 12. A second read operation may be performed to a second selected memory cell (e.g., corresponding to a second bit line (EN<1>) 32) on the selected row (e.g., corresponding to a word line (WL) 28) of memory cells 12.

For example, a first read operation may be performed to a first selected memory cell 12 (e.g., corresponding to a first bit line (EN<0>) 32) on a selected row of memory cells 12. The voltage potential applied to the word line (WL) 28 (e.g., capacitively coupled to the P− region 122) and/or a voltage potential applied to the N+ region 124 via the source line (CN) may be raised to a predetermined voltage potential in order to read a data state stored in the first selected memory cell 12. For example, the voltage potential applied to the word line (WL) 28 (e.g., capacitively coupled to the P− region 122 of the memory cell 12) may be raised to −0.5V from −1.5V, while the voltage potential applied to the N+ region 124 of the memory cell 12 may be raised to 1.2V. The voltage potential applied to the N+ region 120 of the first selected memory cell 12 (e.g., corresponding to the bit line (EN<0>) 32) may be maintained at 0V.

Under such biasing, the junction between the P− region 122 and the N+ region 120 may become forward biased. Also, under such biasing, the junction between the P− region 122 and the N+ region 124 may be reverse biased or become weakly forward biased (e.g., above the reverse bias voltage and below forward bias threshold voltage or the voltage potential at the p-diffusion region is higher than the voltage potential at the n-diffusion region). A voltage potential or current may be generated when forward biasing the junction between the P− region 122 and the N+ region 120. The voltage potential or current generated by the first selected memory cell 12 may be output to a data sense amplifier in the data write and sense circuitry 36 via the corresponding bit line (EN<0>) 32 coupled to the N+ region 120. An amount of voltage potential or current generated may be representative of a data state (e.g., a logic low (binary “0” data state) and/or a logic high (binary “1” data state)) stored in the memory cell 12.

During the first read operation, a voltage potential may be applied to other memory cells 12 (e.g., corresponding to a second bit line (EN<1>) 32, a third bit line (EN<2>) 32, etc.) on the selected row of memory cells 12 in order to reduce disturbance on the one or more unselected memory cells 12. For example, during the first read operation, a voltage potential may be applied to every memory cell 12 along a selected row via the word line (WL) 28. However, when the first read operation is performed on a first memory cell 12 on the selected row, other memory cells 12 on the selected row may experience a disturbance caused by the voltage potential applied via the word line (WL) 28 during the first read operation. In order to reduce a disturbance experienced by the other memory cells 12 on the selected row, a voltage potential may be applied to other memory cells 12 via corresponding bit line (EN) 32.

In an exemplary embodiment, a voltage potential may be applied to the N+ region 120 of a second memory cell 12 via a corresponding bit line (EN<1>) 32. The voltage potential applied via the corresponding bit line (EN<1>) 32 to the second memory cell 12 may be raised to a predetermined voltage potential. In an exemplary embodiment, the voltage potential applied to the bit line (EN<1>) 32 corresponding to the second memory cell 12 may be raised to 1.2V from 0V. Under such biasing, the junction between the N+ region 120 and the P-region 122 of the second memory cell 12 may be reversed biased in order to reduce or eliminate disturbances on the second memory cell 12.

After completion of the first read operation on a first memory cell 12 (e.g., corresponding to the bit line (EN<0>) 32), a second read operation may be performed on a second memory cell 12 (e.g., corresponding to the bit line (EN<1>) 32). For example, after determining a data state stored in a first memory cell 12 (e.g., corresponding to the bit line (EN<0>) 32) during the first read operation, a data state stored in a second memory cell 12 (e.g., corresponding to bit line (EN<1>) 32) may be determined during the second read operation. In an exemplary embodiment, the voltage potential applied to the word line (WL) 28 (e.g., capacitively coupled to the P− region 122 of the memory cell 12) may be raised to −0.5V from −1.5V, while the voltage potential applied to the N+ region 124 of the memory cell 12 may be maintained at 1.2V from the first read operation. The voltage potential applied to the N+ region 120 of the second memory cell 12 (e.g., corresponding to the bit line (EN<1>) 32) may be lowered to 0V from 1.2V.

Under such biasing, the junction between the P− region 122 and the N+ region 120 of the second memory cell 12 may become forward biased. Also under such biasing, the junction between the P− region 122 and the N+ region 124 may be reverse biased or become weakly forward biased (e.g., above the reverse bias voltage and below forward bias threshold voltage or the voltage potential at the p-diffusion region is higher than the voltage potential at the n-diffusion region). A voltage potential or current may be generated when forward biasing the junction between the P− region 122 and the N+ region 120. The voltage potential or current generated by the second memory cell 12 may be output to a data sense amplifier in the data write and sense circuitry 36 via the corresponding bit line (EN<1>) 32 coupled to the N+ region 120. An amount of voltage potential or current generated may be representative of a data state (e.g., a logic low (binary “0” data state) and/or a logic high (binary “1” data state)) stored in the memory cell 12.

In an exemplary embodiment, a refresh operation may include a write logic high (e.g., binary “1” data state) operation where the control signals may be configured to write a logic high (e.g., binary “1” data state) to one or more selected memory cells 12 of one or more selected rows of the memory cell array 20. For example, the write logic high (e.g., binary “1” data state) operation may be performed on one or more selected rows of the memory cell array 20 or the entire memory cell array 20 and a subsequent write logic low (e.g., binary “0” data state) operation may be performed on one or more selected memory cells 12. In an exemplary embodiment, a voltage potential applied to the N+ region 120 and/or the P+ region 126 of the memory cells 12 may be maintained at 0V. The voltage potential applied to the word line (WL) 28 (e.g., capacitively coupled to the P-region 122) may be lowered to −1.5V. Simultaneously to or subsequent to lowering a voltage potential applied to the word line (WL) 28, a voltage potential applied to the source line (CN) 30 may be lowered to −1.0V.

Under such biasing, the junction between the N+ region 120 and the P− region 122 may be reverse biased and the junction between the P+ region 126 and the N+ region 124 may become forward biased. A logic high (e.g., binary “1” data state) may be written to the P− region 122 (e.g., majority charge carriers injected into the P− region 122 from the P+ region 126) via the forward biased junction between the P+ region 126 and the N+ region 124. As more majority charge carriers are accumulated in the P− region 122, the voltage potential at the P− region 122 may increase to approximately 0.7V to 1.0V above the voltage potential at N+ region 124. At this time, the first bipolar transistor 14a may start to switch to an “ON” state and the current generated by the first bipolar transistor 14a may increase the voltage potential at N+ region 124 due to resistive voltage potential drop on the source line (CN) 30. The increase of the voltage potential at N+ region 124 may lead to a decrease of current flow in the second bipolar transistor 14b, which in turn may cause a decrease in the current load on the carrier injection line (EP) 34 after the write logic high (e.g., binary “1” data state) operation has been completed.

In an exemplary embodiment, a refresh operation may include a write logic low (e.g., binary “0” data state) operation where the control signals may be configured to perform one or more write operations to one or more selected memory cells 12. For example, the write logic low (e.g., binary “0” data state) operation may be performed to one or more selected memory cells 12 after the write logic high (e.g., binary “1” data state) operation in order to deplete the majority charge carriers accumulated in the P− regions 122 of the one or more selected memory cells 12. In an exemplary embodiment, a voltage potential applied to the N+ region 120 via the bit line (EN) 32 may be maintained at 0V in order to perform the write logic low (e.g., binary “0” data state) operation. A voltage potential applied to the N+ region 124 via the source line (CN) 30 may be raised to 1.0V from −1.0V during the write logic high (e.g., binary “1” data state) operation. Subsequent to or simultaneously to raising the voltage potential applied to the N+ region 124 via the source line (CN) 30, a voltage potential applied to the word line (WL) 28 may be raised to approximately 0.5V from −1.5V.

Under such biasing, the junction between the N+ region 120 and the P− region 122 may become forward biased and the first bipolar transistor 14a (e.g., regions 120-124) may be switched to an “ON” state. The majority charge carriers accumulated in the P− region 122 during the write logic high (e.g., binary “1” data state) operation may be removed via the forward biased junction between the N+ region 120 and the P− region 122. After removing the majority charge carriers accumulated in the P-region 122, a logic low (e.g., binary “0” data state) may be written to the memory cell 12.

In order to maintain a logic high (e.g., binary “1” data state) in one or more unselected memory cells 12 during the write logic low (e.g., binary “0” data state) operation, a masking operation may be performed on the one or more unselected memory cells 12. For example, the voltage potential applied to the N+ region 120 of the one or more unselected memory cells 12 may be raised to 1.0V or higher (e.g., 1.2V) in order to prevent the depletion of majority charge carriers accumulated in the P− region 122. Under such biasing, the junction between the N+region 120 and the P− region 122 may not be forward biased and the junction between the P− region 122 and the N+ region 124 may not be forward biased in order to prevent the depletion of majority charge carriers accumulated in the P− region 122 and the logic high (e.g., binary “1” data state) may be maintained in the memory cell 12.

In an exemplary embodiment, a refresh operation may also include a preparation to end operation. During the preparation to end operation, the voltage potentials applied to the memory cells 12 may adjust the amount of majority charge carriers or data state stored in the P− region 122 of the memory cells 12. The voltage potential applied to the word line (WL) 28 (e.g., capacitively coupled to the P− region 122) may be lowered to −1.5V and may determine an amount of majority charge carriers or data state stored in the P− region 122 of the memory cells 12. Also, the voltage potentials applied to other regions (e.g., N+ region 120, N+ region 124, and P+ region 126) may be lowered to and/or maintained at 0V in order to maintain a data state stored in the memory cell 12.

At this point it should be noted that providing a direct injection semiconductor memory device in accordance with the present disclosure as described above typically involves the processing of input data and the generation of output data to some extent. This input data processing and output data generation may be implemented in hardware or software. For example, specific electronic components may be employed in a direct injection semiconductor memory device or similar or related circuitry for implementing the functions associated with providing a direct injection semiconductor memory device in accordance with the present disclosure as described above. Alternatively, one or more processors operating in accordance with instructions may implement the functions associated with providing a direct injection semiconductor memory device in accordance with the present disclosure as described above. If such is the case, it is within the scope of the present disclosure that such instructions may be stored on one or more processor readable media (e.g., a magnetic disk or other storage medium), or transmitted to one or more processors via one or more signals embodied in one or more carrier waves.

The present disclosure is not to be limited in scope by the specific embodiments described herein. Indeed, other various embodiments of and modifications to the present disclosure, in addition to those described herein, will be apparent to those of ordinary skill in the art from the foregoing description and accompanying drawings. Thus, such other embodiments and modifications are intended to fall within the scope of the present disclosure. Further, although the present disclosure has been described herein in the context of a particular implementation in a particular environment for a particular purpose, those of ordinary skill in the art will recognize that its usefulness is not limited thereto and that the present disclosure may be beneficially implemented in any number of environments for any number of purposes. Accordingly, the claims set forth below should be construed in view of the full breadth and spirit of the present disclosure as described herein.

Claims

1. A method for performing a refresh operation on a memory cell of a semiconductor memory device comprising the steps of: performing a plurality of sub-operations on a memory cell in an array of memory cells, wherein the memory cell comprises: a first region coupled to a respective bit line of the array;a second region coupled to a respective source line of the array;a body region spaced apart from and capacitively coupled to a respective word line of the array, wherein the body region is electrically floating and disposed between the first region and the second region; anda third region coupled to a respective carrier injection line of the array;wherein the plurality of sub-operations comprises: a hold sub-operation to maintain a data state stored in the memory cell;a read sub-operation to read a data state stored in the memory cell; anda write sub-operation to write a data state into the memory cell.

2. The method according to claim 1, wherein the hold sub-operation comprises: applying a first voltage potential to the first region via the respective bit line of the array;applying a second voltage potential to the second region via the respective source line of the array;applying a third voltage potential to the respective word line of the array to capacitively couple to the body region;applying a fourth voltage potential to the third region via the respective carrier injection line of the array.

3. The method according to claim 2, wherein the first, second, and fourth voltage potentials are greater than the third voltage potential during the hold sub-operation.

4. The method according to claim 3, wherein the third voltage potential is a negative voltage potential and the first, second, and fourth voltage potentials are zero or positive voltage potentials during the hold sub-operation.

5. The method according to claim 2, further comprising increasing the third voltage potential applied to the respective word line from the third voltage potential applied to the respective word line during the hold sub-operation to perform the read sub-operation.

6. The method according to claim 2, further comprising increasing the second voltage potential applied to the respective source line from the second voltage potential applied to the respective source line during the hold sub-operation to perform the read sub-operation.

7. The method according to claim 2, further comprising increasing the first voltage potential applied to the respective bit line from the first voltage potential applied to the respective bit line during the hold sub-operation in order to reduce a disturbance during the read sub-operation.

8. The method according to claim 7, further comprising increasing the third voltage potential applied to the respective word line from the third voltage potential applied to the respective word line during the hold sub-operation to perform the read sub-operation after reducing the disturbance.

9. The method according to claim 2, further comprising maintaining the third voltage potential applied to the respective word line from the third voltage potential applied to the respective word line during the hold sub-operation to perform the write sub-operation to write a logic high data state into the memory cell.

10. The method according to claim 2, further comprising lowering the second voltage potential applied to the second region via the respective source line from the second voltage potential applied to the second region during the hold sub-operation to perform the write sub-operation to write a logic high data state into the memory cell.

11. The method according to claim 2, further comprising increasing the third voltage potential applied to the respective word line from the third voltage potential applied to the respective word line during the hold sub-operation to perform the write sub-operation to write a logic low data state into the memory cell.

12. The method according to claim 2, further comprising increasing the second voltage potential applied to the respective source line from the second voltage potential applied to the respective source line during the hold sub-operation to perform the write sub-operation to write a logic low data state into the memory cell.

13. The method according to claim 2, further comprising maintaining the first voltage potential applied to the respective bit line from the first voltage potential applied to the respective bit line during the hold sub-operation to perform the write sub-operation to write a logic low data state into the memory cell.

14. The method according to claim 2, further comprising increasing the first voltage potential applied to the respective bit line during the write sub-operation to write a logic low data state into the memory cell from the first voltage potential applied to the respective bit line during the hold sub-operation to maintain a logic high stored in the memory cell.

15. The method according to claim 2, wherein the hold sub-operation is performed before the read sub-operation.

16. The method according to claim 2, wherein the hold sub-operation is performed before the write sub-operation.

17. The method according to claim 2, wherein the hold sub-operation is performed after the read sub-operation.

18. The method according to claim 2, wherein the hold sub-operation is performed after the write sub-operation.

19. The method according to claim 2, wherein the read sub-operation is performed before the write sub-operation.

20. The method according to claim 1, wherein the first region, the body region, and the second region form a first bipolar transistor.

21. The method according to claim 20, wherein the body region, the second region, and the third region form a second bipolar transistor.

22. A method for performing a refresh operation on a memory cell of a semiconductor memory device comprising the steps of: performing a plurality of sub-operations on a memory cell in an array of memory cells, wherein the memory cell comprises: a first region coupled to a respective bit line of the array;a second region coupled to a respective source line of the array;a body region spaced apart from and capacitively coupled to a respective word line of the array, wherein the body region is electrically floating and disposed between the first region and the second region; anda third region coupled to a respective carrier injection line of the array;wherein the plurality of sub-operations comprises: a hold sub-operation to maintain a data state stored in the memory cell;a read sub-operation to read a data state stored in the memory cell; anda write sub-operation to write a logic low data state into the memory cell.

23. A method for performing a refresh operation on a memory cell of a semiconductor memory device comprising the steps of: performing a plurality of sub-operations on a memory cell in an array of memory cells, wherein the memory cell comprises: a first region coupled to a respective bit line of the array;a second region coupled to a respective source line of the array;a body region spaced apart from and capacitively coupled to a respective word line of the array, wherein the body region is electrically floating and disposed between the first region and the second region; anda third region coupled to a respective carrier injection line of the array;wherein the plurality of sub-operations comprises: a hold sub-operation to maintain a data state stored in the memory cell;a read sub-operation to read a data state stored in the memory cell; anda write sub-operation to write a logic high data state into the memory cell.