Patent Application
20250118933
Descriptions are generally related to techniques for improving signal integrity performance for a 3-connector design implemented in a backplane topology.
A 3-connector cabling topology, hereinafter referred to as a 3-connector design, can be one example of a type of backplane topology for a computing platform (e.g., a server). A 3-connector design is often used in data centers to support multiple disk drives (e.g., solid state drives) as this type of backplane topology can be arranged to include clock buffer, enclosure management and hot-plugging functionalities. A 3-connector design includes 3 connectors, a cable assembly and a printed circuit board (PCB). The PCB included in this 3-connector design can be referred to as a hot swap backplane (HSBP).
Increasing data rates required for various types of devices arranged to couple with a backplane topology for a computing platform and use of pulse amplitude modulation with four levels (PAM-4) to transmit data signals can present a challenge from a system and signal integrity point of view when coupling devices within the computing platform via a 3-connector design. For example, 3 connectors, a cable assembly and an HSBP arranged to transmit or receive signals via a signal channel can increase a number of discontinuities in a data signal channel and lead to signal channel losses, crosstalk, and/or reflections.
A 3-connector design is a popular type of backplane topology associated with devices such as, but not limited to, storage devices arranged to operate using communication channels or links according to a Peripheral Component Interconnect Special Interest Group (PCI-SIG) specification such as PCI Express Base Specification, Revision 6.2, originally published in February 2024, herein after referred to as “PCIe 6.x” and/or other earlier or later revisions of the PCIe specification, for example, PCIe 5.x or PCIe 7.x, 8.x, etc. In some examples, storage devices arranged to operate communication channels or links according to PCIe 5.x or PCIe 6.x can also be referred to as PCIe Gen 5 or PCIe Gen 6 storage links. A 3-connector design can include three major components of a baseboard for a central processing unit (CPU), a cable assembly and an HSBP. Typically, a 3-connector design has three connectors, four via transitions, three segments of routing, and one cable assembly. These components of a 3-connector design can result in a complicated and difficult backplane topology from a signal integrity point of view.
Current 3-connector designs typically need about 6 inches of PCB wire/trace routing on the baseboard for routing a storage link to the CPU and 3 inches of PCB wire/trace routing for routing the storage link between socket connectors coupled to an HSBP to support common data center configurations for each disk drive to couple with a CPU through the storage link. The total needed routing for each storage link between a disk drive and the CPU is about 9 inches and a cable assembly coupled between the baseboard and the HSBP is about 20 inches for current 3-connector designs implemented in data centers. Based on best-known circuit and platform assumptions, a maximum PCB trace routing length for a PCIe Gen 6 storage link using ultra-low-loss PCB materials (for both the baseboard and HSBP) is around 7 inches. So current 3-connector designs have PCB trace routing lengths that can be 2 inches too long to support PCIe Gen 6 storage link requirements. Although a 2 inch gap does not seem too large, it can be very expensive to close this 2 inch gap using such techniques that include use of a re-timer device or extremely low-loss PCB materials. A preferred option to close the 2 inch gap would be to optimize a 3-connector design without using an additional active device (e.g., re-timer device) or very expensive PCB materials. Extensive optimizations have been made with current 3-connector designs at the baseboard in terms of socket connector placement in relation to a board layout. However, there may be little to no room left for further baseboard optimizations without fundamental changes of an overall baseboard architecture and/or of form factors of surrounding components, such as CPU, dual in-line modules (DIMMs), voltage regulators, PCIe connectors, etc. However, as described in this disclosure, example techniques to improve signal integrity performance for a 3-connector design through changes to the cable assembly and socket connectors arranged to couple to the HSBP can substantially reduce or eliminate PCB trace routing through the HSBP for a data signal channel routed between pins of connectors on either side of the HSBP. These changes, as describe below, result in a new 3-connector design that can meet PCIe Gen 6 and/or possibly later PCI Gen storage link requirements without using additional active devices and/or expensive PCB materials in the baseboard or the HSBP.
According to some examples, devices 122-1 to 122-8 can be disk drives to include, but are not limited to, solid state drives (SSDs), to couple with one or more CPUs housed in server chassis 110. Devices 122-1 to 122-8, for example, can be arranged in an enterprise and data center SSD form factor (EDSFF) to couple to respective socket connectors on HSBP 124 such as socket connector 123-8. For these examples, computing platform system 100 can be deployed in a data center as part of a data storage service. Examples are not limited to data center deployments or data storage services. Also, examples are not limited to devices 122-1 to 122-8 being disk drives. Other examples can include other types of devices that can be configured to have edge connectors that can be inserted into a socket connector on HSBP 124 such as, but not limited to, a graphic processing unit (GPU) accelerator device or other types of processor accelerator devices that may require high data rates for signals routed between a device and a CPU or processor housed in server chassis 110 using a 3-connector design.
In current 3-connectors designs, socket or receptable connectors can be placed on two sides of an HSBP. The types of socket connectors used on either side can be selected independently and placed on either side with an offset. Typically, to connect all signal paths or channels between the two offset socket connectors, 3 inches of PCB trace routing is needed with two transition vias through the HSBP for each data signal channel. Due to rigidity requirements to allow for insertion of multiple devices in socket connectors on the HSBP, the HSBP can be a relatively thick PCB. For high-speed signal designs (e.g., for PCIe Gen 6 links), at least one of the two transition vias need to be back drilled for stub effect mitigation. PCB trace routing and back drilled vias on the HSBP increase channel loss, reduce signal integrity, increase signal reflections, and contribute to the above-mentioned 2 inch gap to meeting PCIe Gen 6 link requirements using current 3-connector designs.
According to some examples, where new 3-connector design 200 can be designed to couple PCIe Gen 6 links between CPU 201 and a device from among devices 122-1 to 122-8, surface mount technology (SMT) can be used to mount socket connector 125-8 and socket connector 123-8 to HSBP 124 and to mount socket connector 220 to CPU baseboard 210. For these examples, socket connectors 220, 125-8, and 123-8 can be high-density SMT connectors designed according to one or more Small Form Factor—Technology Affiliate (SFF-TA) specifications published by the Storage Networking Industry Association (SNIA). Plug connectors 232 and 234 of cable assembly 230 can also be designed according to one or more SFF-TA specifications in order to mate or physically couple with respective socket connectors 220 and 123-8. Device 122-8 can be configured to include an edge connector (not shown) that can also be designed according to one or more SFF-TA specifications in order to mate or physically couple with socket connector 123-8. For example, socket connectors 220 and 125-8 and plug connectors 232 and 234 of cable assembly 230 can be configured according to SFF-TA-1016, “Internal Unshielded High Speed Connector System”, Rev 1.3, published in November 2024. Meanwhile socket connector 123-8 and the edge connector of device 122-8 can be configured according to SFF-TA-1002, “Protocol Agnostic Multi-Lane High Speed Connector”, Rev 1.5, published in April 2024 or SFF-TA-1020, “Cables and Connector Variants Based on SFF-TA-1002, Rev 1.1, published in November 2023. SFF-TA-1016, SFF-TA-1002, or SFF-TA-1020 can be particularly popular in data center or enterprise server designs. In some examples, use of these standardized connectors in a new 3-connector design can make it possible to select, place and set a pinout arrangement of socket connectors on an HSBP such as socket connectors 125-8 and 123-8 on HSBP 124 that can allow for a mirrored pin configuration that substantially reduce or eliminate PCB trace routing of signal channels 240 through HSBP 124 and enable, for example, PCIe Gen 6 link requirements to be met for this new 3-connector design 200.
Examples are not limited to a 8 to 4 Rx/Tx cable configuration as described above for cable configuration 400. For example, the full 8 Rx/Tx data signal channels could be routed through cable assembly 230 to a single plug connector 234 to couple with a socket connector on HSBP 124. Alternatively, the 8 Rx/Tx data signal channels can be split amongst 4 different plug connectors and routed to those 4 different plug connectors to couple with respective 4 socket connectors on HSBP 124. Also, examples are not limited to 8 Rx/Tx data signal channels being received at plug connector 232. More or less Rx/Tx data signal channels can be received at plug connector 232.
According to some examples, at least a portion of the 38 pins included in socket connector 125-8 can be arranged such that pins to route Rx/Tx data signal channels (e.g., included in signal channels 240) are mirrored as shown in
In some examples, pin-to-signal assignments for plug connector 234-1 are arranged to mate or couple with pins of socket connector 125-8 as mentioned above for socket connector pinout arrangement 600 shown in
Although not shown in
In some examples, at 802, the logic flow 800 can configure a plurality of pins within a housing of a first socket connector to route data signals between pins of a first plug connector and a second plurality of pins of a second socket connector mounted to a first side of an host HSBP of a computing platform, the first plug connector included in a cable assembly having a second plug connector coupled with a processor baseboard socket connector. For these examples, the first socket connector can be socket connector 125-8 that includes the Rx/TX data signal pins depicted in
According to some examples, at 804, logic flow 800 can mount the housing of the first socket connector to a second side of the HSBP, the plurality of pins within the mounted housing can be arranged to mirror the second plurality of pins of the second connector mounted to the first side of the HSBP such that individual data signals routed between the plurality of pins and the second plurality of pins can be routed through respective single vias in the HSBP. For these examples, the housing of socket connector 125-8 can be mounted to the second side of HSBP 124 and the Rx/Tx data signal pins of socket connector 125-8 depicted in
Embodiments herein may be implemented in various types of computing and networking equipment, such as switches, routers, racks, and blade servers such as those employed in a data center and/or server farm environment. The servers used in data centers and server farms can include arrayed server configurations such as rack-based servers or blade servers. These servers are interconnected in communication via various network provisions, such as partitioning sets of servers into Local Area Networks (LANs) with appropriate switching and routing facilities between the LANs to form a private Intranet. For example, cloud hosting facilities may typically employ large data centers with a multitude of servers. A blade comprises a separate computing platform that is configured to perform server-type functions, that is, a “server on a card.” Accordingly, each blade includes components common to conventional servers, including a main printed circuit board (main board) providing internal wiring (e.g., buses) for coupling appropriate integrated circuits (ICs) and other components mounted to the board.
Some examples may include an article of manufacture or at least one computer-readable medium. A computer-readable medium may include a non-transitory storage medium to store logic. In some examples, the non-transitory storage medium may include one or more types of computer-readable storage media capable of storing electronic data, including volatile memory or non-volatile memory, removable or non-removable memory, erasable or non-erasable memory, writeable or re-writeable memory, and so forth. In some examples, the logic may include various software elements, such as software components, programs, applications, computer programs, application programs, system programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, procedures, software interfaces, API, instruction sets, computing code, computer code, code segments, computer code segments, words, values, symbols, or any combination thereof.
According to some examples, a computer-readable medium may include a non-transitory storage medium to store or maintain instructions that when executed by a machine, computing device or system, cause the machine, computing device or system to perform methods and/or operations in accordance with the described examples. The instructions may include any suitable type of code, such as source code, compiled code, interpreted code, executable code, static code, dynamic code, and the like. The instructions may be implemented according to a predefined computer language, manner or syntax, for instructing a machine, computing device or system to perform a certain function. The instructions may be implemented using any suitable high-level, low-level, object-oriented, visual, compiled and/or interpreted programming language.
Some examples may be described using the expression “in one example” or “an example” along with their derivatives. These terms mean that a particular feature, structure, or characteristic described in connection with the example is included in at least one example. The appearances of the phrase “in one example” in various places in the specification are not necessarily all referring to the same example.
Some examples may be described using the expression “coupled” and “connected” along with their derivatives. These terms are not necessarily intended as synonyms for each other. For example, descriptions using the terms “connected” and/or “coupled” may indicate that two or more elements are in direct physical or electrical contact with each other. The term “coupled” or “coupled with”, however, may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other.
To the extent various operations or functions are described herein, they can be described or defined as software code, instructions, configuration, and/or data. The content can be directly executable (“object” or “executable” form), source code, or difference code (“delta” or “patch” code). The software content of what is described herein can be provided via an article of manufacture with the content stored thereon, or via a method of operating a communication interface to send data via the communication interface. A machine readable storage medium can cause a machine to perform the functions or operations described and includes any mechanism that stores information in a form accessible by a machine (e.g., computing device, electronic system, etc.), such as recordable/non-recordable media (e.g., read only memory (ROM), random access memory (RAM), magnetic disk storage media, optical storage media, flash memory devices, etc.). A communication interface includes any mechanism that interfaces to any of a hardwired, wireless, optical, etc., medium to communicate to another device, such as a memory bus interface, a processor bus interface, an Internet connection, a disk controller, etc. The communication interface can be configured by providing configuration parameters and/or sending signals to prepare the communication interface to provide a data signal describing the software content. The communication interface can be accessed via one or more commands or signals sent to the communication interface.
The follow examples pertain to additional examples of technologies disclosed herein.
Example 1. An example socket connector can include a housing configured to be mounted to a first side of an HSBP of a computing platform. The housing can be in a form factor configured to receive a first plug connector of a cable assembly having a second plug connector coupled with a processor baseboard socket connector. The socket connector can also include a plurality of pins within the housing configured to route data signals between pins of the first plug connector and a second plurality of pins of a second socket connector mounted to a second side of the HSBP. The plurality of pins can mirror the second plurality of pins such that individual data signals routed between the plurality of pins and the second plurality of pins are routed through respective single vias in the HSBP.
Example 2. The socket connector of example 1, the second socket connector mounted to the second side of the HSBP can be configured to receive a connector edge of a device and the second plurality of pins are configured to route the data signals to or from the connector edge of the device.
Example 3. The socket connector of example 2, the device can be a memory device, a GPU accelerator device, or a processor accelerator device.
Example 4. The socket connector of example 2, the device can be a memory device configured as an SSD in an enterprise and data center SDD form factor (EDSFF).
Example 5. The socket connector of example 4, the housing in the form factor configured to receive the first plug connector of the cable assembly can include the form factor configured according to an SFF-TA specification to include SFF-TA-1016 and the second socket connector on the second side of the HSBP can be configured according to a second SFF-TA specification to include SFF-TA-1002. For this example, a pinout of the plurality of pins within the housing can cause the plurality of pins within the housing to mirror the second plurality of pins based on an SFF-TA-1002 pinout for the second plurality of pins.
Example 6. The socket connector of example 5, a form factor of the first plug connector of the cable assembly can be configured according to SFF-TA-1016 and a pinout of pins in the first plug connector are based on the pinout of the plurality of pins within the housing. For this example, a form factor of the second plug connector of the cable assembly can be configured according to SFF-TA-1016 and a pinout of pins in the second plug connector can be based on an SFF-TA-1016 pinout.
Example 7. The socket connector of example 1, the HSBP can include a PCB. The housing can be mounted to the first side of the HSBP using SMT and the second socket connector can be mounted to the second side of the HSBP using SMT. For this example, the plurality of pins within the housing can mirror the second plurality of pins such that individual data signals routed between the plurality of pins and the second plurality of pins are routed through respective single vias in the PCB without using PCB trace routing.
Example 8. An example method can include configuring a plurality of pins within a housing of a first socket connector to route data signals between pins of a first plug connector and a second plurality of pins of a second socket connector mounted to a first side of an HSBP of a computing platform. The first plug connector can be included in a cable assembly having a second plug connector coupled with a processor baseboard socket connector. The method can also include mounting the housing of the first socket connector to a second side of the HSBP. The plurality of pins within the mounted housing can be arranged to mirror the second plurality of pins of the second socket connector mounted to the first side of the HSBP such that individual data signals routed between the plurality of pins and the second plurality of pins can be routed through respective single vias in the HSBP.
Example 9. The method of example 8, the second socket connector mounted to the first side of the HSBP can be configured to receive a connector edge of a device and the second plurality of pins are configured to route the data signals to or from the connector edge of the device.
Example 10. The method of example 9, the device can be a memory device, a GPU accelerator device, or a processor accelerator device.
Example 11. The method of example 9, the device can be a memory device configured as an SSD in an enterprise and data center SDD form factor (EDSFF).
Example 12. The method of example 11, the housing can be in a form factor configured to receive the first plug connector of the cable assembly, the housing form factor based on an SFF-TA specification to include SFF-TA-1016 and the second socket connector on the first side of the HSBP can be configured based on a second SFF-TA specification to include SFF-TA-1002. For this example, a pinout of the plurality of pins within the housing can cause the plurality of pins within the housing to mirror the second plurality of pins based on an SFF-TA-1002 pinout for the second plurality of pins.
Example 13. The method of example 12, a form factor of the first plug connector of the cable assembly can be configured based on SFF-TA-1016 and a pinout of pins in the first plug connector can be based on the pinout of the plurality of pins within the housing. For this example, a form factor of the second plug connector of the cable assembly can configured based on SFF-TA-1016 and a pinout of pins in the second plug connector can be based on an SFF-TA-1016 pinout.
Example 14. The method of example 8, the HSBP can include a PCB. Mounting the housing of the first socket connector to the second side of the HSBP can include using SMT and the second socket connector can be mounted to the first side of the HSBP using SMT. The plurality of pins can mirror the second plurality of pins such that individual data signals routed between the plurality of pins and the second plurality of pins can be routed through respective single vias in the PCB without using PCB trace routing.
Example 15. An example system can include a cable assembly having a first plug connector and a second plug connector. The system can also include a first socket connector that includes a housing configured to be mounted to a first side of an HSBP of a computing platform. The housing can be in a form factor configured to receive the first plug connector of the cable assembly. The first socket connector can also include a plurality of pins within the housing configured to route data signals between pins of the first plug connector and a second plurality of pins of second socket connector mounted to a second side of the HSBP. The plurality of pins can mirror the second plurality of pins such that individual data signals routed between the plurality of pins and the second plurality of pins can be routed through respective single vias in the HSBP.
Example 16. The system of example 15, the second socket connector mounted to the second side of the HSBP can be configured to receive a connector edge of a device and the second plurality of pins can be configured to route the data signals to or from the connector edge of the device.
Example 17. The system of example 16, the device can be a memory device, a GPU accelerator device, or a processor accelerator device.
Example 18. The system of example 16, the device can be a memory device configured as an SSD in an enterprise and data center SDD form factor (EDSFF).
Example 19. The system of example 18, the housing in the form factor configured to receive the first plug connector of the cable assembly can include the form factor configured according to an SFF-TA specification to include SFF-TA-1016 and the second socket connector on the second side of the HSBP can be configured according to a second SFF-TA specification to include SFF-TA-1002. A pinout of the plurality of pins within the housing can cause the plurality of pins within the housing to mirror the second plurality of pins based on an SFF-TA-1002 pinout for the second plurality of pins.
Example 20. The system of example 19, a form factor of the first plug connector of the cable assembly can be configured according to SFF-TA-1016 and a pinout of pins in the first plug connector can be based on the pinout of the plurality of pins within the housing. For this example a form factor of the second plug connector of the cable assembly can be configured according to SFF-TA-1016 and a pinout of pins in the second plug connector can be based on an SFF-TA-1016 pinout.
Example 21. The system of example 15, the HSBP includes a PCB, the housing of the first socket connector can be mounted to the first side of the HSBP using SMT and the second socket connector can be mounted to the second side of the HSBP using SMT. For this example, the plurality of pins within the housing can mirror the second plurality of pins such that individual data signals routed between the plurality of pins and the second plurality of pins can be routed through respective single vias in the PCB without using PCB trace routing.
It is emphasized that the Abstract of the Disclosure is provided to comply with 37 C.F.R. Section 1.72(b), requiring an abstract that will allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. In addition, in the foregoing Detailed Description, it can be seen that various features are grouped together in a single example for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed examples require more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed example. Thus, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate example. In the appended claims, the terms “including” and “in which” are used as the plain-English equivalents of the respective terms “comprising” and “wherein,” respectively. Moreover, the terms “first,” “second,” “third,” and so forth, are used merely as labels, and are not intended to impose numerical requirements on their objects.
Although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing the claims.
