Typically, in data centers in which workloads (e.g., applications) are assigned to compute devices for execution on behalf of a customer (e.g., in a cloud data center), an accelerator device, if any, is local to (e.g., on the same board) as a general purpose processor assigned to execute a workload and is capable of providing only a fixed type of acceleration. As such, if the particular application executed by the general purpose processor does not include functions or operations (e.g., tasks) that can take advantage of the acceleration capabilities of the local accelerator device, then the application is executed at an un-accelerated speed and the local accelerator device goes unused during the execution of the application, resulting in wasted resources.
The concepts described herein are illustrated by way of example and not by way of limitation in the accompanying figures. For simplicity and clarity of illustration, elements illustrated in the figures are not necessarily drawn to scale. Where considered appropriate, reference labels have been repeated among the figures to indicate corresponding or analogous elements.
While the concepts of the present disclosure are susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and will be described herein in detail. It should be understood, however, that there is no intent to limit the concepts of the present disclosure to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives consistent with the present disclosure and the appended claims.
References in the specification to “one embodiment,” “an embodiment,” “an illustrative embodiment,” etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may or may not necessarily include that particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described. Additionally, it should be appreciated that items included in a list in the form of “at least one A, B, and C” can mean (A); (B); (C); (A and B); (A and C); (B and C); or (A, B, and C). Similarly, items listed in the form of “at least one of A, B, or C” can mean (A); (B); (C); (A and B); (A and C); (B and C); or (A, B, and C).
The disclosed embodiments may be implemented, in some cases, in hardware, firmware, software, or any combination thereof. The disclosed embodiments may also be implemented as instructions carried by or stored on a transitory or non-transitory machine-readable (e.g., computer-readable) storage medium, which may be read and executed by one or more processors. A machine-readable storage medium may be embodied as any storage device, mechanism, or other physical structure for storing or transmitting information in a form readable by a machine (e.g., a volatile or non-volatile memory, a media disc, or other media device).
In the drawings, some structural or method features may be shown in specific arrangements and/or orderings. However, it should be appreciated that such specific arrangements and/or orderings may not be required. Rather, in some embodiments, such features may be arranged in a different manner and/or order than shown in the illustrative figures. Additionally, the inclusion of a structural or method feature in a particular figure is not meant to imply that such feature is required in all embodiments and, in some embodiments, may not be included or may be combined with other features.
The illustrative data center 100 differs from typical data centers in many ways. For example, in the illustrative embodiment, the circuit boards (“sleds”) on which components such as CPUs, memory, and other components are placed are designed for increased thermal performance In particular, in the illustrative embodiment, the sleds are shallower than typical boards. In other words, the sleds are shorter from the front to the back, where cooling fans are located. This decreases the length of the path that air must to travel across the components on the board. Further, the components on the sled are spaced further apart than in typical circuit boards, and the components are arranged to reduce or eliminate shadowing (i.e., one component in the air flow path of another component). In the illustrative embodiment, processing components such as the processors are located on a top side of a sled while near memory, such as DIMMs, are located on a bottom side of the sled. As a result of the enhanced airflow provided by this design, the components may operate at higher frequencies and power levels than in typical systems, thereby increasing performance. Furthermore, the sleds are configured to blindly mate with power and data communication cables in each rack 102A, 102B, 102C, 102D, enhancing their ability to be quickly removed, upgraded, reinstalled, and/or replaced. Similarly, individual components located on the sleds, such as processors, accelerators, memory, and data storage drives, are configured to be easily upgraded due to their increased spacing from each other. In the illustrative embodiment, the components additionally include hardware attestation features to prove their authenticity.
Furthermore, in the illustrative embodiment, the data center 100 utilizes a single network architecture (“fabric”) that supports multiple other network architectures including Ethernet and Omni-Path. The sleds, in the illustrative embodiment, are coupled to switches via optical fibers, which provide higher bandwidth and lower latency than typical twisted pair cabling (e.g., Category 5, Category 5e, Category 6, etc.). Due to the high bandwidth, low latency interconnections and network architecture, the data center 100 may, in use, pool resources, such as memory, accelerators (e.g., graphics accelerators, FPGAs, ASICs, etc.), and data storage drives that are physically disaggregated, and provide them to compute resources (e.g., processors) on an as needed basis, enabling the compute resources to access the pooled resources as if they were local. The illustrative data center 100 additionally receives utilization information for the various resources, predicts resource utilization for different types of workloads based on past resource utilization, and dynamically reallocates the resources based on this information.
The racks 102A, 102B, 102C, 102D of the data center 100 may include physical design features that facilitate the automation of a variety of types of maintenance tasks. For example, data center 100 may be implemented using racks that are designed to be robotically-accessed, and to accept and house robotically-manipulatable resource sleds. Furthermore, in the illustrative embodiment, the racks 102A, 102B, 102C, 102D include integrated power sources that receive a greater voltage than is typical for power sources. The increased voltage enables the power sources to provide additional power to the components on each sled, enabling the components to operate at higher than typical frequencies.
In various embodiments, dual-mode optical switches may be capable of receiving both Ethernet protocol communications carrying Internet Protocol (IP packets) and communications according to a second, high-performance computing (HPC) link-layer protocol (e.g., Intel's Omni-Path Architecture's, Infiniband) via optical signaling media of an optical fabric. As reflected in
MPCMs 916-1 to 916-7 may be configured to provide inserted sleds with access to power sourced by respective power modules 920-1 to 920-7, each of which may draw power from an external power source 921. In various embodiments, external power source 921 may deliver alternating current (AC) power to rack 902, and power modules 920-1 to 920-7 may be configured to convert such AC power to direct current (DC) power to be sourced to inserted sleds. In some embodiments, for example, power modules 920-1 to 920-7 may be configured to convert 277-volt AC power into 12-volt DC power for provision to inserted sleds via respective MPCMs 916-1 to 916-7. The embodiments are not limited to this example.
MPCMs 916-1 to 916-7 may also be arranged to provide inserted sleds with optical signaling connectivity to a dual-mode optical switching infrastructure 914, which may be the same as—or similar to—dual-mode optical switching infrastructure 514 of
Sled 1004 may also include dual-mode optical network interface circuitry 1026. Dual-mode optical network interface circuitry 1026 may generally comprise circuitry that is capable of communicating over optical signaling media according to each of multiple link-layer protocols supported by dual-mode optical switching infrastructure 914 of
Coupling MPCM 1016 with a counterpart MPCM of a sled space in a given rack may cause optical connector 1016A to couple with an optical connector comprised in the counterpart MPCM. This may generally establish optical connectivity between optical cabling of the sled and dual-mode optical network interface circuitry 1026, via each of a set of optical channels 1025. Dual-mode optical network interface circuitry 1026 may communicate with the physical resources 1005 of sled 1004 via electrical signaling media 1028. In addition to the dimensions of the sleds and arrangement of components on the sleds to provide improved cooling and enable operation at a relatively higher thermal envelope (e.g., 250W), as described above with reference to
As shown in
In another example, in various embodiments, one or more pooled storage sleds 1132 may be included among the physical infrastructure 1100A of data center 1100, each of which may comprise a pool of storage resources that is globally accessible to other sleds via optical fabric 1112 and dual-mode optical switching infrastructure 1114. In some embodiments, such pooled storage sleds 1132 may comprise pools of solid-state storage devices such as solid-state drives (SSDs). In various embodiments, one or more high-performance processing sleds 1134 may be included among the physical infrastructure 1100A of data center 1100. In some embodiments, high-performance processing sleds 1134 may comprise pools of high-performance processors, as well as cooling features that enhance air cooling to yield a higher thermal envelope of up to 250W or more. In various embodiments, any given high-performance processing sled 1134 may feature an expansion connector 1117 that can accept a far memory expansion sled, such that the far memory that is locally available to that high-performance processing sled 1134 is disaggregated from the processors and near memory comprised on that sled. In some embodiments, such a high-performance processing sled 1134 may be configured with far memory using an expansion sled that comprises low-latency SSD storage. The optical infrastructure allows for compute resources on one sled to utilize remote accelerator/FPGA, memory, and/or SSD resources that are disaggregated on a sled located on the same rack or any other rack in the data center. The remote resources can be located one switch jump away or two-switch jumps away in the spine-leaf network architecture described above with reference to
In various embodiments, one or more layers of abstraction may be applied to the physical resources of physical infrastructure 1100A in order to define a virtual infrastructure, such as a software-defined infrastructure 1100B. In some embodiments, virtual computing resources 1136 of software-defined infrastructure 1100B may be allocated to support the provision of cloud services 1140. In various embodiments, particular sets of virtual computing resources 1136 may be grouped for provision to cloud services 1140 in the form of SDI services 1138. Examples of cloud services 1140 may include—without limitation—software as a service (SaaS) services 1142, platform as a service (PaaS) services 1144, and infrastructure as a service (IaaS) services 1146.
In some embodiments, management of software-defined infrastructure 1100B may be conducted using a virtual infrastructure management framework 1150B. In various embodiments, virtual infrastructure management framework 1150B may be designed to implement workload fingerprinting techniques and/or machine-learning techniques in conjunction with managing allocation of virtual computing resources 1136 and/or SDI services 1138 to cloud services 1140. In some embodiments, virtual infrastructure management framework 1150B may use/consult telemetry data in conjunction with performing such resource allocation. In various embodiments, an application/service management framework 1150C may be implemented in order to provide QoS management capabilities for cloud services 1140. The embodiments are not limited in this context.
Referring now to
In the illustrative embodiment, the compute sled 1230 includes a central processing unit (CPU) 1232 (e.g., a processor or other device or circuitry capable of performing a series of operations) that executes a workload 1234 (e.g., an application). The accelerator sled 1240, in the illustrative embodiment, includes multiple accelerator devices 1260, 1262, each of which includes multiple kernels 1270, 1272, 1274, 1276. Each accelerator device 1260, 1262 may be embodied as any device or circuitry (e.g., a specialized processor, an FPGA, an ASIC, a graphics processing unit (GPU), reconfigurable hardware, etc.) capable of accelerating the execution of a function. Each kernel 1270, 1272, 1274, 1276 may be embodied as a set of code or a configuration of a portion of the corresponding accelerator device 1260, 1262 that causes the accelerator device 1260, 1262 to perform one or more accelerated functions (e.g., cryptographic operations, compression operations, etc.). Similarly, the accelerator sled 1242, includes accelerator devices 1264, 1266 and corresponding kernels 1278, 1280, 1282, 1284, similar to the accelerator devices 1260, 1262 and kernels 1270, 1272, 1274, 1276. In operation, the orchestrator server 1220 maintains a database of which kernels are present on which accelerator sleds (e.g., on an accelerator device of one of the accelerator sleds 1240, 1242), receives requests to accelerate portions of workloads (e.g., tasks), determines the type of acceleration (e.g., the function(s) to be accelerated) associated with a task using information in the request, and assigns the task to one or more corresponding accelerator sleds 1240, 1242. Furthermore, to provide additional flexibility, the orchestrator server 1220 may coordinate installing and/or removing kernels from the accelerator sleds to accommodate requests for acceleration of tasks from compute sleds (e.g., the compute sled 1230). As such, the system 1210 provides accelerated functions as a service for workloads, rather than limiting workloads to the acceleration capabilities of the accelerator devices, if any, that may be local to the CPU 1232 (e.g., physically located on the compute sled 1230) where the workload is executed.
Referring now to
As shown in
The compute engine 1302 may be embodied as any type of device or collection of devices capable of performing various compute functions described below. In some embodiments, the compute engine 1302 may be embodied as a single device such as an integrated circuit, an embedded system, a field-programmable gate array (FPGA), a system-on-a-chip (SOC), or other integrated system or device. Additionally, in some embodiments, the compute engine 1302 includes or is embodied as a processor 1304 and a memory 1306. The processor 1304 may be embodied as any type of processor capable of performing the functions described herein. For example, the processor 1304 may be embodied as a single or multi-core processor(s), a microcontroller, or other processor or processing/controlling circuit. In some embodiments, the processor 1304 may be embodied as, include, or be coupled to an FPGA, an application specific integrated circuit (ASIC), reconfigurable hardware or hardware circuitry, or other specialized hardware to facilitate performance of the functions described herein. Additionally, in the illustrative embodiment, the processor 1304 includes a kernel tracker logic unit 1320, which may be embodied as any circuitry or device (e.g., an FPGA, an ASIC, a co-processor, etc.) capable of offloading, from the processor 1304, the operations described herein associated with providing accelerated functions as a service.
The main memory 1306 may be embodied as any type of volatile (e.g., dynamic random access memory (DRAM), etc.) or non-volatile memory or data storage capable of performing the functions described herein. Volatile memory may be a storage medium that requires power to maintain the state of data stored by the medium. Non-limiting examples of volatile memory may include various types of random access memory (RAM), such as dynamic random access memory (DRAM) or static random access memory (SRAM). One particular type of DRAM that may be used in a memory module is synchronous dynamic random access memory (SDRAM). In particular embodiments, DRAM of a memory component may comply with a standard promulgated by JEDEC, such as JESD79F for DDR SDRAM, JESD79-2F for DDR2 SDRAM, JESD79-3F for DDR3 SDRAM, JESD79-4A for DDR4 SDRAM, JESD209 for Low Power DDR (LPDDR), JESD209-2 for LPDDR2, JESD209-3 for LPDDR3, and JESD209-4 for LPDDR4 (these standards are available at www.jedec.org). Such standards (and similar standards) may be referred to as DDR-based standards and communication interfaces of the storage devices that implement such standards may be referred to as DDR-based interfaces.
In one embodiment, the memory device is a block addressable memory device, such as those based on NAND or NOR technologies. A memory device may also include future generation nonvolatile devices, such as a three dimensional crosspoint memory device (e.g., Intel 3D XPoint™ memory), or other byte addressable write-in-place nonvolatile memory devices. In one embodiment, the memory device may be or may include memory devices that use chalcogenide glass, multi-threshold level NAND flash memory, NOR flash memory, single or multi-level Phase Change Memory (PCM), a resistive memory, nanowire memory, ferroelectric transistor random access memory (FeTRAM), anti-ferroelectric memory, magnetoresistive random access memory (MRAM) memory that incorporates memristor technology, resistive memory including the metal oxide base, the oxygen vacancy base and the conductive bridge Random Access Memory (CB-RAM), or spin transfer torque (STT)-MRAM, a spintronic magnetic junction memory based device, a magnetic tunneling junction (MTJ) based device, a DW (Domain Wall) and SOT (Spin Orbit Transfer) based device, a thyristor based memory device, or a combination of any of the above, or other memory. The memory device may refer to the die itself and/or to a packaged memory product.
In some embodiments, 3D crosspoint memory (e.g., Intel 3D XPoint™ memory) may comprise a transistor-less stackable cross point architecture in which memory cells sit at the intersection of word lines and bit lines and are individually addressable and in which bit storage is based on a change in bulk resistance. In some embodiments, all or a portion of the main memory 1306 may be integrated into the processor 1304. In operation, the main memory 1306 may store various software and data used during operation such as task request data, kernel map data, telemetry data, applications, programs, libraries, and drivers.
The compute engine 1302 is communicatively coupled to other components of the orchestrator server 1220 via the I/O subsystem 1308, which may be embodied as circuitry and/or components to facilitate input/output operations with the compute engine 1302 (e.g., with the processor 1304 and/or the main memory 1306) and other components of the orchestrator server 1220. For example, the I/O subsystem 1308 may be embodied as, or otherwise include, memory controller hubs, input/output control hubs, integrated sensor hubs, firmware devices, communication links (e.g., point-to-point links, bus links, wires, cables, light guides, printed circuit board traces, etc.), and/or other components and subsystems to facilitate the input/output operations. In some embodiments, the I/O subsystem 1308 may form a portion of a system-on-a-chip (SoC) and be incorporated, along with one or more of the processor 1304, the main memory 1306, and other components of the orchestrator server 1220, into the compute engine 1302.
The communication circuitry 1310 may be embodied as any communication circuit, device, or collection thereof, capable of enabling communications over the network 1212 between the orchestrator server 1220 and another compute device (e.g., the compute sled 1230, the accelerator sleds 1240, 1242, etc.). The communication circuitry 1310 may be configured to use any one or more communication technology (e.g., wired or wireless communications) and associated protocols (e.g., Ethernet, Bluetooth®, Wi-Fi®, WiMAX, etc.) to effect such communication.
The illustrative communication circuitry 1310 includes a network interface controller (NIC) 1312, which may also be referred to as a host fabric interface (HFI). The NIC 1312 may be embodied as one or more add-in-boards, daughter cards, network interface cards, controller chips, chipsets, or other devices that may be used by the orchestrator server 1220 to connect with another compute device (e.g., the compute sled 1230, the accelerator sleds 1240, 1242 etc.). In some embodiments, the NIC 1312 may be embodied as part of a system-on-a-chip (SoC) that includes one or more processors, or included on a multichip package that also contains one or more processors. In some embodiments, the NIC 1312 may include a local processor (not shown) and/or a local memory (not shown) that are both local to the NIC 1312. In such embodiments, the local processor of the NIC 1312 may be capable of performing one or more of the functions of the compute engine 1302 described herein. Additionally or alternatively, in such embodiments, the local memory of the NIC 1312 may be integrated into one or more components of the orchestrator server 1220 at the board level, socket level, chip level, and/or other levels.
The one or more illustrative data storage devices 1314, may be embodied as any type of devices configured for short-term or long-term storage of data such as, for example, memory devices and circuits, memory cards, hard disk drives, solid-state drives, or other data storage devices. Each data storage device 1314 may include a system partition that stores data and firmware code for the data storage device 1314. Each data storage device 1314 may also include an operating system partition that stores data files and executables for an operating system.
Additionally or alternatively, the orchestrator server 1220 may include one or more peripheral devices 1316. Such peripheral devices 1316 may include any type of peripheral device commonly found in a compute device such as a display, speakers, a mouse, a keyboard, and/or other input/output devices, interface devices, and/or other peripheral devices.
Referring now to
In the illustrative environment 1400, the network communicator 1420, which may be embodied as hardware, firmware, software, virtualized hardware, emulated architecture, and/or a combination thereof as discussed above, is configured to facilitate inbound and outbound network communications (e.g., network traffic, network packets, network flows, etc.) to and from the orchestrator server 1220, respectively. To do so, the network communicator 1420 is configured to receive and process data packets from one system or computing device (e.g., the compute sled 1230) and to prepare and send data packets to another computing device or system (e.g., the accelerator sleds 1240, 1242). Accordingly, in some embodiments, at least a portion of the functionality of the network communicator 1420 may be performed by the communication circuitry 1310, and, in the illustrative embodiment, by the NIC 1312.
The acceleration service manager 1430, which may be embodied as hardware, firmware, software, virtualized hardware, emulated architecture, and/or a combination thereof, is configured to coordinate receiving a request to accelerate a task, determine one or more accelerator sleds 1240, 1242 to perform the task, based on whether the accelerator sled 1240, 1242 already has the kernel associated with the task on an accelerator device or has capacity to configure an accelerator device with the kernel (e.g., in an FPGA slot), and assign the task to the determined accelerator sled(s) 1240, 1242 for execution. To do so, in the illustrative embodiment, the acceleration service manager 1430 includes a task request manager 1432, a kernel manager 1434, and a utilization manager 1436. The task request manager 1432, in the illustrative embodiment, is configured to receive a task request and determine characteristics of the task, including the kernel to be used to accelerate the function(s) of the task, whether the task can be performed by multiple accelerator devices concurrently (e.g., through virtualization, sharing of data through virtualized shared memory, etc.), and/or quality of service targets (e.g., a target latency, a target throughput, etc.). The kernel manager 1434, in the illustrative embodiment is configured to determine, using the kernel map data 1404, which accelerator sled 1240, 1242, if any, already has the kernel (e.g., the accelerator device 1260 of accelerator sled 1240 may already have a slot configured with the kernel). In some embodiments, if the kernel is not present on an accelerator sled 1240, 1242, the kernel manager 1434 coordinates configuring at least one of the accelerator devices of the accelerator sleds 1240, 1242 with the kernel. The utilization manager 1436, in the illustrative embodiment, is configured to collect the telemetry data 1406 and analyze the telemetry data 1406 to assist in determining which accelerator sled 1240, 1242 should be selected to accelerate a task. For example, if multiple accelerator sleds 1240, 1242 presently have the kernel associated with a task request, the utilization manager 1436 may analyze the telemetry data 1406 to determine which accelerator sled 1240, 1242 has enough utilization capacity (e.g., the utilization load satisfies a predefined threshold) to meet a quality of service target (e.g., a target latency to complete the task).
Referring now to
Additionally or alternatively, in receiving the request, the orchestrator server 1220 may receive a request with metadata indicative of target quality of service data (e.g., pursuant to a service level agreement (SLA)), as indicated in block 1516. For example, and as indicated in block 1518, the metadata may indicate a target latency (e.g., a maximum number of milliseconds that may elapse before a particular function is completed). As another example, the metadata may indicate a target throughput (e.g., a minimum number of operations per second), as indicated in block 1520. In the illustrative embodiment, the request identifies the kernel associated with the task, as indicated in block 1522. As such, and as indicated in block 1524, in some embodiments, the orchestrator server 1220 may receive a request that includes the kernel itself, such as in the form of a bitstream, as indicated in block 1526, or executable code embodying the kernel, as indicated in block 1528. In the illustrative embodiment, the request includes an identifier of the kernel (e.g., a universally unique identifier (UUID)), as indicated in block 1530. In block 1532, the orchestrator server 1220 determines the subsequent course of action based on whether a task request was received. If no task request was received, the method 1500 loops back to block 1502 to determine whether to continue to enable accelerated functions as a service. Otherwise, the method 1500 advances to block 1534 of
Referring now to
Referring now to
Subsequently, in block 1570, the orchestrator server 1220 assigns the task associated with the task request to the selected accelerator sled(s) for execution. In doing so, the orchestrator server 1220, in the illustrative embodiment, sends an assignment request to the selected accelerator sled(s), as indicated in block 1572. As indicated in block 1574, the orchestrator server 1220 may send an assignment request that includes metadata from the task request (e.g., all or a portion of the metadata received in block 1508 of
Illustrative examples of the technologies disclosed herein are provided below. An embodiment of the technologies may include any one or more, and any combination of, the examples described below.
Example 1 includes a compute device comprising a compute engine to receive a request for an accelerated task, wherein the task is associated with a kernel usable by an accelerator sled communicatively coupled to the compute device to execute the task; determine, in response to the request and with a database indicative of kernels and associated accelerator sleds, an accelerator sled that includes an accelerator device configured with the kernel associated with the request; and assign the task to the determined accelerator sled for execution.
Example 2 includes the subject matter of Example 1, and wherein to determine an accelerator sled that includes an accelerator device configured with the kernel comprises to determine that an accelerator sled is not presently associated with the kernel; determine an accelerator sled with capacity to be configured with the kernel; send the kernel to the determined accelerator sled for configuration; and update the database to indicate that the kernel is associated with the determined accelerator sled.
Example 3 includes the subject matter of any of Examples 1 and 2, and wherein to determine an accelerator sled with capacity to be configured with the kernel comprises to determine a field programmable gate array (FPGA) with an unused slot to be configured with the kernel.
Example 4 includes the subject matter of any of Examples 1-3, and wherein to determine an accelerator sled that includes an accelerator device configured with the kernel comprises to determine multiple accelerator sleds that each include an accelerator device configured with the kernel; and wherein the compute engine is further to select an accelerator sled that is configured with the kernel and that has a utilization load that satisfies a predefined threshold to execute the task; and wherein to assign the task to the determined accelerator sled comprises to assign the task to the selected accelerator sled.
Example 5 includes the subject matter of any of Examples 1-4, and wherein the compute device is communicatively coupled to the multiple accelerator sleds and the compute engine is further to receive, from each accelerator sled, data indicative of a utilization load associated with each accelerator sled; and wherein to select an accelerator sled that is configured with the kernel and that has a utilization load that satisfies a predefined threshold to execute the task comprises to compare the data received from each accelerator sled to the predefined threshold.
Example 6 includes the subject matter of any of Examples 1-5, and wherein to receive a request for an accelerated task comprises to receive a request that includes metadata indicative of characteristics and parameters of the task.
Example 7 includes the subject matter of any of Examples 1-6, and wherein to receive a request that includes metadata indicative of characteristics and parameters of the task comprises to receive a request that includes metadata indicative of a target quality of service associated with the task; wherein to determine an accelerator sled that includes an accelerator device configured with the kernel comprises to determine multiple accelerator sleds that each include an accelerator device configured with the kernel; and wherein the compute engine is further to select an accelerator sled that is configured with the kernel and that has a utilization load that satisfies a predefined threshold associated with the target quality of service to execute the task.
Example 8 includes the subject matter of any of Examples 1-7, and wherein to receive a request that includes metadata indicative of characteristics and parameters of the task comprises to receive a request that includes metadata indicative of virtualization capabilities of the task.
Example 9 includes the subject matter of any of Examples 1-8, and wherein to receive a request that includes metadata indicative of characteristics and parameters of the task comprises to receive a request that includes metadata indicative of concurrent execution capabilities of the task; and wherein to assign the task comprises to assign the task to multiple accelerator sleds for concurrent execution.
Example 10 includes the subject matter of any of Examples 1-9, and wherein to assign the task to multiple accelerator sleds for concurrent execution comprises to send an assignment request to the multiple accelerator sleds, wherein the assignment request includes identifiers of the multiple accelerator sleds assigned to the task to enable data to be shared among the assigned accelerator sleds as the task is concurrently executed.
Example 11 includes the subject matter of any of Examples 1-10, and wherein to assign the task to multiple accelerator sleds for concurrent execution comprises to send an assignment request to the multiple accelerator sleds, wherein the assignment request includes shared virtual memory address data usable by the multiple accelerator sleds to share data in virtual memory as the task is concurrently executed.
Example 12 includes the subject matter of any of Examples 1-11, and wherein to receive the request comprises to receive a request that includes an identifier of the kernel; and wherein to determine, in response to the request and with a database indicative of kernels and associated accelerator sleds, an accelerator sled that includes an accelerator device configured with the kernel associated with the request comprises to compare the received identifier to kernel identifiers in the database.
Example 13 includes the subject matter of any of Examples 1-12, and wherein to receive the request comprises to receive a request that includes the kernel; and wherein to determine, in response to the request and with a database indicative of kernels and associated accelerator sleds, an accelerator sled that includes an accelerator device configured with the kernel associated with the request comprises to obtain a hash of the received kernel; and compare the hash to kernel identifiers in the database.
Example 14 includes the subject matter of any of Examples 1-13, and wherein to receive the request comprises to receive the request from a compute sled executing a workload associated with the task.
Example 15 includes a method comprising receiving, by a compute device, a request for an accelerated task, wherein the task is associated with a kernel usable by an accelerator sled communicatively coupled to the compute device to execute the task; determining, by the compute device and in response to the request and with a database indicative of kernels and associated accelerator sleds, an accelerator sled that includes an accelerator device configured with the kernel associated with the request; and assigning, by the compute device, the task to the determined accelerator sled for execution.
Example 16 includes the subject matter of Example 15, and wherein determining an accelerator sled that includes an accelerator device configured with the kernel comprises determining that an accelerator sled is not presently associated with the kernel; determining an accelerator sled with capacity to be configured with the kernel; sending the kernel to the determined accelerator sled for configuration; and updating the database to indicate that the kernel is associated with the determined accelerator sled.
Example 17 includes the subject matter of any of Examples 15 and 16, and wherein determining an accelerator sled with capacity to be configured with the kernel comprises determining a field programmable gate array (FPGA) with an unused slot to be configured with the kernel.
Example 18 includes the subject matter of any of Examples 15-17, and wherein determining an accelerator sled that includes an accelerator device configured with the kernel comprises determining multiple accelerator sleds that each include an accelerator device configured with the kernel; and the method further comprising selecting, by the compute device, an accelerator sled that is configured with the kernel and that has a utilization load that satisfies a predefined threshold to execute the task; and wherein assigning the task to the determined accelerator sled comprises assigning the task to the selected accelerator sled.
Example 19 includes the subject matter of any of Examples 15-18, and wherein the compute device is communicatively coupled to the multiple accelerator sleds, the method further comprising receiving, by the compute device and from each accelerator sled, data indicative of a utilization load associated with each accelerator sled; and wherein selecting an accelerator sled that is configured with the kernel and that has a utilization load that satisfies a predefined threshold to execute the task comprises comparing the data received from each accelerator sled to the predefined threshold.
Example 20 includes the subject matter of any of Examples 15-19, and wherein receiving a request for an accelerated task comprises receiving a request that includes metadata indicative of characteristics and parameters of the task.
Example 21 includes the subject matter of any of Examples 15-20, and wherein receiving a request that includes metadata indicative of characteristics and parameters of the task comprises receiving a request that includes metadata indicative of a target quality of service associated with the task; and wherein determining an accelerator sled that includes an accelerator device configured with the kernel comprises determining multiple accelerator sleds that each include an accelerator device configured with the kernel; and the method further comprising selecting, by the compute device, an accelerator sled that is configured with the kernel and that has a utilization load that satisfies a predefined threshold associated with the target quality of service to execute the task.
Example 22 includes the subject matter of any of Examples 15-21, and wherein receiving a request that includes metadata indicative of characteristics and parameters of the task comprises receiving a request that includes metadata indicative of virtualization capabilities of the task.
Example 23 includes the subject matter of any of Examples 15-22, and wherein receiving a request that includes metadata indicative of characteristics and parameters of the task comprises receiving a request that includes metadata indicative of concurrent execution capabilities of the task; and wherein assigning the task comprises assigning the task to multiple accelerator sleds for concurrent execution.
Example 24 includes the subject matter of any of Examples 15-23, and wherein assigning the task to multiple accelerator sleds for concurrent execution comprises sending an assignment request to the multiple accelerator sleds, wherein the assignment request includes identifiers of the multiple accelerator sleds assigned to the task to enable data to be shared among the assigned accelerator sleds as the task is concurrently executed.
Example 25 includes the subject matter of any of Examples 15-24, and wherein assigning the task to multiple accelerator sleds for concurrent execution comprises sending an assignment request to the multiple accelerator sleds, wherein the assignment request includes shared virtual memory address data usable by the multiple accelerator sleds to share data in virtual memory as the task is concurrently executed.
Example 26 includes the subject matter of any of Examples 15-25, and wherein receiving the request comprises receiving a request that includes an identifier of the kernel; and wherein determining, in response to the request and with a database indicative of kernels and associated accelerator sleds, an accelerator sled that includes an accelerator device configured with the kernel associated with the request comprises comparing the received identifier to kernel identifiers in the database.
Example 27 includes the subject matter of any of Examples 15-26, and wherein receiving the request comprises receiving a request that includes the kernel; and wherein determining, in response to the request and with a database indicative of kernels and associated accelerator sleds, an accelerator sled that includes an accelerator device configured with the kernel associated with the request comprises obtaining a hash of the received kernel; and comparing the hash to kernel identifiers in the database.
Example 28 includes the subject matter of any of Examples 15-27, and wherein receiving the request comprises receiving the request from a compute sled executing a workload associated with the task.
Example 29 includes one or more machine-readable storage media comprising a plurality of instructions stored thereon that, in response to being executed, cause a compute device to perform the method of any of Examples 15-28.
Example 30 includes a compute device comprising means for performing the method of any of Examples 15-28.
Example 31 includes a compute device comprising one or more processors; one or more memory devices having stored therein a plurality of instructions that, when executed by the one or more processors, cause the network switch to perform the method of any of Examples 15-28.
Example 32 includes a compute device comprising network communicator circuitry to receive a request for an accelerated task, wherein the task is associated with a kernel usable by an accelerator sled communicatively coupled to the compute device to execute the task; and acceleration service manager circuitry to determine, in response to the request and with a database indicative of kernels and associated accelerator sleds, an accelerator sled that includes an accelerator device configured with the kernel associated with the request; and assign the task to the determined accelerator sled for execution.
Example 33 includes the subject matter of Example 32, and wherein to determine an accelerator sled that includes an accelerator device configured with the kernel comprises to determine that an accelerator sled is not presently associated with the kernel; determine an accelerator sled with capacity to be configured with the kernel; send the kernel to the determined accelerator sled for configuration; and update the database to indicate that the kernel is associated with the determined accelerator sled.
Example 34 includes the subject matter of any of Examples 32 and 33, and wherein to determine an accelerator sled with capacity to be configured with the kernel comprises to determine a field programmable gate array (FPGA) with an unused slot to be configured with the kernel.
Example 35 includes the subject matter of any of Examples 32-34, and wherein to determine an accelerator sled that includes an accelerator device configured with the kernel comprises to determine multiple accelerator sleds that each include an accelerator device configured with the kernel; and wherein the acceleration service manager circuitry is further to select an accelerator sled that is configured with the kernel and that has a utilization load that satisfies a predefined threshold to execute the task; and wherein to assign the task to the determined accelerator sled comprises to assign the task to the selected accelerator sled.
Example 36 includes the subject matter of any of Examples 32-35, and wherein the compute device is communicatively coupled to the multiple accelerator sleds and the acceleration service manager circuitry is further to receive, from each accelerator sled, data indicative of a utilization load associated with each accelerator sled; and wherein to select an accelerator sled that is configured with the kernel and that has a utilization load that satisfies a predefined threshold to execute the task comprises to compare the data received from each accelerator sled to the predefined threshold.
Example 37 includes the subject matter of any of Examples 32-36, and wherein to receive a request for an accelerated task comprises to receive a request that includes metadata indicative of characteristics and parameters of the task.
Example 38 includes the subject matter of any of Examples 32-37, and wherein to receive a request that includes metadata indicative of characteristics and parameters of the task comprises to receive a request that includes metadata indicative of a target quality of service associated with the task; wherein to determine an accelerator sled that includes an accelerator device configured with the kernel comprises to determine multiple accelerator sleds that each include an accelerator device configured with the kernel; and wherein the acceleration service manager circuitry is further to select an accelerator sled that is configured with the kernel and that has a utilization load that satisfies a predefined threshold associated with the target quality of service to execute the task.
Example 39 includes the subject matter of any of Examples 32-38, and wherein to receive a request that includes metadata indicative of characteristics and parameters of the task comprises to receive a request that includes metadata indicative of virtualization capabilities of the task.
Example 40 includes the subject matter of any of Examples 32-39, and wherein to receive a request that includes metadata indicative of characteristics and parameters of the task comprises to receive a request that includes metadata indicative of concurrent execution capabilities of the task; and wherein to assign the task comprises to assign the task to multiple accelerator sleds for concurrent execution.
Example 41 includes the subject matter of any of Examples 32-40, and wherein to assign the task to multiple accelerator sleds for concurrent execution comprises to send an assignment request to the multiple accelerator sleds, wherein the assignment request includes identifiers of the multiple accelerator sleds assigned to the task to enable data to be shared among the assigned accelerator sleds as the task is concurrently executed.
Example 42 includes the subject matter of any of Examples 32-41, and wherein to assign the task to multiple accelerator sleds for concurrent execution comprises to send an assignment request to the multiple accelerator sleds, wherein the assignment request includes shared virtual memory address data usable by the multiple accelerator sleds to share data in virtual memory as the task is concurrently executed.
Example 43 includes the subject matter of any of Examples 32-42, and wherein to receive the request comprises to receive a request that includes an identifier of the kernel; and wherein to determine, in response to the request and with a database indicative of kernels and associated accelerator sleds, an accelerator sled that includes an accelerator device configured with the kernel associated with the request comprises to compare the received identifier to kernel identifiers in the database.
Example 44 includes the subject matter of any of Examples 32-43, and wherein to receive the request comprises to receive a request that includes the kernel; and wherein to determine, in response to the request and with a database indicative of kernels and associated accelerator sleds, an accelerator sled that includes an accelerator device configured with the kernel associated with the request comprises to obtain a hash of the received kernel; and compare the hash to kernel identifiers in the database.
Example 45 includes the subject matter of any of Examples 32-44, and wherein to receive the request comprises to receive the request from a compute sled executing a workload associated with the task.
Example 46 includes a compute device comprising circuitry for receiving a request for an accelerated task, wherein the task is associated with a kernel usable by an accelerator sled communicatively coupled to the compute device to execute the task; means for determining, in response to the request and with a database indicative of kernels and associated accelerator sleds, an accelerator sled that includes an accelerator device configured with the kernel associated with the request; and circuitry for assigning, by the compute device, the task to the determined accelerator sled for execution.
Example 47 includes the subject matter of Example 46, and wherein the means for determining an accelerator sled that includes an accelerator device configured with the kernel comprises circuitry for determining that an accelerator sled is not presently associated with the kernel; circuitry for determining an accelerator sled with capacity to be configured with the kernel; circuitry for sending the kernel to the determined accelerator sled for configuration; and circuitry for updating the database to indicate that the kernel is associated with the determined accelerator sled.
Example 48 includes the subject matter of any of Examples 46 and 47, and wherein the circuitry for determining an accelerator sled with capacity to be configured with the kernel comprises circuitry for determining a field programmable gate array (FPGA) with an unused slot to be configured with the kernel.
Example 49 includes the subject matter of any of Examples 46-48, and wherein the means for determining an accelerator sled that includes an accelerator device configured with the kernel comprises circuitry for determining multiple accelerator sleds that each include an accelerator device configured with the kernel; and the compute device further comprising circuitry for selecting an accelerator sled that is configured with the kernel and that has a utilization load that satisfies a predefined threshold to execute the task; and wherein the circuitry for assigning the task to the determined accelerator sled comprises circuitry for assigning the task to the selected accelerator sled.
Example 50 includes the subject matter of any of Examples 46-49, and wherein the compute device is communicatively coupled to the multiple accelerator sleds, the compute device further comprising circuitry for receiving, from each accelerator sled, data indicative of a utilization load associated with each accelerator sled; and wherein the means for selecting an accelerator sled that is configured with the kernel and that has a utilization load that satisfies a predefined threshold to execute the task comprises circuitry for comparing the data received from each accelerator sled to the predefined threshold.
Example 51 includes the subject matter of any of Examples 46-50, and wherein the circuitry for receiving a request for an accelerated task comprises circuitry for receiving a request that includes metadata indicative of characteristics and parameters of the task.
Example 52 includes the subject matter of any of Examples 46-51, and wherein the circuitry for receiving a request that includes metadata indicative of characteristics and parameters of the task comprises circuitry for receiving a request that includes metadata indicative of a target quality of service associated with the task; and wherein the means for determining an accelerator sled that includes an accelerator device configured with the kernel comprises circuitry for determining multiple accelerator sleds that each include an accelerator device configured with the kernel; and the compute device further comprising circuitry for selecting an accelerator sled that is configured with the kernel and that has a utilization load that satisfies a predefined threshold associated with the target quality of service to execute the task.
Example 53 includes the subject matter of any of Examples 46-52, and wherein the circuitry for receiving a request that includes metadata indicative of characteristics and parameters of the task comprises circuitry for receiving a request that includes metadata indicative of virtualization capabilities of the task.
Example 54 includes the subject matter of any of Examples 46-53, and wherein the circuitry for receiving a request that includes metadata indicative of characteristics and parameters of the task comprises circuitry for receiving a request that includes metadata indicative of concurrent execution capabilities of the task; and wherein the circuitry for assigning the task comprises circuitry for assigning the task to multiple accelerator sleds for concurrent execution.
Example 55 includes the subject matter of any of Examples 46-54, and wherein the circuitry for assigning the task to multiple accelerator sleds for concurrent execution comprises circuitry for sending an assignment request to the multiple accelerator sleds, wherein the assignment request includes identifiers of the multiple accelerator sleds assigned to the task to enable data to be shared among the assigned accelerator sleds as the task is concurrently executed.
Example 56 includes the subject matter of any of Examples 46-55, and wherein the circuitry for assigning the task to multiple accelerator sleds for concurrent execution comprises sending an assignment request to the multiple accelerator sleds, wherein the assignment request includes shared virtual memory address data usable by the multiple accelerator sleds to share data in virtual memory as the task is concurrently executed.
Example 57 includes the subject matter of any of Examples 46-56, and wherein the circuitry for receiving the request comprises circuitry for receiving a request that includes an identifier of the kernel; and wherein the means for determining, in response to the request and with a database indicative of kernels and associated accelerator sleds, an accelerator sled that includes an accelerator device configured with the kernel associated with the request comprises circuitry for comparing the received identifier to kernel identifiers in the database.
Example 58 includes the subject matter of any of Examples 46-57, and wherein the circuitry for receiving the request comprises circuitry for receiving a request that includes the kernel; and wherein the means for determining, in response to the request and with a database indicative of kernels and associated accelerator sleds, an accelerator sled that includes an accelerator device configured with the kernel associated with the request comprises circuitry for obtaining a hash of the received kernel; and circuitry for comparing the hash to kernel identifiers in the database.
Example 59 includes the subject matter of any of Examples 46-58, and wherein the circuitry for receiving the request comprises circuitry for receiving the request from a compute sled executing a workload associated with the task.
Number | Date | Country | Kind |
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201741030632 | Aug 2017 | IN | national |
The present application claims the benefit of U.S. Provisional Patent Application No. 62/427,268, filed Nov. 29, 2016, and Indian Provisional Patent Application No. 201741030632, filed Aug. 30, 2017.
Number | Name | Date | Kind |
---|---|---|---|
6367018 | Jain | Apr 2002 | B1 |
7415022 | Kadambi et al. | Aug 2008 | B2 |
7835388 | Hu | Nov 2010 | B2 |
8248928 | Wang et al. | Aug 2012 | B1 |
9026765 | Marshak et al. | May 2015 | B1 |
9859918 | Gopal | Jan 2018 | B1 |
9929747 | Gopal | Mar 2018 | B2 |
9936613 | Adiletta | Apr 2018 | B2 |
9954552 | Gopal | Apr 2018 | B2 |
9973207 | Gopal | May 2018 | B2 |
10033404 | Cutter | Jul 2018 | B2 |
10034407 | Miller | Jul 2018 | B2 |
10045098 | Adiletta | Aug 2018 | B2 |
10070207 | Adiletta et al. | Sep 2018 | B2 |
10085358 | Adiletta | Sep 2018 | B2 |
10091904 | Miller | Oct 2018 | B2 |
10116327 | Cutter | Oct 2018 | B2 |
10191684 | Gopal | Jan 2019 | B2 |
10234833 | Ahuja | Mar 2019 | B2 |
10263637 | Gopal | Apr 2019 | B2 |
10268412 | Guilford | Apr 2019 | B2 |
10313769 | Miller | Jun 2019 | B2 |
10334334 | Miller | Jun 2019 | B2 |
10348327 | Adiletta | Jul 2019 | B2 |
10349152 | Adiletta | Jul 2019 | B2 |
10356495 | Adiletta | Jul 2019 | B2 |
10368148 | Kumar | Jul 2019 | B2 |
10390114 | Schmisseur | Aug 2019 | B2 |
10397670 | Gorius | Aug 2019 | B2 |
10411729 | Miller | Sep 2019 | B2 |
10448126 | Gilsdorf | Oct 2019 | B2 |
10461774 | Balle | Oct 2019 | B2 |
10469252 | Schmisseur | Nov 2019 | B2 |
10474460 | Adiletta | Nov 2019 | B2 |
10476670 | Schmisseur | Nov 2019 | B2 |
10489156 | Munoz | Nov 2019 | B2 |
10542333 | Miller | Jan 2020 | B2 |
20060184670 | Beeson et al. | Aug 2006 | A1 |
20100191823 | Archer et al. | Jul 2010 | A1 |
20110228767 | Singla et al. | Sep 2011 | A1 |
20120054770 | Krishnamurthy et al. | Mar 2012 | A1 |
20120099863 | Xu et al. | Apr 2012 | A1 |
20120207139 | Husted et al. | Aug 2012 | A1 |
20120230343 | Schrum, Jr. | Sep 2012 | A1 |
20130179485 | Chapman et al. | Jul 2013 | A1 |
20130232495 | Rossbach et al. | Sep 2013 | A1 |
20140012961 | Pope | Jan 2014 | A1 |
20150007182 | Rossbach et al. | Jan 2015 | A1 |
20150229529 | Engebretsen | Aug 2015 | A1 |
20150281065 | Liljenstolpe | Oct 2015 | A1 |
20150333824 | Swinkels et al. | Nov 2015 | A1 |
20150334867 | Faw et al. | Nov 2015 | A1 |
20160127191 | Nair | May 2016 | A1 |
20160147592 | Guddeti | May 2016 | A1 |
20160164739 | Skalecki | Jun 2016 | A1 |
20160231939 | Cannata et al. | Aug 2016 | A1 |
20160234580 | Clarke et al. | Aug 2016 | A1 |
20170046179 | Teh et al. | Feb 2017 | A1 |
20170070431 | Nidumolu et al. | Mar 2017 | A1 |
20170116004 | Devegowda et al. | Apr 2017 | A1 |
20170150621 | Breakstone et al. | May 2017 | A1 |
20170223436 | Moynihan et al. | Aug 2017 | A1 |
20170257970 | Alleman et al. | Sep 2017 | A1 |
20170279705 | Lin et al. | Sep 2017 | A1 |
20170317945 | Guo et al. | Nov 2017 | A1 |
20180014306 | Adiletta | Jan 2018 | A1 |
20180014757 | Kumar | Jan 2018 | A1 |
20180017700 | Adiletta | Jan 2018 | A1 |
20180024578 | Ahuja | Jan 2018 | A1 |
20180024739 | Schmisseur | Jan 2018 | A1 |
20180024740 | Miller | Jan 2018 | A1 |
20180024752 | Miller | Jan 2018 | A1 |
20180024756 | Miller | Jan 2018 | A1 |
20180024764 | Miller | Jan 2018 | A1 |
20180024771 | Miller | Jan 2018 | A1 |
20180024775 | Miller | Jan 2018 | A1 |
20180024776 | Miller | Jan 2018 | A1 |
20180024838 | Nachimuthu | Jan 2018 | A1 |
20180024860 | Balle | Jan 2018 | A1 |
20180024861 | Balle | Jan 2018 | A1 |
20180024864 | Wilde | Jan 2018 | A1 |
20180024867 | Gilsdorf | Jan 2018 | A1 |
20180024932 | Nachimuthu | Jan 2018 | A1 |
20180024947 | Miller | Jan 2018 | A1 |
20180024957 | Nachimuthu | Jan 2018 | A1 |
20180024958 | Nachimuthu | Jan 2018 | A1 |
20180024960 | Wagh | Jan 2018 | A1 |
20180025299 | Kumar | Jan 2018 | A1 |
20180026652 | Cutter | Jan 2018 | A1 |
20180026653 | Cutter | Jan 2018 | A1 |
20180026654 | Gopal | Jan 2018 | A1 |
20180026655 | Gopal | Jan 2018 | A1 |
20180026656 | Gopal | Jan 2018 | A1 |
20180026800 | Munoz | Jan 2018 | A1 |
20180026835 | Nachimuthu | Jan 2018 | A1 |
20180026849 | Guim | Jan 2018 | A1 |
20180026851 | Adiletta | Jan 2018 | A1 |
20180026868 | Guim | Jan 2018 | A1 |
20180026882 | Gorius | Jan 2018 | A1 |
20180026904 | Van De Groenendaal | Jan 2018 | A1 |
20180026905 | Balle | Jan 2018 | A1 |
20180026906 | Balle | Jan 2018 | A1 |
20180026907 | Miller | Jan 2018 | A1 |
20180026908 | Nachimuthu | Jan 2018 | A1 |
20180026910 | Balle | Jan 2018 | A1 |
20180026912 | Guim | Jan 2018 | A1 |
20180026913 | Balle | Jan 2018 | A1 |
20180026918 | Kumar | Jan 2018 | A1 |
20180027055 | Balle | Jan 2018 | A1 |
20180027057 | Balle | Jan 2018 | A1 |
20180027058 | Balle | Jan 2018 | A1 |
20180027059 | Miller | Jan 2018 | A1 |
20180027060 | Metsch | Jan 2018 | A1 |
20180027062 | Bernat | Jan 2018 | A1 |
20180027063 | Nachimuthu | Jan 2018 | A1 |
20180027066 | Van De Groenendaal | Jan 2018 | A1 |
20180027067 | Guim | Jan 2018 | A1 |
20180027093 | Guim | Jan 2018 | A1 |
20180027312 | Adiletta | Jan 2018 | A1 |
20180027313 | Adiletta | Jan 2018 | A1 |
20180027376 | Kumar | Jan 2018 | A1 |
20180027679 | Schmisseur | Jan 2018 | A1 |
20180027680 | Kumar | Jan 2018 | A1 |
20180027682 | Adiletta | Jan 2018 | A1 |
20180027684 | Miller | Jan 2018 | A1 |
20180027685 | Miller | Jan 2018 | A1 |
20180027686 | Adiletta | Jan 2018 | A1 |
20180027687 | Adiletta | Jan 2018 | A1 |
20180027688 | Adiletta | Jan 2018 | A1 |
20180027703 | Adiletta | Jan 2018 | A1 |
20180266510 | Gopal | Jan 2018 | A1 |
20180077235 | Nachimuthu | Mar 2018 | A1 |
20180150240 | Bernat | May 2018 | A1 |
20180150256 | Kumar | May 2018 | A1 |
20180150293 | Nachimuthu | May 2018 | A1 |
20180150298 | Balle | May 2018 | A1 |
20180150299 | Balle | May 2018 | A1 |
20180150330 | Bernat | May 2018 | A1 |
20180150334 | Bernat et al. | May 2018 | A1 |
20180150343 | Bernat | May 2018 | A1 |
20180150372 | Nachimuthu | May 2018 | A1 |
20180150391 | Mitchel | May 2018 | A1 |
20180150471 | Gopal | May 2018 | A1 |
20180150644 | Khanna | May 2018 | A1 |
20180151975 | Aoki | May 2018 | A1 |
20180152200 | Guilford | May 2018 | A1 |
20180152201 | Gopal | May 2018 | A1 |
20180152202 | Gopal | May 2018 | A1 |
20180152317 | Chang | May 2018 | A1 |
20180152366 | Cornett | May 2018 | A1 |
20180152383 | Burres | May 2018 | A1 |
20180152540 | Niell | May 2018 | A1 |
20180205392 | Gopal | Jul 2018 | A1 |
20190014396 | Adiletta | Jan 2019 | A1 |
20190021182 | Adiletta | Jan 2019 | A1 |
20190034102 | Miller | Jan 2019 | A1 |
20190034383 | Schmisseur | Jan 2019 | A1 |
20190034490 | Yap | Jan 2019 | A1 |
20190035483 | Schmisseur | Jan 2019 | A1 |
20190042090 | Raghunath | Feb 2019 | A1 |
20190042091 | Raghunath | Feb 2019 | A1 |
20190042122 | Schmisseur | Feb 2019 | A1 |
20190042126 | Sen | Feb 2019 | A1 |
20190042136 | Nachimuthu | Feb 2019 | A1 |
20190042234 | Bernat | Feb 2019 | A1 |
20190042277 | Nachimuthu | Feb 2019 | A1 |
20190042408 | Schmisseur | Feb 2019 | A1 |
20190042611 | Yap | Feb 2019 | A1 |
20190044809 | Willis | Feb 2019 | A1 |
20190044849 | Ganguli | Feb 2019 | A1 |
20190044859 | Sundar | Feb 2019 | A1 |
20190052457 | Connor | Feb 2019 | A1 |
20190062053 | Jensen | Feb 2019 | A1 |
20190065083 | Sen | Feb 2019 | A1 |
20190065112 | Schmisseur | Feb 2019 | A1 |
20190065172 | Nachimuthu | Feb 2019 | A1 |
20190065212 | Kumar | Feb 2019 | A1 |
20190065231 | Schmisseur | Feb 2019 | A1 |
20190065253 | Bernat | Feb 2019 | A1 |
20190065260 | Balle | Feb 2019 | A1 |
20190065261 | Narayan | Feb 2019 | A1 |
20190065281 | Bernat et al. | Feb 2019 | A1 |
20190065290 | Custodio | Feb 2019 | A1 |
20190065401 | Dormitzer | Feb 2019 | A1 |
20190065415 | Nachimuthu | Feb 2019 | A1 |
20190067848 | Aoki | Feb 2019 | A1 |
20190068444 | Grecco | Feb 2019 | A1 |
20190068464 | Bernat | Feb 2019 | A1 |
20190068466 | Chagam | Feb 2019 | A1 |
20190068509 | Hyatt | Feb 2019 | A1 |
20190068521 | Kumar | Feb 2019 | A1 |
20190068523 | Chagam | Feb 2019 | A1 |
20190068693 | Bernat | Feb 2019 | A1 |
20190068696 | Sen | Feb 2019 | A1 |
20190068698 | Kumar | Feb 2019 | A1 |
20190069433 | Balle | Feb 2019 | A1 |
20190069434 | Aoki | Feb 2019 | A1 |
20190196824 | Liu | Jun 2019 | A1 |
20190307014 | Adiletta | Oct 2019 | A1 |
20190342642 | Adiletta | Nov 2019 | A1 |
20190342643 | Adiletta | Nov 2019 | A1 |
20190387291 | Adiletta | Dec 2019 | A1 |
Entry |
---|
Diamantopoulos et al. “High-level Synthesizable Dataflow MapReduce Accelerator for FPGA-coupled Data Centers”, 2015 IEEE, pp. 26-33. |
Burdeniuk et al. “An Event-Assisted Sequencer to Accelerate Matrix Algorithms”, 2010 IEEE, pp. 158-163. |
Ding et al. “A Unified OpenCL-flavor Programming Model with Scalable Hybrid Hardware Platform on FPGAs”, 2014 IEEE, 7 pages. |
Asiatici et al. “Virtualized Execution Runtime for FPGA Accelerators in the Cloud”, 2017 IEEE, pp. 1900-1910. |
Fahmy Suhaib A et al: “Virtualized FPGA Accelerators for Efficient Cloud Computing”, 2015 IEEE 7th International Conference on Cloud Computing Technology and Science (Cloudcom), IEEE, Nov. 30, 2015 (Nov. 30, 2015), pp. 430-435. |
Extended European search report for European patent application No. 1819345.0, dated Feb. 11, 2019 (8 pages). |
Communication pursuant to Article 94(3) for European Patent Application No. 18191345.0, dated Apr. 16, 2021. |
Extended European Search Report for European Patent Application No. 20217841.4, dated Apr. 16, 2021. |
International Preliminary Report on Patentability for PCT Application No. PCT/US2017/038552, dated Jan. 22, 2019. |
International Search Report and Written Opinion for PCT Application No. PCT/US2017/038552, dated Oct. 11, 2017, 3 pages. |
Notice of Allowance for U.S. Appl. No. 15/395,203, dated Apr. 10, 2018. |
Notice of Allowance for U.S. Appl. No. 15/721,829, dated Jan. 22, 2021. |
Notice of Allowance for U.S. Appl. No. 15/721,829, dated Sep. 11, 2020. |
Notice of Allowance for U.S. Appl. No. 16/055,602, dated Feb. 13, 2020. |
Notice of Allowance for U.S. Appl. No. 16/055,602, dated Oct. 28, 2019. |
Notice of Allowance for U.S. Appl. No. 16/513,345, dated Jun. 5, 2020. |
Notice of Allowance for U.S. Appl. No. 16/513,345, dated May 19, 2020. |
Notice of Allowance for U.S. Appl. No. 16/513,371, dated Jan. 31, 2020. |
Notice of Allowance for U.S. Appl. No. 16/513,371, dated Jun. 5, 2020. |
Notice of Allowance for U.S. Appl. No. 16/513,371, dated May 20, 2020. |
Office Action for U.S. Appl. No. 15/395,203, dated Dec. 1, 2017. |
Office Action for U.S. Appl. No. 15/721,829 dated Dec. 23, 2019. |
Office Action for U.S. Appl. No. 15/721,829, dated May 13, 2020. |
Office Action for U.S. Appl. No. 16/055,602 dated Mar. 27, 2019. |
Office Action for U.S. Appl. No. 16/055,602, dated Aug. 15, 2019. |
Office Action for U.S. Appl. No. 16/513,345, dated Jan. 31, 2020. |
Office Action for U.S. Appl. No. 17/015,479, dated Feb. 12, 2021. |
Artail, et al., “Speedy Cloud: Cloud Computing with Support for Hardware Acceleration Services”, 2017 IEEE, pp. 850-865. |
Caulfield, et al., “A Cloud-scale acceleration Architecture”, Microsoft Corp., Oct. 2016, 13 pages. |
Notice of Allowance for U.S. Appl. No. 16/055,602, dated Jun. 12, 2020. |
Notice of Allowance for U.S. Appl. No. 17/015,479, dated May 26, 2021. |
Corrected Notice of Allowability for U.S. Appl. No. 17/015,479, dated Jun. 3, 2021. |
Number | Date | Country | |
---|---|---|---|
20180150334 A1 | May 2018 | US |
Number | Date | Country | |
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62427268 | Nov 2016 | US |