Patent Application
20060229839
The present invention relates, in general, to the field of integrated circuit devices. More particularly, the present invention relates to a temperature sensing and monitoring technique for integrated circuit devices, particularly dynamic random access memories (DRAM).
Among the advantages of DRAMs over static random access memory (SRAM) and other integrated circuit data storage technologies is that their structure is very simple in that each cell typically comprises but a single small capacitor and an associated pass transistor. However, since these capacitors are made very small to provide maximum memory density and they can, under the best of circumstances, only hold a charge for a short period of time, they must be continually refreshed.
In essence, the circuitry to effectuate this refresh operation then serves to effectively read the contents of every cell in a DRAM array and refresh each one with a fresh “charge” before the charge leaks off and the data state is lost. In general, this “refreshing” is done by reading and restoring every “row” in the memory array whereby the process of reading and restoring the contents of each memory cell capacitor re-establishes the charge, and hence, the data state.
Another aspect of DRAM memory, whether stand-alone or embedded is that the frequency with which the cell contents must be refreshed is a function of device temperature. At lower operating temperatures, the memory need not be refreshed as frequently as at higher temperatures. Since this refresh operation adds to the overall latency in memory accesses, the ability to accurately sense the then current operating temperature and adjust the refresh of the memory to the lowest possible rate is highly desirable given the need for ever quicker “reads” and “writes” to the memory.
Conventional temperature sensing techniques for integrated circuit devices generally compare a constant voltage (or current) to a voltage (or current) that is proportional to temperature. Moreover, conventional techniques generally depend on current mirror transistors having a drain-to-source current that is essentially independent of the drain-to-source voltage. Implementations of specific temperature sensing techniques for certain integrated circuit devices are described, for example, in U.S. Pat. No. 6,157,244 issuing Dec. 5, 2000 for: “Power Supply Independent Temperature Sensor” and U.S. Pat. No. 6,531,911 issuing Mar. 11, 2003 for: “low-Power Band-Gap Reference and Temperature Sensor Circuit”.
The present invention discloses a temperature sensing and monitoring technique for integrated circuit devices incorporating the comparison of a voltage inversely proportional to temperature to a voltage proportional to temperature thereby increasing the differential voltage vs. temperature. These two voltages are designed to be equal at a given temperature and a comparison circuit produces a signal that changes from a logic level “high” to a logic level “low” at that given temperature. The inclusion of an additional transistor in each trip point current path forces the gate-to-source and drain-to-source voltage of current mirror transistors to be equal at the temperature trip points.
Particularly disclosed herein is a temperature sensing method for an integrated circuit device comprising: establishing a first voltage which is inversely proportional to a temperature of the device; also establishing a second voltage which is directly proportional to the temperature of the device; comparing the first and second voltages; and producing an output signal when said first and second voltages are substantially equal.
Further disclosed herein is an integrated circuit device comprising a first circuit for establishing a first voltage inversely proportional to a temperature of the device; an associated circuit for establishing a second voltage directly proportional to the temperature; and a comparator coupled to receive the first and second voltages, the comparator producing an output signal having a first state thereof when the first voltage is lower than the second voltage and a second state when the first voltage is higher than the second voltage.
The aforementioned and other features and objects of the present invention and the manner of attaining them will become more apparent and the invention itself will be best understood by reference to the following description of a preferred embodiment taken in conjunction with the accompanying drawings, wherein:
With reference now to
The gate terminals of N-channel transistors 106 and 108 are also coupled to the VSTART node as shown. The source terminals of transistors 106 and 108 are connected to circuit ground. A P-channel transistor 110 has its source terminal connected to VCCX and its gate terminal connected to the drain terminal of transistor 108. The drain terminal of transistor 110 is coupled to the source terminal of P-channel transistor 112 as well as to a node (line “A”) at which a voltage VLIM is taken. The drain terminal of transistor 112 is connected to the drain terminal of N-channel transistor 114, which has its source terminal connected to the emitter of PNP bipolar transistor 116 which has its base and collector terminals both connected to circuit ground. The drain terminal of transistor 114 is connected to its gate at node VNG and the voltage VD is taken at its source terminal. A capacitor connected N-channel transistor 118 has its gate connected to node VLIM and its drain and source terminals connected together at circuit ground.
A P-channel transistor 120 has its source terminal connected to node VLIM and its gate terminal connected to the gate terminal of transistor 112 at node VPG which is, in turn connected to the drain terminal of transistor 106 (line “B”). The drain terminal of transistor 120 is also connected to its gate terminal at line “B” as well as being connected to the drain terminal of N-channel transistor 122 which has its gate terminal connected to the gate and drain terminal of transistor 114 at node VNG. The source terminal of transistor 122 at node VRTOP is coupled through a resistor 124 (which in the embodiment shown may have a resistance of substantially 60K ohms) to the emitter terminal of another PNP bipolar transistor 126 (node VRBOT) which has its base and collector terminals also connected to circuit ground. In the embodiment illustrated, bipolar transistor 126 is constructed to be substantially ten times as large as corresponding bipolar transistor 116.
A P-channel transistor 128 has its source terminal connected to VCCX and its drain terminal connected to a node VPGS at the gate terminal of transistor 110 and the drain terminal of transistor 108. The drain terminal of N-channel transistor 130 is also connected to the drain terminal of transistor 128 while its gate terminal is connected to node VNG at the drain of transistor 114. The source terminal of transistor 130 is connected to the drain terminal of N-channel transistor 136 which has its source terminal connected to circuit ground and its gate terminal connected to VCCX.
In like manner, P-channel transistor 132 has its source terminal connected to VCCX and its gate terminal connected to its drain and the gate of transistor 128 at node VLPG. The drain terminal of transistor 132 is connected to the drain terminal of N-channel transistor 134 which has its source terminal also connected to the drain of transistor 136. The gate terminal of transistor 134 is connected to node VPG as also indicated as line “B”.
In essence, the interconnected transistors 112, 114, 120 and 122 comprise the voltage current mirror 140, with each device having a width-to-length ratio of substantially 2.0μ/2.0μ. The transistors 128, 130, 132, 134 and 136 comprise a differential amplifier 142, with all devices having a width-to-length ratio of substantially 4.0μ/0.4μ except for transistor 136 which may have a width-to-length ratio of substantially 0.5μ/50.0μ. The differential amplifier 142 functions to limit the voltage at VLIM to a level that results in VPG voltage being essentially equal to VNG.
Transistors 106 and 108 may have a width-to-length ratio of substantially 2.0μ/20.0μ, transistor 102 a width-to-length ratio of substantially 0.5μ/10.0μ, transistor 104 a width-to-length ratio of substantially 10.0μ/0.4μ, transistor 110 a width-to-length ratio of substantially 2.4μ/0.96μ while capacitor connected transistor 118 may have a width-to-length ratio of substantially 500.0μ/6.0μ.
With particular reference now to
Similarly, a P-channel transistor 158 has its source terminal connected to node VLIM and its gate terminal connected to node VPG. The drain terminal of transistor 158 is connected to the common-connected drain and gate terminals of N-channel 160 which has its source terminal (node V50) coupled to circuit ground through a resistor 162. In the representative embodiment illustrated, resistor 162 may have a value of substantially 522K ohms. Additionally, and in like manner, a P-channel transistor 164 has its source terminal connected to node VLIM and its gate terminal connected to node VPG. The drain terminal of transistor 164 is connected to the common-connected drain and gate terminals of N-channel 166 which has its source terminal (node V75) coupled to circuit ground through a resistor 168.
Also, in the representative embodiment illustrated, resistor 168 may have a value of substantially 438K ohms and the transistors 152, 154, 158, 160, 164 and 166 a width-to-length ratio of substantially 2.0μ/2.0μ. These latter devices are matched with the devices of the voltage current mirror 140 (
With reference additionally now to
The DAO node intermediate transistors 206 and 208 is connected to the input of a first complementary metal oxide semiconductor (CMOS) inverter comprising series connected P-channel transistor 212 and N-channel transistor 215 connected between VCC and circuit ground. Output of this inverter is connected to the input of another inverter comprising similarly connected P-channel transistor 216 and N-channel transistor 218. The output of this second inverter is then applied through two more series connected inverters 220 and 222 to be provided as a signal VOUT as one of VT1, VT2 or VT3 depending on the input signal VIN. Stated another way, the comparator circuit 200 is operative to compare the voltage VD (which is inversely proportional to temperature) to a selected one of the voltages V25, V50 or V75 at node VIN (which voltages are proportional to temperature) to produce a signal VOUT that changes from a logic level “high” to a logic level “low” at that given temperature.
In the embodiment of the comparator circuit 200 illustrated, transistors 202 and 206 may have a width-to-length ratio of substantially 4.0μ/0.4μ, transistors 204 and 208 a width-to-length ratio of substantially 2.0μ/0.4μ, transistor 210 a width-to-length ratio of substantially 0.5μ/25.0μ, transistors 212 and 216 a width-to-length ratio of substantially 0.5μ/10.0μ while transistors 214 and 218 may have a width-to-length ratio of substantially 0.5μ/20.0μ.
With reference additionally now to
With reference additionally now to
At 25° C., the voltage V25 equals the voltage at VD. This is true because the total voltage dropped across transistors 112 and 114 is equal to the voltage dropped across transistors 152 and 154. Since the voltage on the gate of transistor 112 is equal to the voltage on the gate of transistor 152, the current through transistors 112 and 152 will be equal causing the gate of transistor 154 to bias to the same voltage as the gate of transistor 114. At this point, transistor 112 and transistor 152 are identically biased as are transistors 114 and 154. Analogous conditions are true at 50° C. and 75° C. for V50 and V75 respectively and their associated transistors.
While there have been described above the principles of the present invention in conjunction with specific circuitry and voltage vs. temperature points, it is to be clearly understood that the foregoing description is made only by way of example and not as a limitation to the scope of the invention. Particularly, it is recognized that the teachings of the foregoing disclosure will suggest other modifications to those persons skilled in the relevant art. Such modifications may involve other features which are already known per se and which may be used instead of or in addition to features already described herein. Although claims have been formulated in this application to particular combinations of features, it should be understood that the scope of the disclosure herein also includes any novel feature or any novel combination of features disclosed either explicitly or implicitly or any generalization or modification thereof which would be apparent to persons skilled in the relevant art, whether or not such relates to the same invention as presently claimed in any claim and whether or not it mitigates any or all of the same technical problems as confronted by the present invention. The applicants hereby reserve the right to formulate new claims to such features and/or combinations of such features during the prosecution of the present application or of any further application derived therefrom.
